JP3296761B2 - Display device with built-in drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (TFT) using a polycrystalline semiconductor layer.
or) are arranged in a matrix on the display unit, and a driving circuit with a thin film transistor is also arranged on the periphery.

[0002]

2. Description of the Related Art In recent years, by using polycrystalline (poly) silicon (p-Si) as a channel layer of a TFT,
An LCD with a built-in drive circuit in which a matrix display portion and a peripheral drive circuit are formed on the same substrate has been developed. FIG. 4 is a circuit diagram showing a circuit configuration of the LCD. The central matrix circuit is a display unit. The gate line (G
L) and a drain line (DL) as a signal line are arranged vertically and horizontally, and a TFT (SE) is formed at the intersection. The TFT (SE) has a pixel capacitance (L
C) is connected to one electrode (display electrode) and one electrode of an auxiliary capacitance (SC) for retaining charges. The other electrode (counter electrode) of the pixel capacitor (LC) is formed of a common electrode formed entirely on another substrate opposed to the liquid crystal layer. That is, in the pixel capacitance (LC), a liquid crystal and a common electrode are partitioned by the display electrode, and a switching TFT (SE) is connected to the liquid crystal and the common electrode to form a display pixel.

A gate line (GD) is provided around the display section.
Driver (GD) that applies a scanning signal voltage to the gate
And a drain driver (DD) for applying a pixel signal voltage to the drain line (DL). The gate driver (GD) mainly includes a vertical shift register, and includes a vertical clock signal VCK and its inverted clock signal *.
VCK and a vertical start pulse VST are supplied. The drain driver (DD) mainly includes a horizontal shift register and a transfer gate for sampling, and includes an original picture signal VDS, a horizontal clock signal HCK, and an inverted clock signal * HCK generated by an external integrated circuit.
And a horizontal start pulse HST. Then, one gate line (GL) is selected by the gate driver (GD) according to the scanning signal, and one drain line (DL) is selected dot-sequentially by the drain driver (DD). The original image signal VDS is supplied to the display pixel 3 located at the intersection of the lines.

The gate driver (GD) and the drain driver (DD) are constituted by a TFT CMOS circuit, and are similar to the TFT (SE) in the pixel portion.
They are integrally formed on the same substrate using p-Si. FIG. 5 is a plan view showing the appearance of the LCD panel.
A gate line (GL) and a drain line (DL) are arranged in a matrix on a display unit 2 at the center of the substrate 1, and a display pixel 3 including a TFT (SE) and a pixel capacitor (LC) is arranged at an intersection thereof. . A gate driver (GD) and a drain driver (DD) are arranged around the periphery of the display unit 2 along the periphery of the substrate 1.
Electrode wires for transmitting various signals from the connection terminals 4 provided on the sides extend to the respective driver circuits. The original signal line 5 for transmitting the original image signal VDS therein is connected to the drain driver (D) from the connection terminal 4 along the periphery of the substrate 1.
D), and further extends between the end of the display unit 2 along the drain driver (DD) between the drain driver (DD) and the display unit 2. Reference numeral 6 denotes a transfer gate of the drain driver (DD), and reference numeral 7 denotes a precharge driver of the drain line (DL).

[0005] A light-shielding film 8 covering each drive circuit is arranged so as to prevent leakage of backlight emitted from the back of the LCD panel. The light-shielding film 8 arranged in a frame shape on the periphery of the substrate 1 has a margin for positioning with respect to the frame of the display window when the LCD panel is mainly fixed to the display window opened in the housing of the electronic device. And has a line width of, for example, 2.0 to 5.0 mm.

FIG. 6 is a sectional view showing the structure of the end of the substrate 1. As shown in FIG. A first substrate 1a on which a display pixel such as a TFT (SE) is formed; a counter electrode 9 of a pixel capacitor (LC);
Is bonded to the second substrate 1b on which the liquid crystal is formed by a seal material 10 with a gap therebetween, and the liquid crystal is sealed in the gap.
Will be retained. Reference numeral 11 denotes a flattening film, and 12 denotes a color filter. The original signal line 5 is connected to the first substrate 1.
a) between the display unit 2 and the drain driver (DD).

[0007]

However, while the liquid crystal has a dielectric constant of about 4 in a steady state, the liquid crystal has a property that the dielectric constant rises to about 13 when a voltage is applied by a display electrode. Therefore, there is a problem that the parasitic capacitances C1 and C2 inevitably formed between the original signal line 5 and the light shielding film 8 or between the original signal line 5 and the counter electrode 9 become so large that they cannot be ignored. I have.

Therefore, the resistance components and the parasitic capacitances C1 and C2 of the original image signal line 5 itself, the wiring capacitance of the selected drain line DL, the pixel capacitance (LC) of the selected display pixel 3 and the auxiliary capacitance (SC) ), An integration circuit is formed, and the parasitic capacitance increases as the distance from the supply source (connection terminal 4) of the original image signal VDS increases, so that the amount of delay and attenuation of the input original image signal VDS increases. In the display pixel 3 connected to the drain line (DL) far from the source, there is a defect that a contrast ratio is reduced, a luminance is reduced, and a ghost phenomenon that an image is displayed twice is caused. Naturally, this phenomenon is close-up because the larger the size of the substrate 1 is, the longer the distance of arranging the original image signal line 5 is. Therefore, the light-shielding film 8 itself is positively grounded (VSS) or the power supply. Although the potential (VDD) is not supplied, since it is capacitively coupled to a ground (VSS) line or the like extending below the light shielding film 8, the potential of the original signal line 5 becomes It is considered that a potential difference is generated.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to remove a light-shielding film from above at least a part of an original signal line extending along a drain driver. Reducing the parasitic capacitance with the light-shielding film is the first gist. Further, according to the present invention, an original image signal line is provided by a first extending portion extending between a drain driver and a display portion and a second extending portion extending between a drain driver and an end of a substrate. The original image signal is supplied to the first extended portion from a plurality of locations, and the light-shielding film is removed from above the second extended portion, so that the maximum delay amount of the original image signal can be reduced. The second gist is to prevent the increase of the parasitic capacitance due to the second extending portion.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail. FIG. 1 shows a liquid crystal display (LC) of the present invention.
FIG. 2 is a plan view showing a configuration of a (D panel). The substrate 21 is formed by laminating two transparent substrates made of quartz or non-alkali glass at an interval, and the short side 22 × the long side 23 forms a rectangle of, for example, 68 mm × 90 mm. Substrate 2
A display unit 24 is provided at the center of the display unit 24. A gate line GL to which a scanning signal is applied and a drain line DL to which an original image signal is applied are arranged at substantially the same pitch in a matrix. At the intersection of the gate line GL and the drain line DL, a TFT having a polysilicon semiconductor film as an active layer, a transparent display electrode made of an ITO (Indium-Tin-Oxide) film or the like, and a display pixel made of an auxiliary capacitor and the like 25 are arranged. A drain driver D composed of a TFT CMOS circuit is arranged along the long side 23 of the substrate 21 around the periphery of the substrate 21, that is, around the display section 24.
D, and a gate driver G also formed of a TFT CMOS circuit along the short side 22 of the substrate 21.
D are arranged on two opposing sides. The remaining 1 of the substrate 21
On the side, a precharge driver PD for precharging the drain line DL and various control circuits (not shown) are arranged.

A connection terminal 26 made of chromium (Cr), which is a metal for a gate of a TFT, is arranged on one side of the substrate 21. From the connection terminal 26, an aluminum electrode wiring for supplying various signals and a power supply voltage to each driver circuit extends along the periphery of the substrate 21. Of the electrode wirings extending in this manner, the original signal line 27 transmitting the original signal VDS extends from the connection terminal 26 along the short side 22 of the substrate 21 to the vicinity of the drain driver DD. The display unit 24 extends from end to end along the drain driver DD in parallel with the long side 23. In the case of a color LCD, three original image signal lines 27 extend at least for R, G, and B. The original signal line 27 branches into first and second extending portions 29 and 30 near one end (shown in FIG. 28) of the drain driver DD, and the branched first extending portion 29 is connected to the drain driver DD.
D, the second extending portion 30 extending from one end of the display portion 24 to the other end on the display portion 24 side and branching from the drain portion DD.
, Ie, a region between the drain driver DD and the end of the substrate 21 extends from one end of the display unit 24 to the other. The second extending portion 30 bypassing the drain driver DD is connected to the first extending portion 29 again near the other end of the drain driver DD (see FIG. 31).

Thus, a light-shielding film 32 covering each driver circuit is arranged on the periphery of the substrate 21 so as to prevent the light of the backlight emitted from the back of the LCD panel from leaking. The light-shielding film 32 is also arranged in a lattice pattern inside the display unit 24 so as to cover unnecessary portions except for the transparent electrode portion of the display pixel 25 (not shown). The light-shielding film 32 is connected to the drain driver DD and the original image signal line 27.
Of the original image signal line 27.
The extended portion 30 has its end retracted so as not to cover it.
As a result, the second extension 30 of the original signal line 27
The region extends from the end of the light shielding film 32 to the end of the substrate 21.

FIG. 2 is a sectional view showing a schematic structure of an end portion of the substrate 21. The substrate 21 is a first substrate 21 which is bonded and opposed to each other.
a and the second substrate 21b, both of which are joined at an interval by a sealing material 33 surrounding the periphery of the substrate 21, and the liquid crystal is sealed and held within the interval. Seal material 3
Reference numerals 3 are arranged on four sides along the periphery of the substrate 21. On the surface of the opposing surface 34 of the first substrate 21a, a TFT element is formed by a gate and a polysilicon semiconductor layer, a display electrode is formed by an ITO film or the like, and these are circuit-connected by an aluminum electrode or the like. Reference numeral 35 represents the TF.
A flattening film made of an acrylic resin or the like for flattening the surface by coating T or the like is shown, and the display electrode is formed on the flattening film 35. A second extension 30 of the original signal line 27 is formed of an aluminum electrode in a region between the sealing surface 33 and a region where the drain driver is disposed on the facing surface 34, and the region where the drain driver is disposed and the display unit are formed. The first extending portion 29 of the original image signal line 27 is formed with an aluminum electrode with a line width of 10 to 30 μm in a region between the first and second lines.

The facing surface 36 of the second substrate 21b of the substrate 21
A color filter 37 corresponding to each of R, G and B is formed at a position corresponding to the display electrode of the display pixel 25 on the surface of the light-shielding film 32 so as to be in contact with these color filters 37. (BM) is deposited. An upper part of the light shielding film 32 and the color filter 37 is covered with a flattening film 38 made of an acrylic resin or the like, and a counter electrode 39 made of ITO is formed on the flattening film 38. The counter electrode 39 is connected to the display unit 24.
And terminates near the end of the light-shielding film 32. The light-shielding film 32 covers the drain driver DD and the first extension 29, and the end thereof is receded toward the display unit 24 so as not to cover the second extension 30. .

The circuit configuration of the LCD panel is basically the same as that shown in FIG. Here, a detailed circuit near the drain driver DD will be described with reference to FIG. The drain driver DD includes a horizontal shift register 40, and the horizontal shift register 4
A control signal sequentially output from each output stage (S / R) of 0 is supplied to a control terminal of a transfer gate 41 for sampling arranged in a lower stage, and controls on / off of the transfer gate 41. Transfer gate 4
One of the terminals is connected to the first extending portion 29 of the original image signal line 27, and R, G, B original image signals VDR, VDG, VDB created by an external integrated circuit are supplied to each line. I have. The other terminal has display pixels 2 of R, G, and B, respectively.
The drain lines DL corresponding to the respective columns of the display section 24 in which 5 are arranged are connected. Horizontal shift register 40
The output of each output stage (S / R) is R,
In order to sample a pixel signal voltage to be supplied to each of the G and B pixels, the signal is supplied to three transfer gates 41 connected to each of the R, G and B original image signal lines 29. That is, the R, G, and B original image signals VDR, VDG, and VDB generated externally and given at the same time are sampled at the same time, and each drain line D is applied as a pixel signal voltage.
L.

As described above, due to the restriction that the transfer gate 41 controlled by the horizontal shift register 40 is connected between the original signal line 27 and the drain line DL, the first extending portion of the original signal line 27 is 29
Is placed on the display unit 24 side of the drain driver DD (more precisely, the horizontal shift register 40 of the drain driver DD). In order to clarify the position of the transfer gate 41, the transfer gate 41 is also shown in FIG.

Here, if the transfer gate 41 and the drain driver DD (horizontal shift register 40) are covered and the light-shielding film 32 is partially removed from above the first extending portion 29, the parasitic potential of the original signal line 27 is obtained. Capacity can be minimized. Thus, according to the above-described embodiment, the following operational effects can be obtained. (1) From above the original signal line 27, the conductive light shielding film 3
By removing 2, the parasitic capacitance between them can be reduced. Therefore, the capacitance component of the integration circuit formed by the original image signal line 27 can be reduced, whereby the delay and attenuation of the original image signal that occurs when the original image signal line 27 is drawn long can be reduced. (2) The original image signal line 27 is connected to the first and second extending portions 29,
By removing the light-shielding film 32 from above the second extending portion 30, no parasitic capacitance is generated in the second extending portion 30, so that the delay / attenuation amount of the original image signal can be reduced. Can be smaller. At this time, the delay / attenuation of the signal becomes maximum near the center (42 in FIG. 1) of the first extending portion 29, but the maximum attenuation is about half that of the conventional one by the second extending portion 30. Becomes Then, the first extending portion 2
9 is covered with a light-shielding film 32 and the second extending portion 30 is not covered, so that the pattern design is not forced.
In addition, it is possible to maintain a margin for positioning with respect to the display window of the electronic device.

The line width of the first extending portion 29 is
If the resistance of the second extending portion 30 is reduced by a method such as increasing the line width of the extending portion 30, the operation and effect of the present invention can be further increased.

[0019]

As is clear from the above description, by removing the conductive light-shielding film 32 from above the original signal line 27, the parasitic capacitance is reduced to prevent the delay and attenuation of the original signal. There is an advantage that the display quality can be improved over the entire display screen. Further, the original image signal line 27 is branched at the first and second extending portions 29 and 30 so that the maximum attenuation of the original image signal is halved, and the light shielding film 32 is removed from above the second extending portion 30. Accordingly, it is possible to prevent an increase in the parasitic capacitance due to the provision of the second extending portion 30. Therefore, the contrast ratio and the luminance are uniform over the entire display screen, and there is an advantage that the ghost phenomenon can be prevented and the display quality can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a liquid crystal display device of the present invention.

FIG. 2 is a cross-sectional view illustrating a cross-sectional structure of an end portion of a substrate 21.

FIG. 3 is a circuit diagram showing a drain driver circuit.

FIG. 4 is a circuit diagram illustrating a circuit configuration of a liquid crystal display device.

FIG. 5 is a plan view showing a conventional liquid crystal display device.

FIG. 6 is a cross-sectional view showing a substrate end of a conventional liquid crystal display device.

[Explanation of symbols]

GL Gate line DL Drain line DD Drain driver 21 Substrate 24 Display 26 Connection terminal 27 Original signal line 29 First extension of original signal line 30 Second extension of original signal line 32 Light shielding film

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/1345 G09F 9/00 346

Claims (4)

(57) [Claims] A first substrate facing the first substrate and a second substrate facing the first substrate; a plurality of gate lines and a plurality of drain lines intersecting each other on a display unit on a surface of the first substrate facing the first substrate; Forming a display pixel at each intersection of the gate line and the drain line, arranging the display pixels in a matrix, and arranging a drain driver for applying an original image signal to the drain line at a periphery of the facing surface; An original signal line extending from the connection terminal provided on the peripheral portion of the opposing surface of the substrate along the peripheral portion, and further extending from the end of the display portion along the drain driver, A light-shielding film that covers at least a peripheral portion of the first substrate is disposed on the facing surface of the second substrate; and at least a portion of a portion of the original signal line that extends along the drain driver. Or A display device with a built-in drive circuit, wherein the light-shielding film is eliminated. 2. The image signal line according to claim 1, wherein the original signal line extends in the vicinity of the display section, and a second extension section extends between the drain driver and an end of the substrate. And the second extending portion bypasses the drain driver and is connected to the first extending portion again. The upper portion of the first extending portion is covered with the light shielding film. Second
2. The display device with a built-in drive circuit according to claim 1, wherein the light-shielding film is removed from above the extending part of the driving circuit. 3. The display device with a built-in drive circuit according to claim 1, wherein said light shielding film is made of chromium (Cr). 4. A first and a second substrate are opposed to each other with a liquid crystal interposed therebetween, and a plurality of gate lines and a plurality of drain lines are arranged on a display unit on an opposite surface of the first substrate so as to intersect with each other. Forming a display pixel at each intersection of the gate line and the drain line, arranging the display pixels in a matrix, and arranging a drain driver for applying an original image signal to the drain line at a periphery of the facing surface; An original signal line extending from the connection terminal provided on the peripheral portion of the opposing surface of the substrate along the peripheral portion, and further extending from the end of the display portion along the drain driver, In a liquid crystal display device in which a light-shielding film covering at least a peripheral portion of the first substrate is disposed on a surface facing the second substrate, a portion of the original image signal line extending along the drain driver is provided. A display device with a built-in drive circuit, wherein at least a part of the display device extends in a region between an end of the light shielding film and an end of the substrate.