JP3245070B2 - 半導体構造、積層コンデンサ・セル、ｄｒａｍ、電気的分離方法、及び半導体構造作成方法 - Google Patents

半導体構造、積層コンデンサ・セル、ｄｒａｍ、電気的分離方法、及び半導体構造作成方法

Info

Publication number
JP3245070B2
JP3245070B2 JP24438596A JP24438596A JP3245070B2 JP 3245070 B2 JP3245070 B2 JP 3245070B2 JP 24438596 A JP24438596 A JP 24438596A JP 24438596 A JP24438596 A JP 24438596A JP 3245070 B2 JP3245070 B2 JP 3245070B2
Authority
JP
Japan
Prior art keywords
conductor
lower conductor
semiconductor structure
layer
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP24438596A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09129851A (ja
Inventor
ジョン・エドワード・クローニン
ジョン・ケニス・デプロス
ヒン・ウォン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH09129851A publication Critical patent/JPH09129851A/ja
Application granted granted Critical
Publication of JP3245070B2 publication Critical patent/JP3245070B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP24438596A 1995-10-06 1996-09-17 半導体構造、積層コンデンサ・セル、ｄｒａｍ、電気的分離方法、及び半導体構造作成方法 Expired - Fee Related JP3245070B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/540387 1995-10-06
US08/540,387 US5602051A (en) 1995-10-06 1995-10-06 Method of making stacked electrical device having regions of electrical isolation and electrical connection on a given stack level

Publications (2)

Publication Number Publication Date
JPH09129851A JPH09129851A (ja) 1997-05-16
JP3245070B2 true JP3245070B2 (ja) 2002-01-07

Family

ID=24155241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24438596A Expired - Fee Related JP3245070B2 (ja) 1995-10-06 1996-09-17 半導体構造、積層コンデンサ・セル、ｄｒａｍ、電気的分離方法、及び半導体構造作成方法

Country Status (6)

Country Link
US (2) US5602051A (enExample)
EP (1) EP0767493A2 (enExample)
JP (1) JP3245070B2 (enExample)
KR (1) KR100214915B1 (enExample)
SG (1) SG43376A1 (enExample)
TW (1) TW318269B (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08293543A (ja) * 1995-04-25 1996-11-05 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6429473B1 (en) * 1996-07-30 2002-08-06 International Business Machines Corporation DRAM cell with stacked capacitor self-aligned to bitline
JPH10173046A (ja) * 1996-12-10 1998-06-26 Sony Corp 半導体装置の製造方法
JPH10189898A (ja) * 1996-12-24 1998-07-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3577195B2 (ja) 1997-05-15 2004-10-13 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6104054A (en) * 1998-05-13 2000-08-15 Texas Instruments Incorporated Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies
FR2785720B1 (fr) * 1998-11-05 2003-01-03 St Microelectronics Sa Fabrication de memoire dram et de transistors mos
JP3626058B2 (ja) * 2000-01-25 2005-03-02 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US6507063B2 (en) 2000-04-17 2003-01-14 International Business Machines Corporation Poly-poly/MOS capacitor having a gate encapsulating first electrode layer
JP3953715B2 (ja) * 2000-07-31 2007-08-08 富士通株式会社 半導体装置及びその製造方法
US6563162B2 (en) * 2001-03-21 2003-05-13 Samsung Electronics Co., Ltd. Semiconductor memory device for reducing parasitic bit line capacitance and method of fabricating the same
US20040163445A1 (en) * 2002-10-17 2004-08-26 Dimeo Frank Apparatus and process for sensing fluoro species in semiconductor processing systems
US7080545B2 (en) * 2002-10-17 2006-07-25 Advanced Technology Materials, Inc. Apparatus and process for sensing fluoro species in semiconductor processing systems
US7296458B2 (en) * 2002-10-17 2007-11-20 Advanced Technology Materials, Inc Nickel-coated free-standing silicon carbide structure for sensing fluoro or halogen species in semiconductor processing systems, and processes of making and using same
KR100797896B1 (ko) * 2004-11-12 2008-01-24 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 다양한 동작 전압들을 갖는 집적 회로들을 절연시키기 위한반도체 구조
KR100668833B1 (ko) * 2004-12-17 2007-01-16 주식회사 하이닉스반도체 반도체소자의 캐패시터 제조방법
US20060211253A1 (en) * 2005-03-16 2006-09-21 Ing-Shin Chen Method and apparatus for monitoring plasma conditions in an etching plasma processing facility
US10147735B2 (en) * 2015-03-13 2018-12-04 Toshiba Memory Corporation Semiconductor memory device and production method thereof
KR102490277B1 (ko) * 2017-09-26 2023-01-18 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR20230067339A (ko) 2021-11-09 2023-05-16 삼성전자주식회사 집적회로 소자

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237528A (en) * 1982-11-04 1993-08-17 Hitachi, Ltd. Semiconductor memory
US5214496A (en) * 1982-11-04 1993-05-25 Hitachi, Ltd. Semiconductor memory
JP2602219B2 (ja) * 1987-02-06 1997-04-23 株式会社日立製作所 半導体記憶装置
KR920005632B1 (ko) * 1987-03-20 1992-07-10 가부시기가이샤 히다찌세이사꾸쇼 다층 산화 실리콘 질화 실리콘 유전체의 반도체장치 및 그의 제조방법
US5196910A (en) * 1987-04-24 1993-03-23 Hitachi, Ltd. Semiconductor memory device with recessed array region
JPH0821682B2 (ja) * 1987-04-24 1996-03-04 株式会社日立製作所 半導体装置の製造方法
US5264712A (en) * 1989-03-20 1993-11-23 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
JP2590171B2 (ja) * 1988-01-08 1997-03-12 株式会社日立製作所 半導体記憶装置
US5140389A (en) * 1988-01-08 1992-08-18 Hitachi, Ltd. Semiconductor memory device having stacked capacitor cells
JPH0414868A (ja) * 1990-05-09 1992-01-20 Hitachi Ltd 半導体記憶装置とその製造方法
JPH04342164A (ja) * 1991-05-20 1992-11-27 Hitachi Ltd 半導体集積回路装置の形成方法
US5338700A (en) * 1993-04-14 1994-08-16 Micron Semiconductor, Inc. Method of forming a bit line over capacitor array of memory cells
US5478772A (en) * 1993-04-02 1995-12-26 Micron Technology, Inc. Method for forming a storage cell capacitor compatible with high dielectric constant materials
US5340765A (en) * 1993-08-13 1994-08-23 Micron Semiconductor, Inc. Method for forming enhanced capacitance stacked capacitor structures using hemi-spherical grain polysilicon
KR970000229B1 (ko) * 1993-08-30 1997-01-06 현대전자산업 주식회사 디램 캐패시터의 제조방법

Also Published As

Publication number Publication date
US5804853A (en) 1998-09-08
TW318269B (enExample) 1997-10-21
KR970024220A (ko) 1997-05-30
SG43376A1 (en) 1997-10-17
US5602051A (en) 1997-02-11
EP0767493A2 (en) 1997-04-09
JPH09129851A (ja) 1997-05-16
KR100214915B1 (ko) 1999-08-02

Similar Documents

Publication Publication Date Title
JP3245070B2 (ja) 半導体構造、積層コンデンサ・セル、ｄｒａｍ、電気的分離方法、及び半導体構造作成方法
US7510963B2 (en) Semiconductor device having multilayer interconnection structure and manufacturing method thereof
US7342275B2 (en) Semiconductor device and method of manufacturing the same
US5879986A (en) Method for fabrication of a one gigabit capacitor over bit line DRAM cell with an area equal to eight times the used minimum feature
US8022455B2 (en) Method of fabricating semiconductor device for reducing parasitic capacitance between bit lines and semiconductor device fabricated thereby
US7807569B2 (en) Method of manufacturing a contact structure for a semiconductor device
US5702969A (en) Buried bit line DRAM cells and fabricating methods therefor
US6573551B1 (en) Semiconductor memory device having self-aligned contact and fabricating method thereof
US20020024093A1 (en) Semiconductor device with self-aligned contact structure employing dual spacers and method of manufacturing the same
US6969882B2 (en) Interconnect line selectively isolated from an underlying contact plug
US6300191B1 (en) Method of fabricating a capacitor under bit line structure for a dynamic random access memory device
CN116075153B (zh) 半导体结构及其制备方法
US6953744B2 (en) Methods of fabricating integrated circuit devices providing improved short prevention
KR100273987B1 (ko) 디램 장치 및 제조 방법
JP3594213B2 (ja) 接続部を形成する方法および半導体チップ
US7074725B2 (en) Method for forming a storage node of a capacitor
US7473953B2 (en) Method for fabricating metallic bit-line contacts
JP2000232207A (ja) 半導体装置およびその製造方法
US20220271042A1 (en) Dynamic random access memory and method of manufacturing the same
JP2000049302A (ja) 半導体装置およびその製造方法
JP2969789B2 (ja) 半導体記憶装置の製造方法
JPH11330238A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees