JP3236782B2 - Ceramic substrate, method of manufacturing the same, and divided circuit board - Google Patents

Ceramic substrate, method of manufacturing the same, and divided circuit board

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Publication number
JP3236782B2
JP3236782B2 JP22701396A JP22701396A JP3236782B2 JP 3236782 B2 JP3236782 B2 JP 3236782B2 JP 22701396 A JP22701396 A JP 22701396A JP 22701396 A JP22701396 A JP 22701396A JP 3236782 B2 JP3236782 B2 JP 3236782B2
Authority
JP
Japan
Prior art keywords
groove
insulating layer
electrode
molded body
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP22701396A
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Japanese (ja)
Other versions
JPH1070364A (en
Inventor
則光 深水
譲 松本
道信 中宮
晃 井本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
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Kyocera Corp
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Priority to JP22701396A priority Critical patent/JP3236782B2/en
Publication of JPH1070364A publication Critical patent/JPH1070364A/en
Application granted granted Critical
Publication of JP3236782B2 publication Critical patent/JP3236782B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To inhibit separation of end face electrodes from a split insulating base body and to make it possible to enhance the reliability of the connection of the end face electrodes with the split insulating base body by a method wherein split grooves for splitting the split insulating base body in each unit block are formed in such a way that the grooves pass through between the end parts of two horseshoe-shaped conductive members, which are used as the end face electrodes and oppose to each other. SOLUTION: End face electrodes 2 are formed at 10 places in total on the four side surfaces of a split circuit board 1. Anchor parts 17 formed on the board 1 are respectively connected with these electrodes 2. A surface electrode 3 is formed on the surface of the board 1 and chip components 4, such as a resistor and a capacitor, are connected with this electrode 3. Moreover, a cavity part 5 is formed in the board 1 a semiconductor base chip 6 is housed in this cavity part 5 and the chip 6 is connected with the electrode 3 through wires. Such the split circuit board 1 is obtained by splitting a ceramic board, which is formed by aggregating these split circuit boards 1, along split grooves.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、単位ブロック毎に
分割した際にはそれぞれが複数の端面電極を有する分割
回路基板となるセラミック基板及びその製造方法並びに
分割回路基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic substrate which becomes a divided circuit board having a plurality of end electrodes when divided into unit blocks, a method of manufacturing the same, and a divided circuit board.

【０００２】[0002]

【従来技術】近年、電子機器は小型軽量化、携帯化が進
んでおり、それに用いられる回路ブロックもその動向に
呼応する形で、小型軽量薄型化、表面実装化、複合化が
押し進められている。2. Description of the Related Art In recent years, electronic devices have become smaller, lighter and more portable, and the circuit blocks used therein have been reduced in size, weight, and thickness, surface-mounted, and composited in accordance with the trend. .

【０００３】このような動向の中で、セラミック回路基
板は、その優れた放熱性や低誘電損失等の特徴から従来
より多用されており、表面実装用ハイブリッドＩＣを中
心にして幅広く応用されてきた。[0003] In such a trend, ceramic circuit boards have been widely used because of their excellent heat dissipation properties and low dielectric loss, and have been widely applied mainly to hybrid ICs for surface mounting. .

【０００４】従来、表面実装用ハイブリッドＩＣはセラ
ミック回路基板に半田接合されて用いられている。そし
て、その接合確認と信頼性維持の観点から、セラミック
回路基板は端面電極を有する構造とされている。その端
面電極の構造を製造方法の観点からみると、大別して３
種類の製造方法がある。Conventionally, hybrid ICs for surface mounting are used by being soldered to a ceramic circuit board. The ceramic circuit board has an end face electrode from the viewpoints of joining confirmation and maintaining reliability. From the viewpoint of the manufacturing method, the structure of the end face electrode can be roughly classified into 3
There are different types of manufacturing methods.

【０００５】まずスル−ホ−ル厚膜構造と呼ばれる構造
で、既に端面電極用のスル−ホ−ルが形成された未焼成
もしくは既焼成のセラミック基板に吸引等の技術を併用
し、厚膜印刷技術等により導電性ペ−ストをスル−ホ−
ル内壁面にコーティングし、焼き付ける方法により達成
される構造である。本方法の利点は基板を多数個取りで
処理出来る為、即ち、単位ブロック毎に分割した際には
それぞれが複数の端面電極を有する分割回路基板とな
り、工数削減に有利である。[0005] First, in a structure called a through-hole thick film structure, an unfired or fired ceramic substrate on which a through-hole for an end face electrode has already been formed is combined with a technique such as suction to form a thick film. Conductive paste is converted to sulfo by printing technology, etc.
This is a structure achieved by a method of coating and baking on the inner wall surface of the fuel tank. The advantage of this method is that a plurality of substrates can be processed, that is, when divided into unit blocks, each becomes a divided circuit substrate having a plurality of end face electrodes, which is advantageous in reducing the number of steps.

【０００６】第２の構造は単独形成構造と呼ばれる構造
で、単位ブロックに分割された分割回路基板に、基本的
に１端面ずつ厚膜印刷技術等を用いて端面電極をパタ−
ンニング、焼き付けする方法で達成される構造である。
本方法の利点は実装投影面積でみたときにスルーホール
によるデッドスペースがなく、小型化に適した点であ
る。[0006] The second structure is a so-called single structure, in which end electrodes are patterned on a divided circuit board divided into unit blocks, basically using a thick film printing technique or the like.
This is a structure achieved by lining and baking.
The advantage of this method is that there is no dead space due to a through hole when viewed in a mounting projection area, and the method is suitable for miniaturization.

【０００７】第３の構造は第１の構造を応用したもので
あり、セラミック基板が多層化されて構成されている
際、その未焼成のグリーンシート１層毎にスルーホール
を形成し、該スルーホールの内壁面に導電性ペ−ストを
コーティングし、該スルーホール厚膜構造をとったもの
を積層一体化することにより達成される構造である。こ
の利点は内部配線と端面電極の接合がとり易い点にあ
る。The third structure is an application of the first structure. When the ceramic substrate is formed in a multilayer structure, a through hole is formed for each unfired green sheet, and the through hole is formed. This structure is achieved by coating a conductive paste on the inner wall surface of the hole and laminating and integrating the through-hole thick film structure. This advantage is in that the connection between the internal wiring and the end face electrode can be easily made.

【０００８】[0008]

【発明が解決しようとする課題】しかしながら、上記３
種の製造方法による構造は各々以下のような欠点があっ
た。即ち、第１のスル−ホ−ル厚膜構造では、セラミッ
ク基板が内部配線を有していた場合、内部配線と端面電
極の接続信頼性に欠ける。未焼成のセラミック基板が対
象であるならば、それにパンチング工法等によりスル−
ホ−ルを形成する必要があるが、形成時に内部配線が崩
れて端面電極との接点がとれにくい。However, the above 3)
Each of the structures according to the various manufacturing methods has the following disadvantages. That is, in the first through-hole thick film structure, when the ceramic substrate has the internal wiring, the connection reliability between the internal wiring and the end face electrode is lacking. If the target is an unfired ceramic substrate, the through-hole is punched by a punching method or the like.
Although it is necessary to form a hole, the internal wiring collapses during the formation, making it difficult to make contact with the end face electrode.

【０００９】また、既焼成のセラミック回路基板が対象
であるならば、内部配線に含まれる収縮調整用のフラッ
クス成分等がフリー面であるスルホール内壁面に浮き上
がり、端面電極との接合が難しいという課題が生じる。
この課題を解決する為に、エッチング処理等を行うこと
があるが、本処理はセラミッスを腐食する可能性があ
り、且つコストアップにつながる。また、幅の広い端面
電極が必要な場合、フラックス成分等がフリー面である
スルホール内壁面に浮き上がるため、必要な幅を完全に
コーティングすることは難しい。Further, if a fired ceramic circuit board is the target, a flux component or the like for adjusting shrinkage contained in the internal wiring floats on the inner wall surface of the through hole which is a free surface, and it is difficult to join the end surface electrode. Occurs.
In order to solve this problem, an etching process or the like may be performed, but this process may corrode the ceramics and leads to an increase in cost. Further, when a wide end face electrode is required, it is difficult to completely coat the required width because a flux component and the like float on the inner wall surface of the through hole which is a free surface.

【００１０】第２の単独形成構造では、端面を露出させ
る為に、多数個取りが出来ない。従ってセラミック回路
基板の表面に部品を実装する際、実装効率を大きく低下
させてしまう。In the second single formation structure, since the end face is exposed, a large number of pieces cannot be formed. Therefore, when components are mounted on the surface of the ceramic circuit board, the mounting efficiency is greatly reduced.

【００１１】第３の構造も第１の構造と同様に端面電極
の幅が広くなると不適切になる。即ち、この構造では、
スルーホール内壁面のみにコーティングすることが困難
であり、一方、グリーンシートに形成されたスルーホー
ルに導体ペーストを充填する場合には、導体ペーストを
スルーホール内壁面のみに残すには導体ペーストの除去
作業が必要となり、また、導体ペーストをそのまま残し
た場合には導体ペーストが余分に必要となるという問題
があった。さらに、一層毎にパンチング等によりスルー
ホールを形成していたため、スルーホール内壁面が凹凸
となり、端面電極表面も凹凸になりやすいという問題が
あった。As in the first structure, the third structure becomes unsuitable when the width of the end face electrode is increased. That is, in this structure,
It is difficult to coat only the inner wall surface of the through hole, but when the conductive paste is filled in the through hole formed in the green sheet, it is necessary to remove the conductive paste to leave the conductive paste only on the inner wall surface of the through hole. There is a problem that an operation is required, and if the conductor paste is left as it is, an extra conductor paste is required. Further, since the through holes are formed for each layer by punching or the like, there is a problem that the inner wall surface of the through holes becomes uneven, and the surface of the end face electrode is also likely to be uneven.

【００１２】また、第１および第３の構造では、図８に
示すように、絶縁基体４０の表面に形成された分割溝４
１が、分割した際には端面電極となる円筒状の導電部材
４３を通過していたため、分割溝４１で分割すると導電
部材４３を直接切断することになり、導電部材４３に分
割する際の力が作用し、導電部材４３が剥がれ落ちる
等、導電部材４３と絶縁基体４０の接続信頼性が低下す
るという問題があった。Further, in the first and third structures, as shown in FIG.
When the substrate 1 was divided, it passed through the cylindrical conductive member 43 serving as an end surface electrode. Therefore, when the substrate 1 was divided by the dividing groove 41, the conductive member 43 was directly cut, and the force required to divide the conductive member 43 was reduced. Act, and the connection reliability between the conductive member 43 and the insulating base 40 is reduced, such as the conductive member 43 peeling off.

【００１３】さらに、従来から種々の端面構造や導体形
状が用いられてきたが、金型を用いるパンチング工法に
より端面電極を作成した場合、円及び楕円等の単純形状
による設計を強いられ、導電部材４３と絶縁基体４０の
接続信頼性や量産性に優れた端面構造が得られなった。Furthermore, various end face structures and conductor shapes have conventionally been used. However, when end face electrodes are formed by a punching method using a mold, design using a simple shape such as a circle and an ellipse is forced, and a conductive member is formed. An end face structure excellent in connection reliability and mass productivity between the insulating substrate 43 and the insulating base 40 was not obtained.

【００１４】さらにまた、上記第１乃至第３の構造にお
いては、絶縁基体４０の凹部表面に単に導電部材が積層
されている状態であり、絶縁基体４０の凹部から導電部
材が剥離し易いという問題があった。Furthermore, in the first to third structures, the conductive member is simply laminated on the surface of the concave portion of the insulating base 40, and the conductive member is easily peeled off from the concave portion of the insulating base 40. was there.

【００１５】[0015]

【課題を解決するための手段】本発明のセラミック基板
は、セラミックスからなる絶縁層を複数積層してなる絶
縁基体と、前記絶縁基体表面に形成された分割溝とを有
し、該分割溝で分割した際にそれぞれが内部配線と複数
の端面電極を有する分割回路基板となるセラミック基板
であって、前記絶縁基体はその厚み方向に形成され、か
つ前記分割溝上に形成された貫通孔を有し、該貫通孔の
内面に、前記分割回路基板の端面電極となる一対の馬蹄
形状の導電部材を形成するとともに、該一対の導電部材
の端部を対向させ、前記一対の導電部材の対向する端部
間に前記分割溝が形成された突出部を形成し、且つ前記
導電部材と接続されるアンカー部を前記分割回路基板と
なる領域に前記絶縁基体の厚み方向に形成してなるもの
である。SUMMARY OF THE INVENTION A ceramic substrate according to the present invention has an insulating substrate formed by laminating a plurality of insulating layers made of ceramics, and a dividing groove formed on the surface of the insulating substrate. A ceramic substrate that becomes a divided circuit board each having an internal wiring and a plurality of end face electrodes when divided, wherein the insulating base is formed in a thickness direction thereof, and has a through hole formed on the division groove. Forming a pair of horseshoe-shaped conductive members serving as end surface electrodes of the divided circuit board on the inner surface of the through-hole, with the ends of the pair of conductive members facing each other, and opposing ends of the pair of conductive members. A projection having the division groove formed between the parts is formed, and an anchor connected to the conductive member is formed in a region of the divisional circuit board in a thickness direction of the insulating base.

【００１６】また、本発明のセラミック基板の製造方法
は、セラミックスからなる絶縁層を複数積層してなる絶
縁基体と、前記絶縁基体表面に形成された分割溝とを有
し、該分割溝で分割した際にそれぞれが内部配線と複数
の端面電極を有する分割回路基板となるセラミック基板
の製造方法であって、セラミックスからなる絶縁層材
料、光硬化可能なモノマー、有機バインダを含有するス
リップ材を薄層化し乾燥して絶縁層成形体を形成する工
程と、該絶縁層成形体の表面に前記端面電極およびこの
端面電極に接続されるアンカー部の形成位置を除いて露
光処理を施す工程と、露光処理を施した前記絶縁層成形
体を現像処理して、端面電極を形成する位置に一対の馬
蹄形状の端面電極用貫通溝をその端部同士が対向するよ
うに形成するとともに、前記端面電極用貫通溝と連続す
るアンカー部用貫通溝を形成する工程と、該端面電極用
貫通溝およびアンカー部用貫通溝内に導電性ペーストを
充填する工程と、前記絶縁層成形体の表面に導電性ペー
ストを印刷して内部配線パターンを形成する工程と、前
記端面電極用貫通溝およびアンカー部用貫通溝内に導電
性ペーストを充填した前記絶縁層成形体に露光処理前の
絶縁層成形体を積層する工程と、露光処理から積層まで
の工程を繰り返して形成された積層成形体の表面に、前
記分割回路基板毎に分割するための分割溝を前記一対の
馬蹄形状の端面電極用貫通溝の間を通過するように形成
する工程と、該分割溝が形成された積層成形体を焼成す
る工程とを具備する方法である。Further, a method of manufacturing a ceramic substrate according to the present invention has an insulating substrate formed by laminating a plurality of insulating layers made of ceramics, and a dividing groove formed on the surface of the insulating substrate. A method of manufacturing a ceramic substrate, which becomes a divided circuit board having internal wiring and a plurality of end face electrodes when performing the above method, wherein a slip material containing a ceramic insulating layer material, a photocurable monomer, and an organic binder is thinned. Layering and drying to form an insulating layer molded body, exposing the surface of the insulating layer molded body to an exposure process excluding the formation positions of the end face electrodes and anchor portions connected to the end face electrodes, The processed insulating layer molded body is subjected to a development process, and a pair of horseshoe-shaped end surface electrode through grooves are formed at positions where the end surface electrodes are formed so that the end portions thereof face each other. Forming a through groove for an anchor portion continuous with the through groove for an end surface electrode, filling a conductive paste into the through groove for an end surface electrode and the through groove for an anchor portion, and forming the insulating layer molded body. A step of printing a conductive paste on the surface to form an internal wiring pattern; and forming an insulating layer before the exposure treatment on the insulating layer molded body filled with the conductive paste in the through-holes for the end face electrodes and the through-grooves for the anchor portion. A step of laminating the molded body and a dividing groove for dividing the divided circuit boards for each of the divided circuit boards are formed on the surface of the laminated molded body formed by repeating the steps from exposure processing to lamination for the pair of horseshoe-shaped end face electrodes. This is a method including a step of forming the laminate so as to pass between the through grooves and a step of firing the laminated molded body in which the divided grooves are formed.

【００１７】さらに、本発明の分割回路基板は、分割絶
縁基体の外周面にその厚み方向に形成された凹部に、該
凹部に沿って端面電極を形成してなる分割回路基板にお
いて、前記凹部に、前記端面電極の端部を被覆する突出
部を一体に設けてなるとともに、前記端面電極に接続さ
れるアンカー部を前記分割絶縁基体に厚み方向に設けて
なるものである。Further, according to the present invention, there is provided a divided circuit board comprising: a recess formed in an outer peripheral surface of a divided insulating base in a thickness direction thereof; and an end surface electrode formed along the recess. A projection for covering an end of the end face electrode is integrally provided, and an anchor connected to the end face electrode is provided on the divided insulating base in a thickness direction.

【００１８】尚、本発明のセラミックスからなる絶縁層
において、セラミックとはガラスセラミックも含む意味
であり、絶縁層とは誘電体層も含む意味である。分割し
て基板を作製する場合もあるが、分割して電子部品を作
製する場合も含む。In the insulating layer made of the ceramic of the present invention, the term "ceramic" includes glass ceramics, and the term "insulating layer" includes a dielectric layer. In some cases, the substrate is manufactured by division, and in other cases, the electronic component is manufactured by division.

【００１９】[0019]

【作用】本発明のセラミック基板によれば、単位ブロッ
ク毎に分割する為の分割溝を、端面電極となる相向かい
合う２つの馬蹄形状の導電部材の端部間を通るように形
成したため、分割溝に沿って分割しても、端面電極とな
る導電部材を直接分割することがなくなり、さらにアン
カー部により導電部材が分割絶縁基体に強固に固定され
るため、分割絶縁基体からの端面電極の剥がれが抑制さ
れ、この端面電極と分割絶縁基体との接続信頼性を向上
することができる。According to the ceramic substrate of the present invention, since the dividing groove for dividing into unit blocks is formed so as to pass between the ends of two opposed horseshoe-shaped conductive members serving as end face electrodes, the dividing groove is formed. Even if it is divided along, the conductive member to be the end face electrode will not be directly divided, and the conductive member is firmly fixed to the divided insulating base by the anchor portion, so that the end face electrode is peeled from the divided insulating base. Thus, the connection reliability between the end face electrode and the divided insulating substrate can be improved.

【００２０】また、内部配線と端面電極の接続信頼性が
良好であり、製造工数も少なく、多数個取りの可能なセ
ラミック基板が実現可能となる。更に、多数個取りがで
きることから、セラミック基板の表面に部品を実装する
際に実装効率も高くなるという利点があげられる。Further, the reliability of connection between the internal wiring and the end face electrode is good, the number of manufacturing steps is small, and a ceramic substrate which can be formed in a large number can be realized. Furthermore, since a large number of devices can be formed, there is an advantage that mounting efficiency is improved when components are mounted on the surface of the ceramic substrate.

【００２１】さらに、分割溝に沿って分割して得られた
本発明の分割回路基板では、分割絶縁基体の外周面に形
成された凹部の内方に突出した突出部により、馬蹄形状
の端面電極の端部が被覆されることになり、端面電極が
分割回路基板の外周面には露出せず、外部から直接的に
力が作用するようなことが殆どなく、分割回路基板の取
り扱い時に端面電極が剥がれ落ちる等の問題も改善され
る。さらに、アンカー部により端面電極が分割回路基板
に強固に固定されることになるため、端面電極の剥がれ
をさらに防止することができる。Further, in the divided circuit board of the present invention obtained by dividing along the dividing groove, the horseshoe-shaped end face electrode is formed by the projecting portion projecting inward from the concave portion formed on the outer peripheral surface of the divided insulating base. Is covered, the end face electrode is not exposed to the outer peripheral surface of the divided circuit board, and there is almost no possibility that a force is directly applied from the outside, and the end face electrode is handled when the divided circuit board is handled. Problems such as peeling off are also improved. Further, since the end face electrode is firmly fixed to the divided circuit board by the anchor portion, peeling of the end face electrode can be further prevented.

【００２２】本発明のセラミック基板の製造方法では、
端面電極を絶縁層の厚み方向に、絶縁層一層毎に形成す
る発想は、従来の技術で説明した第３の方法と基本的に
同様である。但し、第３の方法のようにスルーホールを
形成した場合と異なり、端面電極に相当する部分（端面
電極用貫通溝）に端面電極導体を埋め込むような形成で
あることが特徴である。スルーホール方式では、埋め込
まれた導体が剥離するという問題により製作不能であっ
た、例えば１ｍｍの厚みの基板の端面に１ｍｍの幅の端
面電極を形成するといった幅広の端面電極形成が可能に
なる。In the method for manufacturing a ceramic substrate according to the present invention,
The idea of forming the end face electrodes in the thickness direction of the insulating layer for each insulating layer is basically the same as the third method described in the related art. However, unlike the case where the through hole is formed as in the third method, the feature is that the end surface electrode conductor is embedded in a portion corresponding to the end surface electrode (through hole for the end surface electrode). In the through-hole method, a wide end face electrode can be formed, for example, an end face electrode having a width of 1 mm is formed on an end face of a substrate having a thickness of 1 mm, which cannot be manufactured due to a problem that an embedded conductor is separated.

【００２３】[0023]

【発明の実施の形態】本発明のセラミック基板は、一対
の馬蹄形状の導電部材を、絶縁基体に形成された分割溝
を挟んで端部同士が対向するように所定間隔をおいて形
成してなるものである。本発明のセラミック基板の絶縁
基体は、セラミックまたはガラスセラミックからなる絶
縁層を複数積層して構成されており、これらの絶縁層の
間には内部配線が形成されている。そして、このセラミ
ック基板の表面には、分割溝が形成されており、この分
割溝は、端部同士が対向するように形成された一対の馬
蹄形状の導電部材の間に形成されている。導電部材に
は、絶縁層に形成されたアンカー部が接続されている。
分割溝に沿ってセラミック基板を分割することにより、
絶縁基体の外周面に形成された凹部に、該凹部の内方に
突出した突出部が形成され、この突出部により端面電極
の端部が被覆され、かつ、アンカー部により絶縁層にア
ンカーされた複数の端面電極を有する分割回路基板が得
られる。BEST MODE FOR CARRYING OUT THE INVENTION A ceramic substrate according to the present invention is formed by forming a pair of horseshoe-shaped conductive members at predetermined intervals such that ends thereof face each other with a division groove formed in an insulating base therebetween. It becomes. The insulating substrate of the ceramic substrate according to the present invention is configured by laminating a plurality of insulating layers made of ceramic or glass ceramic, and internal wiring is formed between these insulating layers. A division groove is formed on the surface of the ceramic substrate, and the division groove is formed between a pair of horseshoe-shaped conductive members whose ends are opposed to each other. An anchor portion formed on the insulating layer is connected to the conductive member.
By dividing the ceramic substrate along the dividing groove,
In the concave portion formed on the outer peripheral surface of the insulating base, a projecting portion projecting inward of the concave portion was formed, the end portion of the end face electrode was covered by the projecting portion, and anchored to the insulating layer by the anchor portion. A divided circuit board having a plurality of end electrodes is obtained.

【００２４】本発明のセラミック基板の製造方法は、絶
縁層成形体に露光，現像し、端面電極となる位置に馬蹄
形状の端面電極用貫通溝を形成するとともに、端面電極
に接続されるアンカー部となる位置にアンカー部用貫通
溝を形成し、これらの溝に導体ペーストを充填し、以上
の工程を繰り返して、分割した際にはそれぞれがアンカ
ー部に接続された端面電極を有する分割回路基板が複数
形成されたセラミック基板を製造する方法である。In the method for manufacturing a ceramic substrate according to the present invention, the insulating layer molded body is exposed and developed to form a horseshoe-shaped through groove for an end surface electrode at a position to be an end surface electrode, and an anchor portion connected to the end surface electrode. Form a through groove for an anchor portion at a position to be filled, fill these grooves with a conductive paste, repeat the above steps, and when divided, each divided circuit board having an end face electrode connected to the anchor portion Is a method of manufacturing a ceramic substrate on which a plurality of ceramic substrates are formed.

【００２５】また、本発明の製造方法では、端部同士を
対向して形成された一対の馬蹄形状の導電部材の内部に
は、絶縁層成形体の積層一体化後に絶縁層成形体と同一
組成の柱状体が存在している。この構造のまま分割溝に
沿って分割すると端面電極が形成できないため、分割前
に導電部材の内部の柱状体を取り除かなくてはならない
が、この取り除く工程はセラミック基板をハイブリッド
ＩＣ単位ブロックとして使用する前（分割前）であれば
どの過程でも良い。例えば、積層一体化後、焼成前に行
っても良いし、焼成後でもかまわない。According to the manufacturing method of the present invention, the pair of horseshoe-shaped conductive members formed with their ends facing each other have the same composition as the insulating layer molded body after lamination and integration of the insulating layer molded body. Pillars are present. If the structure is divided along the dividing groove with this structure, an end face electrode cannot be formed. Therefore, the columnar body inside the conductive member must be removed before the division, but this removing step uses a ceramic substrate as a hybrid IC unit block. Any process may be used before (before division). For example, it may be performed after lamination and integration and before firing, or after firing.

【００２６】また、分割された分割回路基板は最終的に
半田により実装されるため、分割回路基板の端面電極は
半田で接合できるものでなくてはならない。従って、ガ
ラスセラミックを含むセラミックスとの同時焼成を考え
ると、セラミックスは８００〜１０５０℃程度で焼成可
能な材料であり、また、端面電極の構成金属は、銀，パ
ラジウム，白金，銅および銀とパラジウムの合金のうち
の一種を主成分とするものであり、このうちでも銀系合
金もしくは銅が好ましい。銀は半田食われがある為、ニ
ッケル下地でスズめっき等を施したほうが好ましい。ま
た、タングステンやモリブデン等は半田で接続が直接不
可能である為に、この場合にもタングステンやモリブデ
ン等の表面にメッキ等を施したほうが好ましい。Further, since the divided circuit boards are finally mounted by soldering, the end electrodes of the divided circuit boards must be able to be joined by soldering. Therefore, considering simultaneous firing with ceramics including glass ceramics, ceramics are materials that can be fired at about 800 to 1050 ° C., and the constituent metals of the end face electrodes are silver, palladium, platinum, copper, and silver and palladium. Of these alloys as main components, and among them, a silver alloy or copper is preferable. Since silver is eroded by solder, it is preferable to apply tin plating or the like on a nickel base. Further, since tungsten or molybdenum or the like cannot be directly connected by soldering, it is preferable to apply plating or the like to the surface of tungsten or molybdenum in this case as well.

【００２７】本発明の製造方法について詳細に説明す
る。The production method of the present invention will be described in detail.

【００２８】先ず、絶縁層となるスリップ材は、ガラス
セラミックスまたはセラミック材料、光硬化可能なモノ
マー、有機バインダと、有機溶剤を均質混練して得られ
た溶剤系のスリップ材である。First, the slip material serving as the insulating layer is a solvent-based slip material obtained by homogeneously kneading a glass ceramic or ceramic material, a photocurable monomer, an organic binder, and an organic solvent.

【００２９】また８５０〜１０５０℃で焼成されるいわ
ゆる低温焼成セラミックスを複合回路ブロックとして用
いる場合においては、絶縁層には、セラミック材料とガ
ラス材料（両者を合わせて固形成分という）を一般的に
用いる。When so-called low-temperature fired ceramics fired at 850 to 1050 ° C. is used as a composite circuit block, a ceramic material and a glass material (both are called solid components) are generally used for the insulating layer. .

【００３０】セラミック材料としては、クリストバライ
ト、石英、コランダム（αアルミナ）、ムライト、ジル
コニア、コージェライト等の粉末であり、その平均粒径
は、好ましくは１．０〜６．０μｍ、更に好ましくは
１．５〜４．０μｍである。これらのセラミック材料は
２種以上混合して用いてもよい。ここで、１．０〜６．
０μｍのセラミック材料を用いるのは、セラミック材料
の平均粒径が１．０μｍ未満の場合は、スリップ化する
ことが困難であり、後述の露光時に露光光が乱反射して
充分な露光ができなくなり、逆に平均粒径が６．０μｍ
を超えると緻密な絶縁層が得にくくなるからである。Examples of the ceramic material include powders such as cristobalite, quartz, corundum (α-alumina), mullite, zirconia, and cordierite, and the average particle size is preferably 1.0 to 6.0 μm, more preferably 1 to 6.0 μm. 0.5 to 4.0 μm. These ceramic materials may be used in combination of two or more. Here, 1.0-6.
When the ceramic material having a thickness of 0 μm is used, when the average particle size of the ceramic material is less than 1.0 μm, it is difficult to form a slip, and the exposure light is diffusely reflected at the time of exposure described below, and sufficient exposure cannot be performed. Conversely, the average particle size is 6.0 μm
This is because if it exceeds 300, it becomes difficult to obtain a dense insulating layer.

【００３１】ガラス材料は、複数の金属酸化物を含むガ
ラスフリットであり、８５０〜１０５０℃で焼成した後
に、コージェライト、ムライト、アノーサイト、セルジ
アン、スピネル、ガーナイト、ウィレマイト、ドロマイ
ト、ペタライト及びその置換誘導体の結晶を少なくとも
１種析出するものであれば、強度の高い絶縁層が可能と
なる。特に、アノーサイトまたはセルジアンを析出する
結晶化ガラスフリットを用いると、より強度の高い絶縁
層が得られ、また、コージェライトまたはムライトを析
出し得る結晶化ガラスフリットを用いると、焼成後の熱
膨張率が低い為、回路基板上にＩＣ等のシリコンチップ
を配置するための回路基板としては最適となる。The glass material is a glass frit containing a plurality of metal oxides, and after firing at 850 to 1050 ° C., cordierite, mullite, anorthite, Celsian, spinel, garnite, willemite, dolomite, petalite and its replacement. As long as at least one derivative crystal is deposited, an insulating layer with high strength can be obtained. In particular, when a crystallized glass frit that precipitates anorthite or Celsian is used, an insulating layer with higher strength is obtained, and when a crystallized glass frit that can precipitate cordierite or mullite is used, thermal expansion after firing is performed. Since the rate is low, it is optimal as a circuit board for arranging a silicon chip such as an IC on the circuit board.

【００３２】絶縁層の強度、熱膨張率を考慮した最も好
ましいガラス材料としては、Ｂ2 Ｏ3 、ＳｉＯ2 、Ａｌ
2 Ｏ3 、ＺｎＯ、アルカリ土類酸化物を含むガラスフリ
ットである。この様なガラスフリットは、ガラス化範囲
が広く、また屈伏点が６００〜８００℃付近にある為、
８５０〜１０５０℃程度で焼成する場合、低温焼成多層
セラミック回路基板に用いる内部配線、ビアホール導体
となる銅系、銀系及び金系の導電材料の焼結挙動に適し
ている。The most preferred glass materials in consideration of the strength of the insulating layer and the coefficient of thermal expansion are B 2 O 3 , SiO 2 , Al
It is a glass frit containing 2 O 3 , ZnO, and alkaline earth oxide. Since such a glass frit has a wide vitrification range and a yield point around 600 to 800 ° C.,
When firing at about 850 to 1050 ° C., it is suitable for the sintering behavior of copper-based, silver-based, and gold-based conductive materials serving as internal wiring and via-hole conductors used for low-temperature fired multilayer ceramic circuit boards.

【００３３】夫々の成分の作用として、Ｂ2 Ｏ3 、Ｓｉ
Ｏ2 は、主にネットワークフォーマーとして、Ａｌ2 Ｏ
3 は、主にインターミディエイトとして、ＺｎＯ、アル
カリ土類酸化物は、主に更にネットワークモディファイ
ヤーとして作用する。As the action of each component, B 2 O 3 , Si
O 2 is mainly as a network former, Al 2 O
3 mainly acts as an intermediate, and ZnO and alkaline earth oxides mainly act as a network modifier.

【００３４】このようなガラス材料は、上述の所定成分
を所定の比率で混合して加熱溶解し、これを急冷後に粉
砕することによって得られる。粉砕されたガラスフリッ
トの平均粒径は、１．０〜５．０μｍ、好ましくは１．
５〜３．５μｍである。Such a glass material is obtained by mixing the above-mentioned predetermined components at a predetermined ratio, heating and melting, quenching, and then pulverizing. The average particle size of the crushed glass frit is 1.0 to 5.0 μm, preferably 1.
5 to 3.5 μm.

【００３５】ここで、粉砕されたガラスフリットの平均
粒径を１．０〜５．０μｍとしたのは、平均粒径が１．
０μｍ未満の場合はスリップ化することが困難であり、
後述の露光時に露光光が乱反射して充分な露光ができな
くなり、逆に平均粒径が５．０μｍを超えると分散性が
損なわれ、具体的には絶縁材料であるセラミック粉末間
に均等に溶解分散できず、強度が非常に低下してしまう
からである。The reason why the average particle size of the ground glass frit is set to 1.0 to 5.0 μm is that the average particle size is 1.0 to 5.0 μm.
If the thickness is less than 0 μm, it is difficult to form a slip,
Exposure light is irregularly reflected at the time of exposure to be described later, so that sufficient exposure cannot be performed. Conversely, if the average particle size exceeds 5.0 μm, dispersibility is impaired, and specifically, the powder is uniformly dissolved between ceramic powders, which are insulating materials. This is because they cannot be dispersed and the strength is extremely reduced.

【００３６】上述のセラミック材料とガラス材料との構
成比率は、セラミック材料が１０重量％〜５０重量％、
好ましくは２０重量％〜３５重量％であり、ガラス材料
が９０重量％〜５０重量％、好ましくは８０重量％〜６
５重量％である。The composition ratio of the above-mentioned ceramic material and glass material is such that the ceramic material is 10% by weight to 50% by weight,
It is preferably 20% to 35% by weight, and the glass material is 90% to 50% by weight, preferably 80% to 6% by weight.
5% by weight.

【００３７】ここで、セラミック材料が１０重量％〜５
０重量％、ガラス材料が９０重量％〜５０重量％とした
のは、セラミック材料が１０重量％未満、且つガラス材
料が９０重量％を越えると、絶縁層にガラス質が増加し
すぎ、絶縁層の強度等からしても不適切であり、また、
セラミック材料が５０重量％を越え、且つガラス材料が
５０重量％未満となると、後述の露光時に露光光が乱反
射して充分な露光ができなくなり、焼成後の絶縁層の緻
密性も損なわれるからである。Here, the ceramic material is 10% by weight to 5% by weight.
The reason why the weight is 0% by weight and the glass material is 90% by weight to 50% by weight is that if the ceramic material is less than 10% by weight and the glass material exceeds 90% by weight, the glass quality of the insulating layer is excessively increased, and It is inappropriate even from the strength of
If the amount of the ceramic material exceeds 50% by weight and the amount of the glass material is less than 50% by weight, the exposure light is irregularly reflected at the time of exposure to be described later, so that sufficient exposure cannot be performed, and the denseness of the insulating layer after firing is impaired. is there.

【００３８】上述のセラミック材料の他に、スリップ材
の構成材料としては、焼結によって消失される光硬化可
能なモノマー、有機バインダーと、さらに、有機溶剤と
を含んでいる。溶剤系のスリップ材の代わりに水系スリ
ップ材を用いても良い。In addition to the above-described ceramic materials, the constituent materials of the slip material include a photocurable monomer, an organic binder, which is lost by sintering, and an organic solvent. A water-based slip material may be used instead of the solvent-based slip material.

【００３９】溶剤系スリップ材の光硬化可能なモノマー
は、低温短時間の焼成工程に対応するために、熱分解性
に優れたものでなくてはならない。光硬化可能なモノマ
ーとしては、スリップ材の塗布・乾燥後の露光によっ
て、光重合される必要があり、遊離ラジカルの形成、連
鎖生長付加重合が可能で、２級もしくは３級炭素を有し
たモノマーが好ましく、例えば少なくとも１つの重合可
能なエチレン系基を有するブチルアクリレート等のアル
キルアクリレートおよびそれらに対応するアルキルメタ
クリレートが有効である。また、テトラエチレングリコ
ールジアクリレート等のポリエチレングリコールジアク
リレートおよびそれらに対応するメタクリレートも有効
である。光硬化可能なモノマーは、露光で硬化され、現
像で露光以外部分が容易に除去できるような範囲で添加
され、例えば、固形成分に対して５〜１５重量％以下で
ある。The photo-curable monomer of the solvent-based slip material must be excellent in thermal decomposability in order to cope with a low-temperature, short-time baking step. As a photocurable monomer, a monomer having a secondary or tertiary carbon, which needs to be photopolymerized by exposure after application of a slip material and drying, capable of forming free radicals and chain growth addition polymerization. For example, alkyl acrylates such as butyl acrylate having at least one polymerizable ethylenic group and the corresponding alkyl methacrylates are effective. Further, polyethylene glycol diacrylates such as tetraethylene glycol diacrylate and methacrylates corresponding thereto are also effective. The photo-curable monomer is added in such a range that it can be cured by exposure and a portion other than the exposure can be easily removed by development, and is, for example, 5 to 15% by weight or less based on the solid component.

【００４０】溶剤系スリップ材の有機バインダは、光硬
化可能なモノマーと同様に熱分解性の良好なものでなく
てはならない。具体的には６００℃以下で熱分解が可能
でなくてはならない。更に好ましくは５００℃以下であ
る。熱分解温度が６００℃を越えると、絶縁層内に残存
してしまい、カーボンとしてトラップし、基体を灰色に
変色させたり、絶縁層の絶縁抵抗及びＱ値までも低下さ
せてしまう。またボイドとなりデラミネーションを起こ
すことがある。The organic binder of the solvent-based slip material must have good thermal decomposability like the photocurable monomer. Specifically, thermal decomposition must be possible at 600 ° C. or lower. More preferably, the temperature is 500 ° C. or lower. If the thermal decomposition temperature exceeds 600 ° C., it remains in the insulating layer and is trapped as carbon, discoloring the substrate to gray, and lowering the insulation resistance and Q value of the insulating layer. In addition, it may become a void and cause delamination.

【００４１】また、スリップ材として、増感剤、光開始
系材料等を必要に応じて添加しても構わない。例えば、
光開始系材料としては、ベンゾフェノン類、アシロイン
エステル類化合物などが挙げられる。As a slip material, a sensitizer, a photo-initiating material or the like may be added as required. For example,
Examples of the photoinitiating material include benzophenones and acyloin ester compounds.

【００４２】上述のように、ガラスセラミックスまたは
セラミック材料、光硬化可能なモノマー、有機バインダ
さらに、有機溶剤とともに混合、混練して、絶縁層とな
る溶剤系スリップ材が構成される。混合・混練方法は従
来より用いられている方法、例えばボールミルによる方
法を用いればよい。スリップ材の薄層化方法は、例え
ば、ドクターブレード法（ナイフコート法）、ロールコ
ート法、印刷法などにより形成され、特に塗布後の絶縁
層成形体の表面が平坦化することが容易なドクターブレ
ード法などが好適である。尚、スリップ材は薄層化の方
法に応じて所定粘度に調整される。As described above, a glass-ceramic or ceramic material, a photocurable monomer, an organic binder, and an organic solvent are mixed and kneaded to form a solvent-based slip material serving as an insulating layer. The method of mixing and kneading may be a conventionally used method, for example, a method using a ball mill. The method of thinning the slip material is, for example, a doctor blade method (knife coat method), a roll coat method, a printing method, and the like. A blade method or the like is suitable. The slip material is adjusted to a predetermined viscosity according to the method of thinning.

【００４３】また、端面電極となる導体材料の導電性ペ
ーストは、銀系合金または銅のうち少なくとも１つの金
属材料の粉末と、低融点ガラス成分と、有機バインダー
及び有機溶剤とを均質混練したものが好適に使用され
る。内部配線及びビアホール導体となる導体材料の導電
性ペーストは端面電極のものと同様でもかまわないし、
銀を主成分としたものでもかまわない。これらは、特に
焼成温度が８５０〜１０５０℃であるため、金属材料と
しては、比較的低融点であり、且つ低抵抗材料が選択さ
れ、また、低融点ガラス成分も、絶縁層となる絶縁層成
形体（スリップ材を塗布、乾燥したもの）との焼結挙動
を考慮して、その屈伏点が７００℃前後となるものが使
用される。アンカー部は、端面電極に接続できるもので
あればどのような材料から構成しても良く、端面電極材
料と異なるものでも良いが、端面電極との接続性および
製造容易性の観点から同一材料からなることが望まし
い。この場合には、アンカー部に内部配線を接続するこ
ともできる。The conductive paste of the conductive material used as the end face electrode is obtained by homogeneously kneading a powder of at least one metal material of a silver alloy or copper, a low melting point glass component, an organic binder and an organic solvent. Is preferably used. The conductive paste of the conductor material to be the internal wiring and via-hole conductor may be the same as that of the end face electrode,
A material containing silver as a main component may be used. Since these materials have a firing temperature of 850 to 1050 ° C. in particular, a metal material having a relatively low melting point and a low resistance material is selected. Taking into account the sintering behavior with a body (one coated with a slip material and dried), one having a deformation point of about 700 ° C. is used. The anchor portion may be made of any material as long as it can be connected to the end face electrode, and may be different from the end face electrode material, but from the same material in terms of connectability with the end face electrode and ease of manufacturing. It is desirable to become. In this case, an internal wiring can be connected to the anchor portion.

【００４４】本発明のセラミック回路基板の製造方法
は、まず、支持基板上にスリップ材料を薄層化（以下、
単に塗布という）・乾燥して絶縁層となる絶縁層成形体
を形成する。In the method of manufacturing a ceramic circuit board according to the present invention, first, a slip material is thinned on a support substrate (hereinafter, referred to as a “slip material”).
(The coating is simply referred to as coating.) Drying to form an insulating layer molded body that becomes an insulating layer.

【００４５】支持基板としては、ガラス基板，有機フィ
ルム，アルミナセラミックなどが例示できる。この支持
基板は、焼成工程前で取り外される。Examples of the supporting substrate include a glass substrate, an organic film, and an alumina ceramic. This support substrate is removed before the firing step.

【００４６】塗布方法としては、ドクターブレード法や
ロールコート法、塗布面積を概略支持基板と同一面積と
するスクリーンを用いた印刷法などによって形成され
る。As a coating method, it is formed by a doctor blade method, a roll coating method, a printing method using a screen having a coating area approximately the same as that of the supporting substrate, or the like.

【００４７】次に、支持基板上に形成した絶縁層成形体
に端面電極となる馬蹄形状の端面電極用貫通溝及び端面
電極用貫通溝に連通するアンカー部用貫通溝、さらに必
要に応じビアホール導体となる貫通穴を形成する。尚、
実際には、貫通溝及び貫通穴の下部は支持基板などによ
って閉塞されているが、便宜上貫通溝及び貫通穴とい
う。Next, a horseshoe-shaped through groove for an end surface electrode serving as an end surface electrode, a through groove for an anchor portion communicating with the through groove for the end surface electrode, and a via-hole conductor, if necessary, are formed on the insulating layer formed body formed on the support substrate. Is formed. still,
Actually, the lower portions of the through-groove and the through-hole are closed by a support substrate or the like, but are referred to as the through-groove and the through-hole for convenience.

【００４８】貫通溝及び貫通穴の形成方法は、露光・現
像を用いて行う。尚、ビアホール導体の形成の不要な絶
縁層成形体については、この貫通穴の形成、そして次に
続く導電性ペーストの充填を省略する。The method for forming the through-grooves and through-holes is performed using exposure and development. The formation of the through hole and the subsequent filling of the conductive paste are omitted for the insulating layer molded body that does not require the formation of the via hole conductor.

【００４９】露光処理は、例えば、フォトターゲットを
絶縁層成形体上に近接または載置して、貫通溝および貫
通穴以外の領域に、低圧、高圧、超高圧の水銀灯系の露
光光を照射する。これにより、貫通溝及び貫通穴以外の
領域では、光硬化可能なモノマーが光重合反応を起こ
す。従って、貫通溝及び貫通穴部分のみが現像処理によ
って除去可能な溶化部となる。この際の端面電極用貫通
溝の形状は、端部同士が対向するように一対の馬蹄形状
の端面電極用貫通溝を所定間隔をおいて形成される。ア
ンカー部の形状は、端面電極がアンカーされる形状であ
ればどのような形状でも良いが、特に、アンカー効果の
点からＴ字状であることが望ましい。In the exposure treatment, for example, a photo target is placed close to or placed on the insulating layer molded body, and the regions other than the through-grooves and through-holes are irradiated with low-, high-, and ultra-high-pressure mercury lamp exposure light. . As a result, the photocurable monomer causes a photopolymerization reaction in a region other than the through groove and the through hole. Therefore, only the through-groove and the through-hole portion become the fusible portion that can be removed by the developing process. At this time, the shape of the end surface electrode through-groove is such that a pair of horseshoe-shaped end surface electrode through-grooves are formed at predetermined intervals so that the ends are opposed to each other. The shape of the anchor portion may be any shape as long as the end surface electrode is anchored, but it is particularly desirable to be T-shaped from the viewpoint of the anchor effect.

【００５０】現像処理は、クロロセン等の溶剤を例えば
スプレー現像法やパドル現像法によって、貫通溝や貫通
穴である露光溶化部に接触させ、現像を行う。一対の馬
蹄形状の端面電極用貫通溝の端部同士の間には、絶縁層
成形体の一部が残存している。その後、必要に応じて洗
浄及び乾燥を行なう。In the developing treatment, a solvent such as chlorocene is brought into contact with the exposed and solubilized portion which is a through groove or a through hole by, for example, a spray developing method or a paddle developing method to perform development. A part of the insulating layer molded body remains between the ends of the pair of horseshoe-shaped end face electrode through grooves. Thereafter, washing and drying are performed as necessary.

【００５１】次に、端面電極、アンカー部及びビアホー
ル導体となる導電部材を、絶縁層成形体の貫通溝や貫通
穴に導電性ペーストを充填し、乾燥することによって形
成する。充填方法は、例えばスクリーン印刷方法で行な
う。Next, a conductive member to be an end face electrode, an anchor portion and a via hole conductor is formed by filling a conductive paste in a through-groove or a through-hole of the molded insulating layer and drying it. The filling method is performed by, for example, a screen printing method.

【００５２】次に、内部配線となるパターンを導電性ペ
ーストを用いて印刷・乾燥する。印刷方法は、例えばス
クリーン印刷方法で行なう。尚、内部配線が不要な場合
は、この工程は省略される。また、この内部配線パター
ンの形成は、貫通溝形成後に形成しても良い。Next, a pattern to be an internal wiring is printed and dried using a conductive paste. The printing method is, for example, a screen printing method. If no internal wiring is required, this step is omitted. The internal wiring pattern may be formed after the formation of the through groove.

【００５３】以上、スリップ材の塗布・乾燥による絶縁
層成形体の形成、露光・現像による貫通溝及び貫通穴の
形成、導電性ペーストの印刷形成による導電部材及び内
部配線となるパターンの形成で、基本的に１層分の絶縁
層成形体及び内部配線パターンの形成が終了し、これを
所望の回数繰り返すことにより未焼成状態の積層成形体
が完成する。その後、必要に応じてプレス等を行ない形
状を整える。As described above, the formation of the insulating layer molded body by applying and drying the slip material, the formation of the through-grooves and the through-holes by exposure and development, the formation of the conductive member and the pattern to be the internal wiring by the printing of the conductive paste, Basically, the formation of the insulating layer molded body and the internal wiring pattern for one layer is completed, and this is repeated a desired number of times to complete the unfired laminated molded body. Thereafter, the shape is adjusted by performing pressing or the like as necessary.

【００５４】この後、積層成形体に、端部が対向するよ
うに形成された一対の馬蹄形状の端面電極用貫通溝の間
を分割溝が通過するように、分割回路基板毎に分割する
ための分割溝を形成する。この分割溝の形成工程は、一
対の馬蹄形状の端面電極用貫通溝の内側に形成された馬
蹄形状の導電部材内部の柱状体を取り除く前に行うこと
が望ましい。Thereafter, the divided molded body is divided into divided circuit boards so that the divided grooves pass between a pair of horseshoe-shaped end surface electrode through grooves formed so that the ends are opposed to each other. Is formed. The step of forming the dividing groove is desirably performed before removing the columnar body inside the horseshoe-shaped conductive member formed inside the pair of horseshoe-shaped end face electrode through grooves.

【００５５】次に、端面電極用貫通溝に充填された一対
の馬蹄形状の導電部材内部の柱状体を取り除く。本工程
は先述のごとく未焼成状態のセラミック回路基板状態で
実施することは本発明においては限定されるものではな
いが、加工の容易性から積層成形体を形成した後除去す
ることが好ましい。方法としては金型による打ち抜き方
法等が好ましいが、ドリルによる工法等でも実用可能で
ある。Next, the pillars inside the pair of horseshoe-shaped conductive members filled in the through-holes for the end face electrodes are removed. It is not limited in the present invention that the present step is performed in the unfired state of the ceramic circuit board as described above, but it is preferable to remove the laminated molded body after forming it from the viewpoint of easiness of processing. As a method, a punching method using a die or the like is preferable, but a method using a drill or the like is also practical.

【００５６】最後に焼成を行なう。焼成工程は脱バイン
ダ過程と焼成過程からなり、脱バインダ過程（〜６００
℃）で絶縁層成形体、内部配線パターン，端面電極、ア
ンカー部及びビアホール導体の導電部材の有機成分を消
失する。その後、所定雰囲気、所定温度で絶縁層となる
絶縁層成形体および内部配線パターン，端面電極，アン
カー部，ビアホール導体となる導電部材を一括的に焼成
する。Finally, firing is performed. The firing step includes a binder removal step and a firing step.
C), the organic components of the insulating layer molded body, the internal wiring pattern, the end face electrode, the anchor portion, and the conductive member of the via-hole conductor disappear. Thereafter, the insulating layer molded body serving as the insulating layer and the internal wiring pattern, the end surface electrode, the anchor portion, and the conductive member serving as the via hole conductor are fired at a predetermined atmosphere and at a predetermined temperature.

【００５７】[0057]

【実施例】図１は、本発明の製造方法により作製された
セラミック基板を分割溝に沿って分割し、得られた分割
回路基板の斜視図である。図１において、符号１は分割
回路基板を示しており、入出力端子、電源端子、グラン
ド端子等の端子が端面電極２として示されている。図１
においては、端面電極２は分割回路基板１の側面４面に
計１０箇所形成されている。これらの端面電極２には分
割回路基板１に形成されたアンカー部１７が接続されて
いる。また、分割回路基板１の表面には、表面電極（配
線）３が形成され、この表面電極３には抵抗器やコンデ
ンサ等のチップ部品４が接続されている。また、分割回
路基板１にはキャビティ部５が形成されており、このキ
ャビティ部５には半導体ベアチップ６が収容され、ワイ
ヤにより表層電極３と接続されている。FIG. 1 is a perspective view of a divided circuit board obtained by dividing a ceramic substrate manufactured by the manufacturing method of the present invention along a dividing groove. In FIG. 1, reference numeral 1 denotes a divided circuit board, and terminals such as input / output terminals, power supply terminals, and ground terminals are shown as end face electrodes 2. FIG.
In the example, the end face electrodes 2 are formed at a total of ten places on the four side surfaces of the divided circuit board 1. Anchors 17 formed on the divided circuit board 1 are connected to these end electrodes 2. A surface electrode (wiring) 3 is formed on the surface of the divided circuit board 1, and a chip component 4 such as a resistor or a capacitor is connected to the surface electrode 3. A cavity 5 is formed in the divided circuit board 1, and a semiconductor bare chip 6 is accommodated in the cavity 5, and is connected to the surface electrode 3 by a wire.

【００５８】このような分割回路基板１は、この分割回
路基板１が集合した、図２に示すようなセラミック基板
を分割溝７に沿って分割することにより得られる。Such a divided circuit board 1 is obtained by dividing a ceramic substrate as shown in FIG.

【００５９】この実施例では、セラミック基板を、内部
配線導体として金系、銀系、銅系導体を使用した低温焼
成のセラミックにより形成した場合について説明する。In this embodiment, a case will be described in which the ceramic substrate is formed of a low-temperature fired ceramic using a gold-based, silver-based, or copper-based conductor as the internal wiring conductor.

【００６０】本発明のセラミック基板は、図３に示すよ
うに、絶縁層１０ａ〜１０ｇ、内部配線１１、ビアホー
ル導体１２、端面電極２となる導電部材２１、導電部材
２１に接続されるアンカー部１７とからなり、絶縁層１
０ａ〜１０ｇにより絶縁基体１３が形成され、表面には
表面電極３が形成されている。尚、図２においては、表
面電極３およびアンカー部１７の記載は省略している。As shown in FIG. 3, the ceramic substrate of the present invention comprises insulating layers 10a to 10g, internal wiring 11, via hole conductor 12, conductive member 21 to be end face electrode 2, and anchor 17 connected to conductive member 21. And the insulating layer 1
The insulating base 13 is formed from 0a to 10g, and the surface electrode 3 is formed on the surface. 2, illustration of the surface electrode 3 and the anchor portion 17 is omitted.

【００６１】絶縁層１０ａ〜１０ｇはガラスセラミック
材料からなり、それぞれの厚みは４０〜１５０μｍであ
る。このような絶縁層１０ａと絶縁層１０ｂ、絶縁層１
０ｃと絶縁層１０ｄ、絶縁層１０ｅと絶縁層１０ｆ、絶
縁層１０ｆと絶縁層１０ｇ間には、内部配線１１が配置
されている。内部配線１１は、金系、銀系、銅系の金属
材料、例えば銀系導体からなっている。また、内部配線
１１は、絶縁層１０ｇの厚みを貫くビアホール導体１２
によって接続されているものもあれば、容量結合等で分
布定数的に接続されるものもある。このビアホール導体
１２も内部配線１１と同様に金系、銀系、銅系の金属材
料、例えば銀系導体からなっている。The insulating layers 10a to 10g are made of a glass ceramic material, and each has a thickness of 40 to 150 μm. Such an insulating layer 10a, an insulating layer 10b, an insulating layer 1
The internal wiring 11 is disposed between the insulating layer 10c and the insulating layer 10d, between the insulating layer 10e and the insulating layer 10f, and between the insulating layer 10f and the insulating layer 10g. The internal wiring 11 is made of a gold-based, silver-based, or copper-based metal material, for example, a silver-based conductor. Further, the internal wiring 11 includes a via-hole conductor 12 penetrating through the thickness of the insulating layer 10g.
Some are connected in a distributed manner by capacitive coupling or the like. The via-hole conductor 12 is also made of a gold-based, silver-based, or copper-based metal material, for example, a silver-based conductor, like the internal wiring 11.

【００６２】絶縁基体１３の表面には、絶縁層１０ｇの
ビアホール導体１２と接続する表面電極３が形成されて
おり、この表面電極３上には、必要に応じて厚膜抵抗体
膜や厚膜保護膜が形成されたり、メッキ処理されたり、
また、図１に示したように、ＩＣを含む各種電子部品が
半田やボンディング細線によって接合される。A surface electrode 3 connected to the via-hole conductor 12 of the insulating layer 10g is formed on the surface of the insulating substrate 13, and a thick resistor film or a thick film is formed on the surface electrode 3 as necessary. If a protective film is formed, plated,
Further, as shown in FIG. 1, various electronic components including an IC are joined by solder or a thin bonding wire.

【００６３】本発明の分割回路基板は、図４及び図５に
示される中間構造を経て製造される。まず、絶縁層１０
ａ〜１０ｇとなるスリップ材を作成する。The divided circuit board of the present invention is manufactured through the intermediate structure shown in FIGS. First, the insulating layer 10
A slip material of a to 10 g is prepared.

【００６４】溶剤系スリップ材は、例えば、ガラス材料
であるＳｉＯ2 、Ａｌ2 Ｏ3 、ＺｎＯ、ＭｇＯ、Ｂ2 Ｏ
3 を主成分とする結晶化ガラス粉末５０重量％とセラミ
ック材料であるアルミナ粉末５０重量％とからなるガラ
ス−セラミック粉末と、光硬化可能なモノマー、例えば
ポリオキシエチル化トリメチロールプロパントリアクリ
レートと、有機バインダ、例えばアルキルメタクリレー
トと、可塑剤とを、有機溶剤、例えばエチルカルビトー
ルアセテートに混合し、ボールミルで約４８時間混練し
て作成される。Solvent-based slip materials include, for example, glass materials such as SiO 2 , Al 2 O 3 , ZnO, MgO, and B 2 O.
A glass-ceramic powder comprising 50% by weight of a crystallized glass powder containing 3 as a main component and 50% by weight of an alumina powder as a ceramic material, a photocurable monomer such as polyoxyethylated trimethylolpropane triacrylate, It is prepared by mixing an organic binder such as alkyl methacrylate and a plasticizer with an organic solvent such as ethyl carbitol acetate, and kneading the mixture in a ball mill for about 48 hours.

【００６５】尚、この実施例では溶剤系スリップ材を作
成しているが、上述のように親水性の官能基を付加した
光硬化可能なモノマー、例えば多官能基メタクリレート
モノマー、有機バインダ、例えばカルボキシル変性アル
キルメタクリレートを用いて、イオン交換水で混練した
水系スリップ材を作成しても構わない。In this embodiment, a solvent-based slip material is prepared. However, as described above, a photocurable monomer having a hydrophilic functional group added thereto, for example, a polyfunctional methacrylate monomer, an organic binder such as carboxylic acid Using a modified alkyl methacrylate, an aqueous slip material kneaded with ion-exchanged water may be prepared.

【００６６】また、内部配線１１、ビアホール導体１
２、端面電極２、アンカー部１７となる導電性ペースト
を作成する。導電性ペーストは、低融点で且つ低抵抗の
金属材料である例えば銀粉末と、硼珪酸系低融点ガラ
ス、例えばＢ2 Ｏ3 −ＳｉＯ2 −ＢａＯガラス、ＣａＯ
−Ｂ2 Ｏ3 −ＳｉＯ2 ガラス、ＣａＯ−Ａｌ2 Ｏ3 −Ｂ
2Ｏ3 −ＳｉＯ2 ガラスと、有機バインダ、例えばエチ
ルセルロースとを、有機溶剤、例えば２，２，４−トリ
メチル−１，３−ペンタジオ−ルモノイソブチレ−トに
混合し、ボールミルで均質に混練して作成する。The internal wiring 11 and the via-hole conductor 1
2. A conductive paste for forming the end face electrode 2 and the anchor portion 17 is prepared. The conductive paste is a low melting point and low resistance metal material such as silver powder, and a borosilicate low melting point glass such as B 2 O 3 —SiO 2 —BaO glass or CaO.
-B 2 O 3 -SiO 2 glass, CaO-Al 2 O 3 -B
2 O 3 —SiO 2 glass and an organic binder, for example, ethyl cellulose, are mixed with an organic solvent, for example, 2,2,4-trimethyl-1,3-pentadiol monoisobutyrate, and kneaded homogeneously with a ball mill. I do.

【００６７】そして、先ず、図４（ａ）に示すように、
上述のスリップ材を用意された支持基板１４上に塗布し
て乾燥を行い、最下層となる絶縁層成形体２０ａを形成
する。具体的には、まず、支持基板１４上に、上述のス
リップ材をドクターブレード法によって塗布した後乾燥
して、焼成後の絶縁層１０ａ〜１０ｇの最下層である絶
縁層１０ａとなる絶縁層成形体２０ａを形成する。ここ
で、支持基板１４としては、マイラーフイルムを用い、
焼成工程前に取り外される。塗布後の乾燥条件は、６０
〜８０℃で２０分乾燥であり、薄層化・乾燥された絶縁
層成形体２０ａの厚みは１２０μｍである。Then, first, as shown in FIG.
The slip material described above is applied to the prepared support substrate 14 and dried to form the lowermost insulating layer molded body 20a. Specifically, first, the above-mentioned slip material is applied on the support substrate 14 by a doctor blade method, and then dried, and then the insulating layer 10a to be the lowermost layer of the fired insulating layers 10a to 10g is formed. The body 20a is formed. Here, a mylar film is used as the support substrate 14,
Removed before firing process. Drying conditions after application are 60
Drying is performed at -80 ° C for 20 minutes, and the thickness of the thinned and dried insulating layer molded body 20a is 120 µm.

【００６８】この絶縁層成形体２０ａには端面電極２に
相当する導電部材２１およびこの導電部材２１に接続す
るアンカー部１７が形成されるため、図４（ｂ）に示す
ように、端面電極用貫通溝２３およびアンカー部用貫通
溝３７の形成を行う。一対の端面電極用貫通溝２３は、
平面方向からみると、図６に示すように、それらの端部
２４同士が所定間隔をおいて対向して形成されている。
また、アンカー部用貫通溝３７はＴ字状をしており、端
面電極用貫通溝２３に連通している。端面電極用貫通溝
２３およびアンカー部用貫通溝３７の形成は、露光処
理、現像処理、洗浄・乾燥処理を行うことにより形成す
る。Since the conductive member 21 corresponding to the end face electrode 2 and the anchor portion 17 connected to the conductive member 21 are formed on the insulating layer molded body 20a, as shown in FIG. The through groove 23 and the anchor part through groove 37 are formed. The pair of end surface electrode through grooves 23 are
When viewed from the plane, as shown in FIG. 6, the ends 24 are formed facing each other at a predetermined interval.
The anchor portion through groove 37 has a T-shape, and communicates with the end surface electrode through groove 23. The through-hole 23 for the end face electrode and the through-groove 37 for the anchor portion are formed by performing an exposure process, a development process, and a cleaning / drying process.

【００６９】露光処理は、例えば、フォトターゲットを
絶縁層成形体２０ａ上に近接または載置して、端面電極
用貫通溝２３およびアンカー部用貫通溝３７以外の領域
に、低圧、高圧、超高圧の水銀灯系の露光光を照射す
る。これにより、端面電極用貫通溝２３およびアンカー
部用貫通溝３７以外の領域では、光硬化可能なモノマー
が光重合反応を起こす。従って、端面電極用貫通溝２３
およびアンカー部用貫通溝３７部分のみが現像処理によ
って除去可能な溶化部となる。In the exposure processing, for example, a photo target is placed close to or placed on the insulating layer molded body 20a, and a low pressure, a high pressure and an ultra high pressure are applied to the area other than the end face electrode through groove 23 and the anchor part through groove 37. Irradiation exposure light of a mercury lamp system. As a result, the photocurable monomer causes a photopolymerization reaction in a region other than the end surface electrode through groove 23 and the anchor portion through groove 37. Therefore, the through groove 23 for the end face electrode
Also, only the portion of the through groove 37 for the anchor portion is a solubilized portion that can be removed by the developing process.

【００７０】具体的には、露光処理は、絶縁層成形体２
０ａ上に端面電極用貫通溝２３およびアンカー部用貫通
溝３７が形成される領域が遮光されるようなフォトター
ゲットを載置して、超高圧水銀灯（１０ｍＷ／ｃｍ2 ）
を光源として用いて露光を行なう。Specifically, the exposure treatment is performed on the insulating layer molded body 2
A photo target is placed on Oa so that the area where the end surface electrode through groove 23 and the anchor part through groove 37 are formed is shielded from light, and an ultra-high pressure mercury lamp (10 mW / cm 2 ) is used.
Exposure is performed using as a light source.

【００７１】これにより、端面電極用貫通溝２３および
アンカー部用貫通溝３７が形成される領域の絶縁層成形
体２０ａにおいては光硬化可能なモノマの光重合反応が
おこらず、端面電極用貫通溝２３およびアンカー部用貫
通溝３７が形成される領域以外の絶縁層成形体２０ａに
おいては、光重合反応が起こる。ここで光重合反応が起
こった部位を不溶化部といい、光重合反応が起こらない
部位を溶化部という。As a result, the photopolymerization reaction of the photocurable monomer does not occur in the insulating layer molded body 20a in the region where the through groove 23 for the end face electrode and the through groove 37 for the anchor portion are formed. A photopolymerization reaction occurs in the insulating layer molded body 20a other than the region where the through holes 23 and the anchor portion through grooves 37 are formed. Here, the part where the photopolymerization reaction has occurred is called an insolubilized part, and the part where the photopolymerization reaction does not occur is called a solubilized part.

【００７２】尚、１２０μｍ程度の絶縁層成形体は、超
高圧水銀灯（１０ｍＷ／ｃｍ2 ）を２０〜３０秒程度照
射すれば露光を行うことができる。The molded product of the insulating layer having a thickness of about 120 μm can be exposed by irradiating an ultra-high pressure mercury lamp (10 mW / cm 2 ) for about 20 to 30 seconds.

【００７３】現像処理は、クロロセン等の溶剤を例えば
スプレー現像法やパドル現像法によって、絶縁層成形体
２０ａである露光溶化部に接触させ、現像を行う。その
後、必要に応じて洗浄及び乾燥を行なう。現像処理は、
絶縁層成形体２０ａの溶化部を現像液で除去するもの
で、具体的には１，１，１−トリクロロエタンをスプレ
ー法で現像を行う。In the development treatment, a solvent such as chlorocene is brought into contact with the exposed and solubilized portion, which is the molded article of the insulating layer 20a, by, for example, a spray development method or a paddle development method to perform development. Thereafter, washing and drying are performed as necessary. The development process is
This is for removing the solubilized portion of the insulating layer molded body 20a with a developer, and specifically, 1,1,1-trichloroethane is developed by a spray method.

【００７４】この現像処理により、絶縁層成形体２０ａ
に１００〜２００μｍ幅でＵ字状の端面電極用貫通溝２
３を形成することができ、またＴ字状のアンカー部用貫
通溝３７を形成することができる。その後、絶縁層成形
体２０ａを現像によって生じる不要なカスなどを洗浄、
乾燥工程により完全に除去する。尚、端面電極用貫通溝
２３は、平面的に見て一部が開口したもの（馬蹄形状）
であれば良く、半円状、Ｕ字状、および楕円形，四角
形，その他の閉ループ状のものの一部が開口した形状で
あっても良いことは勿論である。また、アンカー部用貫
通溝３７は端面電極をアンカーできるものであればどの
ような形状でも良い。By this developing treatment, the insulating layer molded body 20a
U-shaped end face electrode through groove 2 having a width of 100 to 200 μm
3, and a T-shaped anchor portion through groove 37 can be formed. Thereafter, unnecessary debris or the like generated by developing the insulating layer molded body 20a is washed,
It is completely removed by a drying step. The through-hole 23 for the end face electrode is partially open when viewed in plan (a horseshoe shape).
Any shape may be used as long as the shape is a semicircle, a U-shape, an ellipse, a square, or a part of a closed loop. Further, the through groove 37 for the anchor portion may have any shape as long as it can anchor the end face electrode.

【００７５】次に、端面電極用貫通溝２３およびアンカ
ー部用貫通溝３７に導体ペーストを充填し、乾燥して、
図４（ｃ）に示すように、端面電極２を形成するための
導電部材２１およびアンカー部１７を形成するための導
電部材２２を形成する。具体的には、上述の工程で形成
した端面電極用貫通溝２３およびアンカー部用貫通溝３
７に上述の導電性ペーストを充填し、乾燥する。端面電
極用貫通溝２３およびアンカー部用貫通溝３７に相当す
る部位のみに印刷可能なスクリーンを用いる印刷によっ
て、端面電極２となる導電部材２１およびアンカー部１
７となる導電部材２２を形成し、その後、５０℃・１０
分乾燥する。Next, a conductive paste is filled in the end surface electrode through-groove 23 and the anchor-portion through-groove 37, and dried,
As shown in FIG. 4C, a conductive member 21 for forming the end face electrode 2 and a conductive member 22 for forming the anchor portion 17 are formed. Specifically, the end surface electrode through-groove 23 and the anchor portion through-groove 3 formed in the above-described steps are formed.
7 is filled with the above-mentioned conductive paste and dried. The conductive member 21 and the anchor portion 1 serving as the end surface electrode 2 are printed by printing using a screen that can be printed only at portions corresponding to the end surface electrode through groove 23 and the anchor portion through groove 37.
7 is formed, and thereafter, at 50 ° C.
Allow to dry.

【００７６】次に、焼成後に内部配線１１となるパター
ンを印刷・乾燥を行う。具体的には、図４（ｃ）に示す
ように、絶縁層１０ａと絶縁層１０ｂとの間に配置され
る内部配線１１となる内部配線パターン２６をスクリー
ン印刷法にて形成し、乾燥を行う。内部配線パターン２
６はアンカー部１７の導電部材２２と電気的に接続され
る。Next, a pattern to be the internal wiring 11 after firing is printed and dried. More specifically, as shown in FIG. 4C, an internal wiring pattern 26 serving as the internal wiring 11 disposed between the insulating layer 10a and the insulating layer 10b is formed by a screen printing method and dried. . Internal wiring pattern 2
6 is electrically connected to the conductive member 22 of the anchor portion 17.

【００７７】そして、前述した絶縁層成形体２０ａの形
成から、内部配線パターン２６の形成までの工程を繰り
返す。このようにして、図５に示すように、最上層の絶
縁層成形体２０ｇを形成し、露光・現像処理により端面
電極用貫通溝２３、アンカー部用貫通溝３７およびビア
ホールを形成するための貫通穴を形成し、端面電極２、
アンカー部１７やビアホール導体１２となる導電性ペー
ストを印刷充填して、７層の積層成形体２７を形成す
る。尚、内部配線パターン２６が不要な場合には、前述
した内部配線パターン２６の作製工程が省略される。Then, the steps from the formation of the insulating layer molded body 20a to the formation of the internal wiring pattern 26 are repeated. In this way, as shown in FIG. 5, the uppermost insulating layer molded body 20g is formed, and the through-hole for forming the through-hole 23 for the end face electrode, the through-hole 37 for the anchor part, and the via hole is formed by exposure and development. A hole is formed and the end face electrode 2,
A conductive paste that becomes the anchor portion 17 and the via-hole conductor 12 is printed and filled to form a seven-layer laminated body 27. If the internal wiring pattern 26 is unnecessary, the above-described step of manufacturing the internal wiring pattern 26 is omitted.

【００７８】続いて、表面電極３となる導体膜を印刷・
乾燥により形成する。これは、各絶縁層成形体２０ａ〜
２０ｇ、内部配線１１となる配線パターン２６、ビアホ
ール導体１２、アンカー部１７および端面電極２となる
導電部材２１、２２との一括焼成時に、表面電極３とな
る導体膜も一括的に焼成しようとするものである。Subsequently, a conductor film to be the surface electrode 3 is printed and
It is formed by drying. This is because each of the insulating layer molded bodies 20a-
20 g, the wiring pattern 26 to be the internal wiring 11, the via-hole conductor 12, the anchor portion 17, and the conductive members 21 and 22 to be the end surface electrodes 2 are simultaneously baked together with the conductive film to be the surface electrode 3. Things.

【００７９】次に、必要に応じて、積層成形体２７の形
状をプレスで整え、分割溝７を形成し、支持基板１４を
取り外す。分割溝７は、図２および図６に示すように対
向して形成された一対の端面電極用貫通溝２３の内側の
柱状体２９を通過するように形成されている。このよう
な分割溝７の形成は、ダイシングソーを用いて形成され
ている。Next, if necessary, the shape of the laminated molded body 27 is adjusted by pressing, the dividing groove 7 is formed, and the support substrate 14 is removed. The dividing groove 7 is formed so as to pass through the columnar body 29 inside the pair of end surface electrode through grooves 23 formed facing each other as shown in FIGS. 2 and 6. Such division grooves 7 are formed by using a dicing saw.

【００８０】次に端面電極２となる一対の馬蹄形状の導
電部材２１で囲まれた円柱状の柱状体２９を取り除く。
除去は金型による打ち抜きで実施する。この際、金型の
クリアランスを配慮した上で、柱状体２９とともに、一
対の導電部材２１の内面が僅かな厚み取り除かれる。本
工程は先述のごとく未焼成状態で実施することは本発明
においては限定されるものではないが、加工の容易性か
ら積層成形体２７を形成した後除去することが好まし
い。方法としては上述したように金型による打ち抜き方
法等が好ましいが、ドリルによる工法等でも実用可能で
ある。Next, the columnar body 29 surrounded by the pair of horseshoe-shaped conductive members 21 serving as the end surface electrodes 2 is removed.
Removal is performed by punching with a die. At this time, the inner surfaces of the pair of conductive members 21 are removed with a slight thickness together with the columnar bodies 29 while taking into account the clearance of the mold. It is not limited in the present invention that this step is performed in the unfired state as described above, but it is preferable to remove after forming the laminated molded body 27 from the viewpoint of easiness of processing. As a method, a punching method using a die or the like is preferable as described above, but a method using a drill or the like is also practical.

【００８１】次に焼成を行う。焼成は、脱バインダー工
程と本焼成工程からなる。脱バインダー工程は、概ね６
００℃以下の温度領域であり、絶縁層成形体２０ａ〜２
０ｇ及び内部配線パターン２６、導電部材２１、２２に
含まれている有機バインダ、光硬化可能なモノマを消失
する過程であり、本焼成工程は、ピーク温度８５０〜１
０５０℃、例えば、９００℃３０分ピークの焼成過程で
あり、絶縁層となる絶縁層成形体１０ａ〜１０ｇおよび
内部配線パターン２６，端面電極２，アンカー部１７，
ビアホール導体１２となる導電部材２１、２２を一括的
に焼成する。Next, firing is performed. The firing includes a binder removal step and a main firing step. The debinding process is generally 6
The temperature range is not higher than 00 ° C.
0 g, the internal wiring pattern 26, the organic binder contained in the conductive members 21 and 22, and the photo-curable monomer are eliminated.
This is a baking process at a peak of 050 ° C., for example, 900 ° C. for 30 minutes.
The conductive members 21 and 22 to be the via-hole conductors 12 are fired collectively.

【００８２】これにより、図３に示すように、７層の絶
縁層１０ａ〜１０ｇの所定の間に内部配線１１、ビアホ
ール導体１２、アンカー部１７、端面電極２となる導電
部材２１が形成され、さらに、表面電極３が形成された
本発明のセラミック基板が作製される。As a result, as shown in FIG. 3, the internal wiring 11, the via-hole conductor 12, the anchor portion 17, and the conductive member 21 serving as the end face electrode 2 are formed between predetermined portions of the seven insulating layers 10a to 10g. Further, the ceramic substrate of the present invention on which the surface electrode 3 is formed is manufactured.

【００８３】その後、表面処理として、さらに、厚膜抵
抗膜や厚膜保護膜の印刷・焼きつけ、メッキ処理、さら
にＩＣチップを含む電子部品の接合を行う。そして、こ
の後、分割溝７に沿って分割することにより、図１に示
したような分割回路基板１が得られる。即ち、分割回路
基板１は、図７に示すように、分割絶縁基体の外周面に
形成された凹部３１に、該凹部３１の内方に突出し、か
つ、端面電極２の端部２４を被覆する突出部３３が設け
られて形成されている。また、端面電極２に接続された
Ｔ字状のアンカー部１７が形成されている。Thereafter, as a surface treatment, printing and baking of a thick-film resistive film and a thick-film protective film, plating, and bonding of electronic components including an IC chip are further performed. After that, by dividing along the dividing groove 7, the divided circuit board 1 as shown in FIG. 1 is obtained. That is, as shown in FIG. 7, the divided circuit board 1 projects inwardly of the recess 31 formed on the outer peripheral surface of the divided insulating base and covers the end 24 of the end face electrode 2. The projection 33 is provided and formed. Further, a T-shaped anchor portion 17 connected to the end face electrode 2 is formed.

【００８４】本発明のセラミック基板の製造方法によれ
ば、貫通穴や端面電極用貫通溝、アンカー部用貫通溝が
フォトターゲットを用いて、露光・現像処理によって作
製されるため、フォトターゲットのパターンによって
も、複雑形状や種々の大きさの端面電極やアンカー部、
ビアホール導体が形成され、接続する相手部材に対応し
た形状，大きさとすることができる。According to the method for manufacturing a ceramic substrate of the present invention, the through-hole, the through-groove for the end face electrode, and the through-groove for the anchor portion are formed by exposure and development using a photo target. Depending on the end face electrode and anchor part of complicated shape and various sizes,
A via-hole conductor is formed, and the shape and size can be adjusted to correspond to the mating member to be connected.

【００８５】また、従来の製造方法、即ち、金型やＮＣ
パンチの打ち抜きでは得ることができない大きな径、ま
たは小さな径の貫通溝や貫通穴を形成でき、さらに相対
位置精度の高い貫通穴の形成が可能である。Further, the conventional manufacturing method, that is, the mold and the NC
It is possible to form a through groove or a through hole having a large diameter or a small diameter that cannot be obtained by punching a punch, and it is possible to form a through hole with high relative positional accuracy.

【００８６】また、絶縁層となるスリップ材の塗布によ
り絶縁層成形体が形成されるため、絶縁層成形体の表面
が、内部配線の配線パターンの積層状態にかかわらず、
常に平面状態を維持でき、絶縁層成形体上に配線パター
ンを形成するにあたって、非常に精度が高くなる。Further, since the insulating layer molded body is formed by applying the slip material serving as the insulating layer, the surface of the insulating layer molded body is irrespective of the lamination state of the wiring pattern of the internal wiring.
The planar state can always be maintained, and the precision in forming the wiring pattern on the molded insulating layer becomes extremely high.

【００８７】さらに、本発明の分割回路基板では、絶縁
基体の外周面に形成された凹部の内方に突出した突出部
により、端面電極の端部が被覆されることになり、端面
電極が分割回路基板の外周面には露出せず、外部から直
接的に力が作用するようなことが殆どなく、分割回路基
板の取り扱い時に端面電極が剥がれ落ちる等の問題を改
善することができる。また、セラミック基板の分割時に
おいても、端面電極となる導電部材を直接分割すること
がないため力が作用せず、端面電極の剥離を防止するこ
とができる。さらに、アンカー部により端面電極が基板
に確実に固定されることになるので、端面電極の剥離を
防止することができるとともに、アンカー部を関して端
面電極に内部配線等を確実に接続することができる。Further, in the divided circuit board according to the present invention, the end of the end face electrode is covered by the protrusion projecting inward from the concave portion formed on the outer peripheral surface of the insulating base, and the end face electrode is divided. It is not exposed to the outer peripheral surface of the circuit board, and there is almost no possibility that a force is directly applied from the outside. Thus, it is possible to improve the problem that the end face electrode peels off when the divided circuit board is handled. In addition, even when the ceramic substrate is divided, the conductive member serving as the end face electrode is not directly divided, so that no force acts and separation of the end face electrode can be prevented. Furthermore, since the end face electrode is securely fixed to the substrate by the anchor portion, peeling of the end face electrode can be prevented, and internal wiring and the like can be reliably connected to the end face electrode with respect to the anchor portion. it can.

【００８８】上述の実施例では、内部配線１１として、
Ａｕ系、Ａｇ系、Ｃｕ系の低融点金属材料を用いた低温
焼成のセラミック基板の製造方法で説明したが、内部配
線１１として、タングステン、モリブデンなどの高融点
金属材料を用いた、１３００℃前後で焼成されるセラミ
ック基板に、本発明の製造方法を適用しても構わない。
この場合、スリップ材のガラス材料の組成を所定成分と
し、さらにセラミック材料との混合比率を所定に設定す
る必要がある。In the above embodiment, the internal wiring 11 is
The method of manufacturing a low-temperature sintering ceramic substrate using a Au-based, Ag-based, or Cu-based low-melting-point metal material has been described, but a high-melting-point metal material such as tungsten or molybdenum is used as the internal wiring 11 at around 1300 ° C. The manufacturing method of the present invention may be applied to a ceramic substrate fired in the above.
In this case, it is necessary to set the composition of the glass material of the slip material as a predetermined component, and further set the mixing ratio with the ceramic material to a predetermined value.

【００８９】尚、アンカー部１７は、絶縁基体１３の厚
み方向に貫通するように設けても良いが、例えば、図３
の絶縁層１０ａと１０ｂのみに形成したり、絶縁層１０
ｄのみに形成しても良い。The anchor portion 17 may be provided so as to penetrate in the thickness direction of the insulating base 13;
May be formed only on the insulating layers 10a and 10b,
It may be formed only in d.

【００９０】[0090]

【発明の効果】本発明によれば、内部配線と端面電極の
接続信頼性が良好であり、分割時及び、使用時に端面電
極の導体部が剥がれ落ちる等の問題が改善される。ま
た、製造工数も少なく、多数個取りの可能なセラミック
回路基板が実現可能となる。また、多数個取りができる
ことから、セラミック回路基板の表面に部品を実装する
際に実装効率も高くなる利点があげられる。According to the present invention, the connection reliability between the internal wiring and the end face electrode is good, and the problem that the conductor of the end face electrode peels off at the time of division and use is improved. Further, the number of manufacturing steps is small, and a ceramic circuit board that can be manufactured in large numbers can be realized. In addition, since a large number of individual components can be obtained, there is an advantage that mounting efficiency is increased when components are mounted on the surface of the ceramic circuit board.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の製造方法により製造されたセラミック
基板を分割して得られた分割回路基板の斜視図である。FIG. 1 is a perspective view of a divided circuit board obtained by dividing a ceramic substrate manufactured by a manufacturing method of the present invention.

【図２】本発明の製造方法により得られたセラミック基
板を示す斜視図である。FIG. 2 is a perspective view showing a ceramic substrate obtained by the manufacturing method of the present invention.

【図３】図２のＡ線における一部断面図である。FIG. 3 is a partial cross-sectional view taken along line A of FIG. 2;

【図４】本発明の製造方法を説明するための工程図であ
る。FIG. 4 is a process chart for explaining the manufacturing method of the present invention.

【図５】焼成前の積層成形体を示す断面図である。FIG. 5 is a cross-sectional view showing a laminated molded body before firing.

【図６】図３における一対の馬蹄形状の導電部材近傍を
示す斜視図である。FIG. 6 is a perspective view showing the vicinity of a pair of horseshoe-shaped conductive members in FIG. 3;

【図７】分割回路基板の端面電極部分を拡大して示す斜
視図である。FIG. 7 is an enlarged perspective view showing an end face electrode portion of the divided circuit board.

【図８】従来のセラミック基板の導電部材部分を拡大し
て示す平面図である。FIG. 8 is an enlarged plan view showing a conductive member portion of a conventional ceramic substrate.

【符号の説明】[Explanation of symbols]

１・・・分割回路基板 ２・・・端面電極 ４・・・チップ部品 ７・・・分割溝 １０ａ〜１０ｇ・・・絶縁層 １１・・・内部配線 １２・・・ビアホール導体 １３・・・絶縁基体 １４・・・支持基板 １７・・・アンカー部 ２０ａ〜２０ｇ・・・絶縁層成形体 ２１、２２・・・導電部材 ２３・・・端面電極用貫通溝 ２４・・・端部 ２６・・・配線パターン ２７・・・積層成形体 ２９・・・柱状体 ３１・・・凹部 ３３・・・突出部 ３７・・・アンカー部用貫通溝 DESCRIPTION OF SYMBOLS 1 ... Divided circuit board 2 ... End surface electrode 4 ... Chip component 7 ... Divided groove 10a-10g ... Insulating layer 11 ... Internal wiring 12 ... Via-hole conductor 13 ... Insulation Base 14 Support substrate 17 Anchor portions 20a to 20g Insulating layer molded body 21, 22 Conductive member 23 End surface electrode through groove 24 End 26 Wiring pattern 27 ... laminated molded body 29 ... columnar body 31 ... concave part 33 ... protruding part 37 ... through groove for anchor part

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平５−37109（ＪＰ，Ａ) 特開 平７−122831（ＪＰ，Ａ) 特開 平１−95593（ＪＰ，Ａ) 特開 平７−192961（ＪＰ，Ａ) 特開 平７−15143（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 3/46 H05K 1/02 H05K 3/00 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-37109 (JP, A) JP-A-7-122831 (JP, A) JP-A-1-95593 (JP, A) JP-A-7- 192961 (JP, A) JP-A-7-15143 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H05K 3/46 H05K 1/02 H05K 3/00

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】セラミックスからなる絶縁層を複数積層し
てなる絶縁基体と、前記絶縁基体表面に形成された分割
溝とを有し、該分割溝で分割した際にそれぞれが内部配
線と複数の端面電極を有する分割回路基板となるセラミ
ック基板であって、前記絶縁基体はその厚み方向に形成
され、かつ前記分割溝上に形成された貫通孔を有し、該
貫通孔の内面に、前記分割回路基板の端面電極となる一
対の馬蹄形状の導電部材を形成するとともに、該一対の
導電部材の端部を対向させ、前記一対の導電部材の対向
する端部間に前記分割溝が形成された突出部を形成し、
且つ前記導電部材と接続されるアンカー部を前記分割回
路基板となる領域に前記絶縁基体の厚み方向に形成して
なることを特徴とするセラミック基板。An insulating substrate formed by laminating a plurality of insulating layers made of ceramics; and a dividing groove formed on a surface of the insulating substrate. A ceramic substrate serving as a divided circuit substrate having an end surface electrode, wherein the insulating base is formed in a thickness direction thereof and has a through hole formed on the division groove, and the divided circuit is formed on an inner surface of the through hole. A pair of horseshoe-shaped conductive members serving as end surface electrodes of the substrate are formed, the ends of the pair of conductive members are opposed to each other, and the divided groove is formed between the opposed ends of the pair of conductive members. Form a part,
A ceramic substrate, wherein an anchor portion connected to the conductive member is formed in a thickness direction of the insulating base in a region to be the divided circuit board. 【請求項２】セラミックスからなる絶縁層を複数積層し
てなる絶縁基体と、前記絶縁基体表面に形成された分割
溝とを有し、該分割溝で分割した際にそれぞれが内部配
線と複数の端面電極を有する分割回路基板となるセラミ
ック基板の製造方法であって、 セラミックスからなる絶縁層材料、光硬化可能なモノマ
ー、有機バインダを含有するスリップ材を薄層化し乾燥
して絶縁層成形体を形成する工程と、 該絶縁層成形体の表面に前記端面電極およびこの端面電
極に接続されるアンカー部の形成位置を除いて露光処理
を施す工程と、 露光処理を施した前記絶縁層成形体を現像処理して、端
面電極を形成する位置に一対の馬蹄形状の端面電極用貫
通溝をその端部同士が対向するように所定間隔をおいて
形成するとともに、前記端面電極用貫通溝と連続するア
ンカー部用貫通溝を形成する工程と、 該端面電極用貫通溝およびアンカー部用貫通溝内に導電
性ペーストを充填する工程と、 前記絶縁層成形体の表面に導電性ペーストを印刷して内
部配線パターンを形成する工程と、 前記端面電極用貫通溝およびアンカー部用貫通溝内に導
電性ペーストを充填した前記絶縁層成形体に露光処理前
の絶縁層成形体を積層する工程と、 露光処理から積層までの工程を繰り返して形成された積
層成形体の表面に、前記分割回路基板毎に分割するため
の分割溝を前記一対の馬蹄形状の端面電極用貫通溝の間
を通過するように形成する工程と、 該分割溝が形成された積層成形体を焼成する工程とを具
備してなることを特徴とするセラミック基板の製造方
法。2. An insulating substrate formed by laminating a plurality of insulating layers made of ceramics, and a dividing groove formed on the surface of the insulating substrate. A method of manufacturing a ceramic substrate to be a divided circuit substrate having an end face electrode, comprising thinning and drying an insulating layer material made of ceramics, a photocurable monomer, and a slip material containing an organic binder to form an insulating layer molded body. Forming, exposing the surface of the insulating layer molded body to an exposure process excluding the formation position of the end face electrode and the anchor portion connected to the end face electrode, and forming the exposed insulating layer molded body. Developing and forming a pair of horseshoe-shaped end face electrode through grooves at predetermined intervals at positions where end face electrodes are to be formed so that the ends thereof face each other, and forming the end face electrode through grooves. Forming a continuous anchor portion through groove; filling the end surface electrode through groove and the anchor portion through groove with a conductive paste; and printing a conductive paste on the surface of the insulating layer molded body. Forming an internal wiring pattern, and laminating the insulating layer molded body before the exposure treatment on the insulating layer molded body filled with a conductive paste in the end face electrode through groove and the anchor part through groove, On the surface of the laminated molded body formed by repeating the steps from the exposure processing to the lamination, a division groove for dividing the divided circuit boards is passed between the pair of horseshoe-shaped end surface electrode through grooves. And a step of firing the laminated molded body in which the divided grooves are formed. 【請求項３】分割絶縁基体の外周面にその厚み方向に形
成された凹部に、該凹部に沿って端面電極を形成してな
る分割回路基板において、前記凹部に、前記端面電極の
端部を被覆する突出部を一体に設けてなるとともに、前
記端面電極に接続されるアンカー部を前記分割絶縁基体
に厚み方向に設けてなることを特徴とする分割回路基
板。3. A divided circuit board having an end face electrode formed along a concave portion formed in a thickness direction on an outer peripheral surface of a divided insulating base, wherein the end portion of the end face electrode is formed in the concave portion. A divided circuit board, wherein a projecting portion to be covered is provided integrally, and an anchor portion connected to the end face electrode is provided in the thickness direction on the divided insulating substrate.
JP22701396A 1996-08-28 1996-08-28 Ceramic substrate, method of manufacturing the same, and divided circuit board Expired - Fee Related JP3236782B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22701396A JP3236782B2 (en) 1996-08-28 1996-08-28 Ceramic substrate, method of manufacturing the same, and divided circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22701396A JP3236782B2 (en) 1996-08-28 1996-08-28 Ceramic substrate, method of manufacturing the same, and divided circuit board

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JP3236782B2 true JP3236782B2 (en) 2001-12-10

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* Cited by examiner, † Cited by third party
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JP2000307200A (en) * 1999-04-23 2000-11-02 Kyocera Corp Multi-section ceramic wiring board
TW498602B (en) 2000-05-30 2002-08-11 Alps Electric Co Ltd Circuit unit
KR100495211B1 (en) * 2002-11-25 2005-06-14 삼성전기주식회사 Ceramic multilayer board and its manufacture
JP2008130618A (en) * 2006-11-16 2008-06-05 Murata Mfg Co Ltd Multilayer wiring board
JP5383545B2 (en) * 2009-05-27 2014-01-08 京セラ株式会社 Multi-cavity wiring board and wiring board
WO2011037260A1 (en) * 2009-09-28 2011-03-31 京セラ株式会社 Structure and method for producing same
US8461462B2 (en) 2009-09-28 2013-06-11 Kyocera Corporation Circuit substrate, laminated board and laminated sheet
JP2014127678A (en) * 2012-12-27 2014-07-07 Kyocera Corp Wiring board and electronic device
CN112601359A (en) * 2020-11-27 2021-04-02 苏州华博电子科技有限公司 Manufacturing method and manufacturing die for front and side continuous thin film circuit
WO2023091328A1 (en) * 2021-11-22 2023-05-25 Corning Incorporated Methods and apparatus for manufacturing an electronic apparatus

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