JP2003101225A - Ceramic substrate and divided circuit board - Google Patents

Ceramic substrate and divided circuit board

Info

Publication number
JP2003101225A
JP2003101225A JP2001294744A JP2001294744A JP2003101225A JP 2003101225 A JP2003101225 A JP 2003101225A JP 2001294744 A JP2001294744 A JP 2001294744A JP 2001294744 A JP2001294744 A JP 2001294744A JP 2003101225 A JP2003101225 A JP 2003101225A
Authority
JP
Japan
Prior art keywords
insulating
divided
columnar
substrate
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001294744A
Other languages
Japanese (ja)
Inventor
Norimitsu Fukamizu
則光 深水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001294744A priority Critical patent/JP2003101225A/en
Publication of JP2003101225A publication Critical patent/JP2003101225A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a ceramic substrate capable of improving the connecting reliability of a wiring layer to an end face electrode and to provide a divided circuit board. SOLUTION: The ceramic substrate comprises an insulating base 21 obtained by laminating a plurality of insulating layers 21a to 21h, dividing grooves 17 formed on the surface of the base 21, and a dividing circuit board having punched holes 27 formed in a thickness direction of the base 2 and formed on the grooves 17 and having a plurality of end face electrodes 2 formed when the base 21 is divided at the grooves 17. The substrate further comprises a plurality of columnar conductors 9 partly exposed to the holes 27 and formed at a predetermined interval in such a manner that the conductors 9 of the upper and lower adjacent insulating layers 21a to 21h are partly superposed as seen from above the base 21, and the superposed parts of the conductors 9 are exposed to the holes 27.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、単位ブロック毎に
分割した際にはそれぞれが複数の端面電極を有する分割
回路基板となるセラミック基板及び分割回路基板に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic substrate and a divided circuit board which are divided circuit boards each having a plurality of end face electrodes when divided into unit blocks.

【0002】[0002]

【従来技術】近年、電子機器は小型軽量化、携帯化が進
んでおり、それに用いられる回路ブロックもその動向に
呼応する形で、小型軽量薄型化、表面実装化、複合化が
押し進められている。
2. Description of the Related Art In recent years, electronic devices have become smaller and lighter and more portable, and circuit blocks used therein have been made smaller, lighter and thinner, surface-mounted, and compounded in response to the trend. .

【0003】このような動向の中で、セラミック回路基
板は、その優れた放熱性や低誘電損失等の特徴から多用
されており、高周波モジュールとしてその応用が進めら
れている。
In such a trend, the ceramic circuit board is widely used because of its excellent heat dissipation and low dielectric loss, and its application as a high frequency module is being promoted.

【0004】高周波モジュール用セラミック回路基板は
マザーボードに半田接合されて用いられている。端面電
極はセラミック回路基板に形成され、マザーボードへの
固定と信号を伝達する役割を持つものである。そして、
その端面電極の構造を製造方法の観点からみると、大別
して2種類の製造方法がある。
A ceramic circuit board for a high frequency module is used by being soldered to a mother board. The end surface electrodes are formed on the ceramic circuit board and have a role of fixing to the mother board and transmitting signals. And
From the viewpoint of the manufacturing method, there are roughly two types of manufacturing methods for the structure of the end face electrode.

【0005】まず第1の方法はスルーホール厚膜構造と
呼ばれる構造で、既に端面電極用のスルーホールが形成
された既焼成のセラミック回路基板に吸引等の技術を併
用し、厚膜印刷技術等により導電性ペーストをスルーホ
ール内壁面にコーティングし、焼き付ける方法により達
成される構造である。本方法の利点は基板を多数個取り
で処理出来る為、即ち、単位ブロック毎に分割した際に
はそれぞれが複数の端面電極を有する分割回路基板とす
ることができ、工数削減に有利である。
The first method is a structure called a through-hole thick film structure, in which a technique such as suction is used in combination with a fired ceramic circuit board on which through holes for end face electrodes have already been formed, and a thick film printing technique or the like. The conductive paste is coated on the inner wall surface of the through hole, and then baked. The advantage of this method is that a large number of substrates can be processed, that is, when divided into unit blocks, each can be a divided circuit substrate having a plurality of end face electrodes, which is advantageous in reducing the number of steps.

【0006】第2の構造は第1の構造を応用したもので
あり、未焼成のグリーンシート1層毎にスルーホールを
形成し、該スルーホールの内壁面に導電性ペーストをコ
ーティングし、該スルーホール厚膜構造をとったものを
積層一体化することにより達成される構造である。この
利点は配線層と端面電極の接合がとり易い点にある。
The second structure is an application of the first structure, in which a through hole is formed in each green sheet of green sheets, and the inner wall surface of the through hole is coated with a conductive paste, and the through hole is formed. This is a structure achieved by laminating and integrating a hole thick film structure. The advantage is that the wiring layer and the end face electrode can be easily joined.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上記ス
ルーホール厚膜構造では、セラミック基板が配線層を有
していた場合、その未焼成のセラミック基板に積層後一
括してスルーホールを形成するには、金型を用いたパン
チング工法等により形成する必要があるが、打抜孔形成
位置には、積層方向に配線層とグリーンシートが交互に
形成されており、しかも、打抜孔形成位置では配線層が
形成されない、積層方向にグリーンシートのみ形成され
た部分の割合が多いため、金型によるパンチ時に、より
強度の大きいグリーンシートが配線層の端部を打抜方向
に押し出して配線層が崩れ、端面電極との接点がとれに
くいという問題があった。
However, in the above-mentioned through-hole thick film structure, in the case where the ceramic substrate has a wiring layer, it is necessary to form the through-holes after being laminated on the unfired ceramic substrate. , It is necessary to form by a punching method using a die, but at the punching hole forming position, the wiring layer and the green sheet are alternately formed in the stacking direction, and moreover, the wiring layer is formed at the punching hole forming position. Since there is a large proportion of the part that is not formed and only the green sheet is formed in the stacking direction, when punching with the mold, the green sheet with higher strength pushes the end of the wiring layer in the punching direction and the wiring layer collapses, and the end surface There is a problem that it is difficult to make contact with the electrodes.

【0008】また、グリーンシート1層毎にスルーホー
ルを形成し、該スルーホールの内壁面に導電性ペースト
をコーティングし、最後に積層一体化する場合には、各
グリーンシートの積層ズレが発生し、スルーホール内壁
面が凹凸となり、端面電極表面も凹凸になりやすく、同
様に、配線層と端面電極の接続信頼性が低下するといっ
た問題があった。
Further, when a through hole is formed in each green sheet layer, the inner wall surface of the through hole is coated with a conductive paste, and finally the layers are laminated and integrated, a deviation of the lamination of the green sheets occurs. However, the inner wall surface of the through-hole becomes uneven, and the surface of the end face electrode also tends to become uneven, and similarly, there is a problem that the connection reliability between the wiring layer and the end face electrode decreases.

【0009】本発明は、配線層と端面電極との接続信頼
性を向上できるセラミック基板及び分割回路基板を提供
することを目的とする。
It is an object of the present invention to provide a ceramic substrate and a divided circuit substrate which can improve the connection reliability between the wiring layer and the end face electrode.

【0010】[0010]

【課題を解決するための手段】本発明のセラミック基板
は、セラミックスからなる絶縁層を複数積層してなる絶
縁基体と、前記絶縁層間に形成された配線層と、該配線
層に接続されるビアホール導体と、前記絶縁基体表面に
形成された分割溝と、前記絶縁基体の厚み方向に形成さ
れ、かつ前記分割溝の延長線上に形成された打抜孔とを
有し、前記分割溝で前記絶縁基体を分割した際にそれぞ
れが複数の端面電極を有する分割回路基板となるセラミ
ック基板であって、前記各絶縁層の厚み方向に、前記打
抜孔内に一部露出する柱状導体を前記打抜孔に沿って所
定間隔をおいて複数形成するとともに、隣接する上下の
前記絶縁層の柱状導体が、前記絶縁基体の上方から見て
一部重畳し、該柱状導体の重畳部分が前記打抜孔内に露
出していることを特徴とする。
A ceramic substrate according to the present invention comprises an insulating substrate formed by laminating a plurality of insulating layers made of ceramics, a wiring layer formed between the insulating layers, and a via hole connected to the wiring layer. A conductor, a dividing groove formed on the surface of the insulating base, and a punching hole formed in the thickness direction of the insulating base and formed on an extension line of the dividing groove. Is a ceramic substrate that becomes a divided circuit board each having a plurality of end face electrodes when divided into, and a columnar conductor that is partially exposed in the punched hole along the punched hole in the thickness direction of each insulating layer. A plurality of columnar conductors of the upper and lower insulating layers that are adjacent to each other partially overlap each other when viewed from above the insulating base, and the overlapped portion of the columnar conductors is exposed in the punched hole. That And butterflies.

【0011】本発明のセラミック基板では、絶縁層成形
体の積層後に金型により打ち抜かれる打抜孔を中心にし
て、柱状導体が所定間隔をおいて連続的に配列されてい
る。そして、絶縁層成形体の積層終了後に金型により打
抜孔が打ち抜かれる時には、絶縁層成形体の厚み方向に
形成された柱状導体の一部が金型の打ち抜き面となるた
め、柱状導体の一部が除去され、打抜孔の内面に柱状導
体の一部が露出する。
In the ceramic substrate of the present invention, columnar conductors are continuously arranged at a predetermined interval centering on a punching hole punched by a die after the insulating layer molded body is laminated. Then, when the punching holes are punched out by the mold after the lamination of the insulating layer molded body is completed, a part of the columnar conductor formed in the thickness direction of the insulating layer molded body becomes the punching surface of the mold, so that The portion is removed, and a part of the columnar conductor is exposed on the inner surface of the punched hole.

【0012】また、各々の絶縁層に形成された柱状導体
は、隣接する上下の絶縁層に形成された柱状導体が互い
にオーバーラップして形成されているため、打抜孔の切
断面には柱状導体が、絶縁基体の上下面間に連続して形
成されていることになる。このため、切断面には、厚み
方向に絶縁層成形体が連続して存在することがなく、ま
た、各絶縁層には、厚み方向に貫通する柱状導体が形成
され、各絶縁層の柱状導体が重畳部分を介して接続され
ていることになるため、打ち抜く絶縁層の割合が少な
く、打抜時に絶縁層に作用する余分なストレスや、変形
が殆ど発生せず、配線層と端面電極との接続信頼性を向
上できる。
Further, since the columnar conductors formed in the respective insulating layers are formed by the columnar conductors formed in the adjacent upper and lower insulating layers overlapping each other, the columnar conductors are formed on the cut surface of the punched hole. Are continuously formed between the upper and lower surfaces of the insulating base. Therefore, the insulating layer molded body does not exist continuously in the thickness direction on the cut surface, and columnar conductors penetrating in the thickness direction are formed in each insulating layer. Since it is connected through the overlapping portion, the proportion of the insulating layer to be punched is small, and there is almost no extra stress or deformation that acts on the insulating layer during punching, and the wiring layer and the end face electrode The connection reliability can be improved.

【0013】また、従来のように、打抜孔の内面全面に
導体層を形成する場合よりも導体使用量を低減でき、安
価な基板を作製できる。
Further, the amount of the conductor used can be reduced and an inexpensive substrate can be manufactured as compared with the conventional case where the conductor layer is formed on the entire inner surface of the punched hole.

【0014】さらに、絶縁層成形体の積層終了後に一括
で打ち抜きを行なうため、従来のように、打抜孔の積層
ズレの影響による接続不良の発生もなく、さらにそれぞ
れの柱状導体は絶縁基体内部で電気的に接続されている
ため、接続信頼性の高い端面電極を提供することができ
る。
Furthermore, since the punching is carried out in a batch after the lamination of the insulating layer molded body is completed, there is no connection failure due to the influence of the stacking deviation of the punching holes as in the conventional case, and each columnar conductor is inside the insulating substrate. Since they are electrically connected, it is possible to provide an end face electrode with high connection reliability.

【0015】また、本発明では、絶縁層の柱状導体は、
打抜孔内への露出部分から前記絶縁層内部に向けて次第
に幅が大きくなる幅広部を有することが望ましい。これ
により、柱状導体が絶縁基体にアンカーされ、絶縁基体
からの脱落を防止でき、端面電極の絶縁基体への接続強
度を向上できる。
In the present invention, the columnar conductor of the insulating layer is
It is desirable to have a wide portion in which the width gradually increases from the exposed portion inside the punched hole toward the inside of the insulating layer. As a result, the columnar conductor is anchored to the insulating base, can be prevented from falling off from the insulating base, and the connection strength of the end face electrode to the insulating base can be improved.

【0016】さらに、本発明では、絶縁層の柱状導体
は、絶縁基体の上方から見て分割溝を除いて形成されて
いることが望ましい。これにより、分割溝で分割した際
には、絶縁層で分割されることになり、しかも柱状導体
は凹部内には露出することになるが、分割絶縁基体の外
周面には露出しておらず、外部の物体が衝突して柱状導
体が剥離や脱落するようなことがない。
Further, in the present invention, it is desirable that the columnar conductor of the insulating layer is formed excluding the dividing groove when viewed from above the insulating substrate. As a result, when divided by the dividing groove, it is divided by the insulating layer, and the columnar conductor is exposed in the recess, but is not exposed on the outer peripheral surface of the divided insulating substrate. The columnar conductor does not peel off or fall off due to collision with an external object.

【0017】本発明の分割回路基板は、セラミックスか
らなる絶縁層を複数積層してなる分割絶縁基体の外周面
に、かつ厚み方向に形成された凹部に、該凹部に端面電
極を形成してなる分割回路基板であって、前記端面電極
が、前記各絶縁層の厚み方向に、前記凹部に一部露出す
る柱状導体を前記凹部に沿って所定間隔をおいて複数形
成してなるとともに、隣接する上下の前記絶縁層の柱状
導体が、前記分割絶縁基体の上方から見て一部重畳し、
該柱状導体の重畳部分が前記凹部に露出していることを
特徴とする。
The divided circuit board of the present invention is formed by forming an end face electrode in a concave portion formed on the outer peripheral surface of a divided insulating substrate formed by laminating a plurality of insulating layers made of ceramics and in the thickness direction. In the divided circuit board, the end face electrode is formed by forming a plurality of columnar conductors partially exposed in the recess along the recess at predetermined intervals in the thickness direction of each insulating layer, and adjacent to each other. The columnar conductors of the upper and lower insulating layers partially overlap with each other when viewed from above the divided insulating substrate,
The overlapping portion of the columnar conductor is exposed in the recess.

【0018】このような分割回路基板では、上記したセ
ラミック基板と同様に、配線層と端面電極との接続信頼
性を向上できる。
In such a divided circuit board, it is possible to improve the connection reliability between the wiring layer and the end face electrode, as in the ceramic board described above.

【0019】また、分割絶縁基体の凹部に金属層が形成
されていることが望ましい。この金属層が柱状導体の露
出部分を含む凹部全面に形成されているため、分割回路
基板をマザーボードにハンダ付けする際に強固に接合で
きる。
Further, it is desirable that a metal layer is formed in the recess of the divided insulating substrate. Since this metal layer is formed on the entire surface of the concave portion including the exposed portion of the columnar conductor, it is possible to firmly bond the divided circuit board when soldering it to the mother board.

【0020】[0020]

【発明の実施の形態】図1は、本発明のセラミック基板
を分割溝で分割して形成した分割回路基板の斜視図を示
すもので、符号1は分割絶縁基体を示しており、入出力
端子、電源端子、グランド端子等の端子が端面電極2と
して示されている。端面電極2は分割絶縁基体1の側面
に露出して形成されている。
FIG. 1 is a perspective view of a divided circuit board formed by dividing a ceramic substrate of the present invention by dividing grooves. Reference numeral 1 indicates a divided insulating base, and an input / output terminal. Terminals such as a power supply terminal and a ground terminal are shown as the end surface electrodes 2. The end surface electrode 2 is formed so as to be exposed on the side surface of the divided insulating base 1.

【0021】また、分割絶縁基体1の上面には表面電極
(配線)3が形成され、この表面電極3には抵抗器、コ
ンデンサ、インダクタ等のチップ部品4が接続されてい
る。
A surface electrode (wiring) 3 is formed on the upper surface of the divided insulating substrate 1, and a chip component 4 such as a resistor, a capacitor or an inductor is connected to the surface electrode 3.

【0022】また、分割絶縁基体1にはキャビティ部5
が形成されており、このキャビティ部5には半導体ベア
チップ6が収容され、ワイヤにより表面電極3と接続さ
れている。
Further, the divided insulating substrate 1 has a cavity 5
The semiconductor bare chip 6 is housed in the cavity 5 and is connected to the surface electrode 3 by a wire.

【0023】そして、本発明の分割回路基板では、分割
絶縁基体1の外周面に、その厚み方向に複数の凹部7が
形成され、図2に示すように、これらの凹部7に沿って
端面電極2が形成されている。端面電極2は、分割絶縁
基体1を構成する各絶縁層1a〜1hの厚み方向に、凹
部7に一部露出する柱状導体9を、凹部7に沿って所定
間隔をおいて複数形成して構成され、上下の絶縁層1a
〜1hの柱状導体9が、分割絶縁基体1の上方から見て
重畳し、柱状導体9の重畳部分11も凹部7に露出して
いる。
In the split circuit board of the present invention, a plurality of recesses 7 are formed on the outer peripheral surface of the split insulating substrate 1 in the thickness direction thereof, and as shown in FIG. 2 is formed. The end surface electrode 2 is formed by forming a plurality of columnar conductors 9 that are partially exposed in the recesses 7 along the recesses 7 at predetermined intervals in the thickness direction of each of the insulating layers 1a to 1h that form the divided insulating substrate 1. The upper and lower insulating layers 1a
The columnar conductors 9 of 1 h overlap with each other when viewed from above the divided insulating substrate 1, and the overlapped portion 11 of the columnar conductor 9 is also exposed in the recess 7.

【0024】即ち、柱状導体9は円柱の一部が凹部7に
より除去された形状をなしており、その露出部分から、
絶縁層1a〜1hの内部に向けて幅が大きくなる幅広部
10が形成されている。柱状導体9の一部は格子状とな
るように凹部7に露出しており、重畳部分11により、
柱状導体9は、分割絶縁基体1の厚み方向、及ぶ横方向
に相互に電気的に接続されている。これにより端面電極
2が構成されている。図1の場合、柱状導体9が外部に
露出した、凹部7及び、凹部7が形成された分割絶縁基
体1表面に金属層8が形成されている。尚、金属層8は
形成しなくても良いが、半田によるマザーボードへの接
合の観点から、金属層8を形成することが望ましい。各
絶縁層1a〜1hには、複数の柱状導体9が形成されて
いるが、各絶縁層1a〜1hに形成された柱状導体9の
うち少なくとも1つには配線層が接続される。
That is, the columnar conductor 9 has a shape in which a part of the cylinder is removed by the recess 7, and from the exposed portion,
A wide portion 10 having a width that increases toward the inside of the insulating layers 1a to 1h is formed. Part of the columnar conductor 9 is exposed in the recess 7 so as to form a lattice, and the overlapping portion 11
The columnar conductors 9 are electrically connected to each other in the thickness direction of the divided insulating base body 1 and in the lateral direction. Thereby, the end face electrode 2 is formed. In the case of FIG. 1, the metal layer 8 is formed on the surface of the concave portion 7 where the columnar conductor 9 is exposed to the outside and the surface of the divided insulating substrate 1 in which the concave portion 7 is formed. Although the metal layer 8 need not be formed, it is desirable to form the metal layer 8 from the viewpoint of joining to the mother board by soldering. A plurality of columnar conductors 9 are formed on each of the insulating layers 1a to 1h, but a wiring layer is connected to at least one of the columnar conductors 9 formed on each of the insulating layers 1a to 1h.

【0025】図3は、本発明のセラミック基板の斜視図
を示すもので、このセラミック基板には分割溝17が形
成され、この分割溝17の延長線上に打抜孔19が形成
されている。このセラミック基板を分割溝17で分割す
ることにより、上記図1の分割回路基板が得られる。
尚、図3では、打抜孔19を便宜上簡略化して記載し
た。
FIG. 3 is a perspective view of the ceramic substrate of the present invention, in which a dividing groove 17 is formed in this ceramic substrate, and a punching hole 19 is formed on an extension line of the dividing groove 17. By dividing this ceramic substrate along the dividing groove 17, the divided circuit substrate shown in FIG. 1 is obtained.
In FIG. 3, the punching hole 19 is simplified for convenience.

【0026】このセラミック基板の絶縁基体21は、図
4に示すように、絶縁層21a〜21h、配線層23、
ビアホール導体24とから構成されており、絶縁層21
a〜21hは、例えば、セラミック、又はガラスセラミ
ック材料からなり、それぞれの厚みは40〜150μm
とされている。
As shown in FIG. 4, the insulating substrate 21 of the ceramic substrate has insulating layers 21a to 21h, a wiring layer 23,
And the insulating layer 21.
a to 21h are made of, for example, ceramic or glass ceramic material, and each has a thickness of 40 to 150 μm.
It is said that.

【0027】このような絶縁層21bと絶縁層21c、
絶縁層21dと絶縁層21e、絶縁層21fと絶縁層2
1g間には配線層23が形成されている。配線層23
は、金系、銀系、銅系の金属材料、例えば銀系導体から
なっている。また、配線層23はビアホール導体24に
よって接続されているものもあれば、容量結合等で分布
定数的に接続されるものもある。このビアホール導体2
4も配線層23と同様に金系、銀系、銅系の金属材料、
例えば銀系導体からなっている。
The insulating layer 21b and the insulating layer 21c,
Insulating layer 21d and insulating layer 21e, insulating layer 21f and insulating layer 2
The wiring layer 23 is formed between 1g. Wiring layer 23
Is made of a gold-based, silver-based, or copper-based metal material, for example, a silver-based conductor. The wiring layer 23 may be connected by the via-hole conductor 24, or may be connected in a distributed constant manner by capacitive coupling or the like. This via hole conductor 2
Similarly to the wiring layer 23, 4 is a metal material of gold, silver or copper,
For example, it is made of a silver-based conductor.

【0028】セラミック基板には、図5(a)に示すよ
うに、分割溝17上に複数の円形状の打抜孔27が形成
されており、これらの打抜孔27内には、複数の柱状導
体9の一部が露出し、分割溝17で分割した際に端面電
極2となる。
As shown in FIG. 5A, the ceramic substrate has a plurality of circular punched holes 27 formed in the dividing groove 17, and the punched holes 27 have a plurality of columnar conductors. Part of 9 is exposed and becomes the end face electrode 2 when divided by the dividing groove 17.

【0029】打抜孔27の内面には、図5(a)(b)
に示すように、各絶縁層21a〜21hの厚み方向に、
打抜孔27内に一部露出する柱状導体9が、打抜孔27
に沿って所定間隔をおいて複数形成され、上下の絶縁層
21a〜21hの柱状導体9が、絶縁基体21の上方か
ら見て一部重畳し、柱状導体9の重畳部分11が打抜孔
27内に露出している。尚、打抜孔27は図5(c)に
示すように断面が楕円形状であっても良く、その場合の
柱状導体9の配列は図5(d)に示すようになる。
The inner surface of the punching hole 27 is shown in FIGS.
As shown in, in the thickness direction of each of the insulating layers 21a to 21h,
The columnar conductor 9 partially exposed in the punching hole 27 is
A plurality of columnar conductors 9 of the upper and lower insulating layers 21a to 21h are formed at predetermined intervals along the line and partially overlap each other when viewed from above the insulating substrate 21, and the overlapped portion 11 of the columnar conductor 9 is formed in the punching hole 27. Is exposed to. The punched holes 27 may have an elliptical cross section as shown in FIG. 5C, and the arrangement of the columnar conductors 9 in this case is as shown in FIG. 5D.

【0030】本発明のセラミック基板の製法を、図6に
基いて説明する。先ず、絶縁層21a〜21hとなるス
リップ材を作製する。スリップ材は、例えば、ガラスセ
ラミックスまたはセラミック原料粉末、光硬化可能なモ
ノマー、例えばポリオキシエチル化トリメチロールプロ
パントリアクリレートと、有機バインダ、例えばアルキ
ルメタクリレートと、可塑剤とを、有機溶剤、例えばエ
チルカルビトールアセテートに混合し、ボールミルで混
練して作製される。
A method of manufacturing the ceramic substrate of the present invention will be described with reference to FIG. First, a slip material to be the insulating layers 21a to 21h is manufactured. The slip material is, for example, glass ceramics or ceramic raw material powder, a photocurable monomer such as polyoxyethylated trimethylolpropane triacrylate, an organic binder such as alkyl methacrylate, a plasticizer, and an organic solvent such as ethyl carbyl. It is prepared by mixing with tall acetate and kneading with a ball mill.

【0031】原料粉末としては、例えば、金属元素とし
て少なくともMg、Ti、Caを含有する複合酸化物で
あって、その金属元素酸化物による組成式を(1−x)
MgTiO3−xCaTiO3(但し、式中xは重量比を
表し、0.01≦x≦0.15)で表される主成分10
0重量部に対して、硼素含有化合物をB23換算で3〜
30重量部、アルカリ金属含有化合物をアルカリ金属炭
酸塩換算で1〜25重量部添加含有してなるものが用い
られる。
The raw material powder is, for example, a composite oxide containing at least Mg, Ti, and Ca as metal elements, and the composition formula of the metal element oxide is (1-x).
Main component 10 represented by MgTiO 3 —xCaTiO 3 (where x represents a weight ratio, 0.01 ≦ x ≦ 0.15)
With respect to 0 part by weight, the boron-containing compound is 3 to 3 in terms of B 2 O 3.
The one containing 30 parts by weight and 1 to 25 parts by weight of the alkali metal-containing compound in terms of alkali metal carbonate is used.

【0032】尚、上述では溶剤系スリップ材を作製して
いるが、親水性の官能基を付加した光硬化可能なモノマ
ー、例えば多官能基メタクリレートモノマー、有機バイ
ンダ、例えばカルボキシル変性アルキルメタクリレート
を用いて、イオン交換水で混練した水系スリップ材であ
っても良い。
Although a solvent-based slip material is prepared in the above, a photo-curable monomer having a hydrophilic functional group added thereto, for example, a polyfunctional methacrylate monomer, an organic binder such as a carboxyl-modified alkyl methacrylate is used. Alternatively, a water-based slip material kneaded with ion-exchanged water may be used.

【0033】原料粉末としては、例えば、ガラス材料で
あるSiO2、Al23、ZnO、MgO、B23を主
成分とする結晶化ガラス粉末70重量%とセラミック材
料であるアルミナ粉末30重量%とからなるものも用い
られる。原料粉末は、特に限定されるものではない。
As the raw material powder, for example, 70% by weight of crystallized glass powder containing SiO 2 , Al 2 O 3 , ZnO, MgO, and B 2 O 3 which are glass materials as main components and alumina powder 30 which is a ceramic material are used. Also used are those consisting of wt%. The raw material powder is not particularly limited.

【0034】また、柱状導体9、ビアホール導体24、
配線層23および表面電極3となる導電性ペーストを作
製する。導電性ペーストは、低融点で且つ低抵抗の金属
材料である例えば銀粉末と、硼珪酸系低融点ガラス、例
えばB23−SiO2−BaOガラス、CaO−B23
−SiO2ガラス、CaO−Al23−B23−SiO2
ガラスと、有機バインダ、例えばエチルセルロースと
を、有機溶剤、例えば2,2,4−トリメチル−1,3
−ペンタジオールモノイソブチレートに混合し、3本ロ
ーラーにより均質混練して作製される。
Further, the columnar conductor 9, the via-hole conductor 24,
A conductive paste to be the wiring layer 23 and the surface electrode 3 is prepared. The conductive paste is a low melting point and low resistance metallic material such as silver powder and borosilicate low melting point glass such as B 2 O 3 —SiO 2 —BaO glass and CaO—B 2 O 3.
-SiO 2 glass, CaO-Al 2 O 3 -B 2 O 3 -SiO 2
Glass and an organic binder such as ethyl cellulose are mixed with an organic solvent such as 2,2,4-trimethyl-1,3.
-Mixed with pentadiol monoisobutyrate and homogeneously kneaded with three rollers.

【0035】本発明のセラミック基板の製法は、まず、
図6(a)に示すように、支持基板35上に、上述の導
電性ペーストを塗布し、表面電極3となる導体層36を
形成し、この後、上述したスリップ材をドクターブレー
ド法によって塗布・乾燥して、絶縁層1aを形成する絶
縁層成形体41aを形成する。ここで、支持基板35と
してはマイラーフイルムを用い、焼成工程前に取り外さ
れる。
The manufacturing method of the ceramic substrate of the present invention is as follows.
As shown in FIG. 6A, the above-mentioned conductive paste is applied onto the support substrate 35 to form the conductor layer 36 which becomes the surface electrode 3, and then the above-mentioned slip material is applied by the doctor blade method. -Drying forms the insulating layer molded body 41a which forms the insulating layer 1a. Here, a Mylar film is used as the support substrate 35 and is removed before the firing step.

【0036】次に、絶縁層成形体41aに、図6(b)
に示すように、柱状導体9を形成するため、及びビアホ
ール導体24を形成するための貫通孔43a、45aの
形成を行う。柱状導体9を形成するための貫通孔43a
は、図7(a)に示すように、断面円形状の貫通孔43
aが、分割溝17を跨ぐように、環状に所定間隔をおい
て複数形成されている。後述する打抜孔27を破線で示
す。また、分割溝17は、この絶縁層成形体41a上に
は形成されないが、便宜上記載した。尚、柱状導体9を
形成するための貫通孔43aは、図7(b)に示すよう
に、断面が楕円形状の打抜孔27に沿って形成しても良
い。
Next, as shown in FIG. 6B, the insulating layer molded body 41a is formed.
As shown in FIG. 3, through holes 43a and 45a for forming the columnar conductor 9 and for forming the via hole conductor 24 are formed. Through hole 43a for forming the columnar conductor 9
Is a through hole 43 having a circular cross section, as shown in FIG.
A plurality of “a” are formed in a ring shape at predetermined intervals so as to straddle the dividing groove 17. A punching hole 27 described later is shown by a broken line. The dividing groove 17 is not formed on the insulating layer molded body 41a, but is described for convenience. The through hole 43a for forming the columnar conductor 9 may be formed along the punched hole 27 having an elliptical cross section, as shown in FIG. 7B.

【0037】貫通孔43a、45aの形成は、露光処
理、現像処理、洗浄・乾燥処理により行う。露光処理
は、絶縁層成形体41a上に、貫通孔43a、45aが
形成される領域が遮光されるようなフォトターゲットを
載置して、例えば、超高圧水銀灯(10mW/cm2
を光源として用いて露光を行なう。
The through holes 43a and 45a are formed by exposure processing, development processing, and cleaning / drying processing. The exposure process is performed by placing a photo target on the insulating layer molded body 41a such that the regions where the through holes 43a and 45a are formed are shielded from light, and, for example, an ultra-high pressure mercury lamp (10 mW / cm 2 ).
Is used as a light source to perform exposure.

【0038】これにより、貫通孔43a、45aが形成
される領域の絶縁層成形体41aにおいては、光硬化可
能なモノマの光重合反応がおこらず、貫通孔43a、4
5aが形成される領域以外の絶縁層成形体41aにおい
ては、光重合反応が起こる。ここで光重合反応が起こっ
た部位を不溶化部といい、光重合反応が起こらない部位
を溶化部という。
As a result, in the insulating layer molded body 41a in the regions where the through holes 43a and 45a are formed, the photopolymerization reaction of the photocurable monomer does not occur, and the through holes 43a and 4a are formed.
In the insulating layer molded body 41a other than the region where 5a is formed, a photopolymerization reaction occurs. The portion where the photopolymerization reaction has occurred is called the insolubilized portion, and the portion where the photopolymerization reaction does not occur is called the solubilized portion.

【0039】現像処理は、絶縁層成形体41aの溶化部
を現像液で除去するもので、具体的には、例えば、トリ
エタノールアミン水溶液を現像液として用いてスプレー
現像を行う。この現像処理により、絶縁層成形体41a
に貫通孔43a、45aを形成することができる。
The developing treatment is to remove the solubilized portion of the insulating layer molded body 41a with a developing solution. Specifically, for example, spray developing is carried out using an aqueous solution of triethanolamine as a developing solution. By this development processing, the insulating layer molded body 41a
Through holes 43a and 45a can be formed in the.

【0040】次に、貫通孔43a、45aへ導電性ペー
ストを充填し、乾燥して、ビアホール導体24、柱状導
体9となる導電部材47a、49aを形成する。具体的
には、図6(c)に示すように、上述の工程で形成した
貫通孔43a、45a内に上述の導電性ペーストを充填
し、乾燥する。貫通孔43a、45aに相当する部位の
みに印刷可能なスクリーンを用いて印刷によって導体部
材47a、49aを形成し、その後、80℃で10分乾
燥する。
Next, the through holes 43a and 45a are filled with a conductive paste and dried to form the via hole conductors 24 and the conductive members 47a and 49a to be the columnar conductors 9. Specifically, as shown in FIG. 6C, the above-mentioned conductive paste is filled in the through holes 43a and 45a formed in the above-described process and dried. Conductive members 47a and 49a are formed by printing using a screen that can be printed only on the portions corresponding to the through holes 43a and 45a, and then dried at 80 ° C. for 10 minutes.

【0041】次に、ビアホール導体24、柱状導体9と
なる導電部材47a、49aが形成された絶縁層成形体
41aの上面に、上記と同様にして絶縁層成形体41b
を形成し、これに柱状導体9を形成するため、及びビア
ホール導体24を形成するための貫通孔43b、45b
を、上記と同様にして形成する。
Next, the insulating layer molded body 41b is formed on the upper surface of the insulating layer molded body 41a on which the via-hole conductor 24 and the conductive members 47a and 49a to be the columnar conductors 9 are formed in the same manner as described above.
Through holes 43b, 45b for forming columnar conductors 9 therein and for forming via hole conductors 24
Are formed in the same manner as described above.

【0042】絶縁層成形体41bに柱状導体9を形成す
るための貫通孔43は、図7に破線で示すように、下層
の絶縁層成形体41bに形成された柱状導体9用の導電
部材と一部重畳するように形成される。この後、貫通孔
43b、45b内に導電性ペーストを充填し、導電部材
を形成する。
The through hole 43 for forming the columnar conductor 9 in the insulating layer molded body 41b is provided with a conductive member for the columnar conductor 9 formed in the lower insulating layer molded body 41b as shown by a broken line in FIG. It is formed so as to partially overlap. After that, the conductive paste is filled in the through holes 43b and 45b to form a conductive member.

【0043】上記のような工程を繰り返して、絶縁層成
形体41a〜41gが形成された積層体を作製する。こ
の後、スリップ材をドクターブレード法によって塗布・
乾燥して、絶縁基体1の最表面の絶縁層成形体41hを
形成する。
By repeating the above steps, a laminate having the insulating layer molded bodies 41a to 41g formed thereon is produced. After this, apply the slip material by the doctor blade method.
By drying, the outermost surface insulating layer molded body 41h of the insulating substrate 1 is formed.

【0044】この絶縁層成形体41hに上記した露光処
理を施し、導電性ペーストを塗布して表面電極を形成す
る。
The insulating layer molded body 41h is subjected to the above-mentioned exposure treatment and a conductive paste is applied to form a surface electrode.

【0045】このようにして作製された積層成形体を、
必要に応じて、プレスで形状を整え、図6(e)に示す
ような成形体が得られる。この後、支持基板35が除去
される。
The laminated molded body thus produced is
If necessary, the shape is adjusted by a press to obtain a molded body as shown in FIG. 6 (e). After that, the support substrate 35 is removed.

【0046】次に、打抜孔27の形成を行なう。方法と
しては金型による打ち抜き方法等が好ましいが、ドリル
による工法等でも実用可能である。この打抜孔27は、
その切断面が、図7(a)に破線で示したように、端面
電極部の柱状導体9を分割する位置に形成される。これ
により、打抜孔27の表面には、柱状導体9の一部が露
出し、この露出部分から内部に向けて次第に幅が広がる
幅広部10が形成されている。幅広部10は、断面が円
形の柱状導体9及び打抜孔27の場合には、柱状導体9
の中心が残存するように打ち抜くことにより形成され
る。
Next, punching holes 27 are formed. As a method, a punching method with a die is preferable, but a method using a drill is also practical. This punching hole 27 is
The cut surface is formed at the position where the columnar conductor 9 of the end face electrode portion is divided, as shown by the broken line in FIG. As a result, a part of the columnar conductor 9 is exposed on the surface of the punched hole 27, and a wide portion 10 whose width gradually increases from the exposed portion toward the inside is formed. In the case of the columnar conductor 9 having a circular cross section and the punched hole 27, the wide portion 10 has the columnar conductor 9
It is formed by punching so that the center of the remains.

【0047】即ち、円形状に所定間隔をおいて形成され
た柱状導体9の内側に、かつそれぞれの柱状導体9の中
心よりも内側となる位置に形成される。言い換えれば、
打抜孔27により打ち抜かれる部分の面積が残部よりも
少なくなるような打抜孔27の寸法とされている。
That is, they are formed inside the columnar conductors 9 formed at predetermined intervals in a circular shape and at a position inside the center of each columnar conductor 9. In other words,
The size of the punching hole 27 is set so that the area of the portion punched by the punching hole 27 is smaller than that of the remaining portion.

【0048】次に、打抜孔27に吸引等の技術を用い、
導電性ペーストを内壁面にコーティングする。
Next, a technique such as suction is used for the punching hole 27,
The inner wall surface is coated with a conductive paste.

【0049】この後、積層成形体の両面から、回路ブロ
ックに分割するための分割溝17を形成する。分割溝1
7は、打抜孔27を2分割するような位置に、鋭利な刃
物を押し当てることより形成する。
Thereafter, dividing grooves 17 for dividing into circuit blocks are formed on both sides of the laminated molded body. Dividing groove 1
7 is formed by pressing a sharp blade at a position where the punched hole 27 is divided into two.

【0050】最後に焼成を行なう。焼成工程は脱バイン
ダ過程と焼成過程からなり、脱バインダ過程(〜600
℃)で絶縁層成形体、配線層パターン、端面電極及びビ
アホール導体の導電部材の有機成分を消失する。その
後、所定雰囲気、所定温度で絶縁層となる絶縁層成形体
および配線層パターン,端面電極,ビアホール導体、柱
状導体となる導電部材を一括的に焼成する。
Finally, firing is performed. The firing process consists of a binder removal process and a firing process.
(.Degree. C.), the organic components of the insulating layer molded body, the wiring layer pattern, the end face electrodes, and the conductive members of the via-hole conductor disappear. After that, the insulating layer molded body and the wiring layer pattern, the end surface electrodes, the via hole conductors, and the columnar conductors, which become the insulating layer, are collectively fired in a predetermined atmosphere and at a predetermined temperature.

【0051】その後、表面処理として、さらに、厚膜抵
抗膜や厚膜保護膜の印刷・焼きつけ、メッキ処理、さら
にICチップを含むチップ部品4、6の接合を行う。
After that, as the surface treatment, printing / baking of a thick film resistance film or a thick film protective film, plating treatment, and joining of chip components 4 and 6 including an IC chip are further performed.

【0052】尚、表面電極3は、絶縁層1a〜1hの焼
成された積層体の表面に、印刷・乾燥し、所定雰囲気で
焼きつけを行っても良い。例えば、配線層23にAg系
導体を用い、表面電極3としてCu系導体を用いる場
合、絶縁層21a〜21hと配線層23の導体膜からな
る積層体を、酸化性雰囲気又は中性雰囲気で焼成し、焼
成された積層体の表面に、Cu系導体の印刷・乾燥を行
い、中性雰囲気又は還元性雰囲気・780℃(AgとC
uの共晶点)以下の温度で焼成する。
The surface electrode 3 may be printed and dried on the surface of the fired laminate of the insulating layers 1a to 1h and baked in a predetermined atmosphere. For example, when an Ag-based conductor is used for the wiring layer 23 and a Cu-based conductor is used for the surface electrode 3, a laminate including the insulating layers 21a to 21h and the conductor film of the wiring layer 23 is fired in an oxidizing atmosphere or a neutral atmosphere. Then, a Cu-based conductor is printed and dried on the surface of the fired laminated body, and a neutral atmosphere or a reducing atmosphere at 780 ° C. (Ag and C
firing at a temperature equal to or lower than the (eutectic point of u).

【0053】尚、上記態様では、スリップを支持基板上
に塗布乾燥して絶縁層成形体を積層する方法で形成し、
貫通孔を露光現像で形成したが、誘電体グリーンシート
を形成し、このグリーンシートに貫通孔を金型のパンチ
ングにより形成し、これに導電性ペーストを充填し、こ
の導電性ペーストが充填されたグリーンシートを積層す
る、いわゆるグリーンシート積層方式にて、セラミック
基板を作製しても良いことは勿論である。
In the above embodiment, the slip is applied on the supporting substrate and dried to form the insulating layer molded body,
Although the through holes were formed by exposure and development, a dielectric green sheet was formed, the through holes were formed in this green sheet by punching of a mold, and this was filled with a conductive paste, and this conductive paste was filled. Needless to say, the ceramic substrate may be manufactured by a so-called green sheet laminating method in which green sheets are laminated.

【0054】[0054]

【発明の効果】本発明のセラミック基板は、各絶縁層の
厚み方向に、打抜孔内に一部露出する柱状導体を打抜孔
に沿って所定間隔をおいて複数形成するとともに、隣接
する上下の絶縁層の柱状導体が、絶縁基体の上方から見
て一部重畳し、該柱状導体の重畳部分が打抜孔内に露出
しているため、打ち抜き時に絶縁層に作用する余分なス
トレスや、変形が殆ど発生せず、配線層が崩れ、配線層
と端面電極との接続信頼性を向上できる。
According to the ceramic substrate of the present invention, a plurality of columnar conductors partially exposed in the punching hole are formed along the punching hole at predetermined intervals in the thickness direction of each insulating layer, and adjacent columnar conductors are formed. Since the columnar conductors of the insulating layer partially overlap with each other when viewed from above the insulating substrate, and the overlapping portions of the columnar conductors are exposed in the punching holes, extra stress or deformation acting on the insulating layer during punching is prevented. Almost no occurrence occurs, the wiring layer collapses, and the connection reliability between the wiring layer and the end face electrode can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の分割回路基板を示す斜視図である。FIG. 1 is a perspective view showing a divided circuit board of the present invention.

【図2】図1の端面電極部分を金属層を除去して示す斜
視図である。
2 is a perspective view showing an end face electrode portion of FIG. 1 with a metal layer removed. FIG.

【図3】本発明のセラミック基板を示す斜視図である。FIG. 3 is a perspective view showing a ceramic substrate of the present invention.

【図4】図3の一部を拡大して示す断面図である。FIG. 4 is a sectional view showing a part of FIG. 3 in an enlarged manner.

【図5】本発明のセラミック基板の打抜孔及びその近傍
を示す図である。
FIG. 5 is a view showing a punching hole of the ceramic substrate of the present invention and the vicinity thereof.

【図6】本発明のセラミック基板の製法を示す工程図で
ある。
FIG. 6 is a process chart showing a method for producing a ceramic substrate of the present invention.

【図7】絶縁層成形体に柱状導体を形成するための貫通
孔を示す平面図である。
FIG. 7 is a plan view showing a through hole for forming a columnar conductor in an insulating layer molded body.

【符号の説明】[Explanation of symbols]

1・・・分割絶縁基体 1a〜1h、21a〜21h・・・絶縁層 2・・・端面電極 7・・・凹部 8・・・金属層 9・・・柱状導体 10・・・幅広部 11・・・重畳部分 17・・・分割溝 21・・・絶縁基体 23・・・配線層 24・・・ビアホール導体 27・・・打抜孔 1-divided insulating substrate 1a to 1h, 21a to 21h ... Insulating layer 2 ... Edge electrode 7 ... Recess 8 ... Metal layer 9 ... Column conductor 10 ... Wide part 11 ... Superposed part 17 ... Dividing groove 21 ... Insulating substrate 23 ... Wiring layer 24 ... Via hole conductor 27 ... Punch hole

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 1/11 H05K 3/40 D 3/00 H01L 23/12 C 3/40 L Fターム(参考) 5E317 AA22 AA26 BB04 BB12 BB14 CC22 CC25 CD21 CD31 CD32 GG11 5E338 AA03 AA18 BB02 BB13 BB25 BB47 BB48 BB65 BB75 CC01 CC04 CC06 CD01 CD33 EE11 EE26 EE33 5E346 AA15 AA38 AA42 AA43 AA60 BB01 BB13 BB16 CC18 CC32 CC39 DD02 DD34 EE23 EE24 FF18 FF42 GG05 GG08 HH07 HH33 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H05K 1/11 H05K 3/40 D 3/00 H01L 23/12 C 3/40 LF term (reference) 5E317 AA22 AA26 BB04 BB12 BB14 CC22 CC25 CD21 CD31 CD32. HH33

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】セラミックスからなる絶縁層を複数積層し
てなる絶縁基体と、前記絶縁層間に形成された配線層
と、該配線層に接続されるビアホール導体と、前記絶縁
基体表面に形成された分割溝と、前記絶縁基体の厚み方
向に形成され、かつ前記分割溝の延長線上に形成された
打抜孔とを有し、前記分割溝で前記絶縁基体を分割した
際にそれぞれが複数の端面電極を有する分割回路基板と
なるセラミック基板であって、前記各絶縁層の厚み方向
に、前記打抜孔内に一部露出する柱状導体を前記打抜孔
に沿って所定間隔をおいて複数形成するとともに、隣接
する上下の前記絶縁層の柱状導体が、前記絶縁基体の上
方から見て一部重畳し、該柱状導体の重畳部分が前記打
抜孔内に露出していることを特徴とするセラミック基
板。
1. An insulating base formed by laminating a plurality of insulating layers made of ceramics, a wiring layer formed between the insulating layers, a via-hole conductor connected to the wiring layer, and a surface formed on the insulating base. It has a dividing groove and a punching hole formed in the thickness direction of the insulating substrate and formed on an extension line of the dividing groove, each of which has a plurality of end face electrodes when the insulating substrate is divided by the dividing groove. A ceramic substrate to be a divided circuit board having, in the thickness direction of each insulating layer, a plurality of columnar conductors partially exposed in the punched hole are formed at predetermined intervals along the punched hole, A ceramic substrate, wherein the columnar conductors of the adjacent upper and lower insulating layers partially overlap each other when viewed from above the insulating substrate, and the overlapping portions of the columnar conductors are exposed in the punched holes.
【請求項2】絶縁層の柱状導体は、打抜孔内への露出部
分から前記絶縁層内部に向けて次第に幅が大きくなる幅
広部を有することを特徴とする請求項1記載のセラミッ
ク基板。
2. The ceramic substrate according to claim 1, wherein the columnar conductor of the insulating layer has a wide portion whose width gradually increases from an exposed portion inside the punched hole toward the inside of the insulating layer.
【請求項3】絶縁層の柱状導体は、絶縁基体の上方から
見て分割溝を除いて形成されていることを特徴とする請
求項1又は2記載のセラミック基板。
3. The ceramic substrate according to claim 1, wherein the columnar conductor of the insulating layer is formed by removing the dividing groove when viewed from above the insulating substrate.
【請求項4】セラミックスからなる絶縁層を複数積層し
てなる分割絶縁基体の外周面に、かつ厚み方向に形成さ
れた凹部に、該凹部に端面電極を形成してなる分割回路
基板であって、前記端面電極が、前記各絶縁層の厚み方
向に、前記凹部に一部露出する柱状導体を前記凹部に沿
って所定間隔をおいて複数形成してなるとともに、隣接
する上下の前記絶縁層の柱状導体が、前記分割絶縁基体
の上方から見て一部重畳し、該柱状導体の重畳部分が前
記凹部に露出していることを特徴とする分割回路基板。
4. A divided circuit board in which an end face electrode is formed in a concave portion formed on the outer peripheral surface of a divided insulating substrate formed by laminating a plurality of ceramic insulating layers and in the thickness direction. The end surface electrode is formed by forming a plurality of columnar conductors partially exposed in the recess along the recess at predetermined intervals in the thickness direction of each of the insulating layers. A divided circuit board, wherein the columnar conductors partially overlap each other when viewed from above the divided insulating substrate, and the overlapped portions of the columnar conductors are exposed in the recesses.
【請求項5】分割絶縁基体の凹部に金属層が形成されて
いることを特徴とする請求項4記載の分割回路基板。
5. The divided circuit board according to claim 4, wherein a metal layer is formed in the recess of the divided insulating substrate.
JP2001294744A 2001-09-26 2001-09-26 Ceramic substrate and divided circuit board Pending JP2003101225A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001294744A JP2003101225A (en) 2001-09-26 2001-09-26 Ceramic substrate and divided circuit board

Publications (1)

Publication Number Publication Date
JP2003101225A true JP2003101225A (en) 2003-04-04

Family

ID=19116296

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2003101225A (en)

Cited By (12)

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JP2003218262A (en) * 2002-01-21 2003-07-31 Kyocera Corp Wiring board
JP2003249590A (en) * 2002-02-25 2003-09-05 Kyocera Corp Wiring board
JP2007013186A (en) * 2005-07-01 2007-01-18 Kofukin Seimitsu Kogyo (Shenzhen) Yugenkoshi Printed circuit board assembly
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JP2009200404A (en) * 2008-02-25 2009-09-03 Alps Electric Co Ltd Method of manufacturing ceramic wiring board
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JP2007013186A (en) * 2005-07-01 2007-01-18 Kofukin Seimitsu Kogyo (Shenzhen) Yugenkoshi Printed circuit board assembly
JP2008098578A (en) * 2006-10-16 2008-04-24 Kyocera Corp Wiring component and method for manufacturing the same
JP2008294246A (en) * 2007-05-25 2008-12-04 Koa Corp End electrode forming method of low-temperature baked ceramic multilayer substrate
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US8450615B2 (en) 2007-08-29 2013-05-28 Murata Manufacturing Co., Ltd. Ceramic multilayer substrate
JP2009200404A (en) * 2008-02-25 2009-09-03 Alps Electric Co Ltd Method of manufacturing ceramic wiring board
WO2009110286A1 (en) * 2008-03-07 2009-09-11 株式会社村田製作所 Electronic component and method for manufacturing the same
JP4784689B2 (en) * 2008-03-07 2011-10-05 株式会社村田製作所 Electronic component and manufacturing method thereof
JP2009231479A (en) * 2008-03-21 2009-10-08 Alps Electric Co Ltd Ceramic multilayer wiring board and manufacturing method thereof
JP4712065B2 (en) * 2008-04-14 2011-06-29 京セラ株式会社 Multi-cavity wiring board, wiring board, and multi-cavity wiring board and method of manufacturing wiring board
JP2008187198A (en) * 2008-04-14 2008-08-14 Kyocera Corp Multi-piece wiring substrate and wiring substrate, and manufacturing method therefor
CN104168712A (en) * 2014-08-20 2014-11-26 广东生益科技股份有限公司 Trough type metalized half hole and manufacturing method thereof
JP2017174943A (en) * 2016-03-23 2017-09-28 京セラ株式会社 Wiring board, electronic device, and electronic module

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