JP2008294246A - End electrode forming method of low-temperature baked ceramic multilayer substrate - Google Patents

End electrode forming method of low-temperature baked ceramic multilayer substrate Download PDF

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JP2008294246A
JP2008294246A JP2007138549A JP2007138549A JP2008294246A JP 2008294246 A JP2008294246 A JP 2008294246A JP 2007138549 A JP2007138549 A JP 2007138549A JP 2007138549 A JP2007138549 A JP 2007138549A JP 2008294246 A JP2008294246 A JP 2008294246A
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conductor layer
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Isao Touchi
功 登内
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Koa Corp
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Koa Corp
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<P>PROBLEM TO BE SOLVED: To provide an end electrode forming method of a highly reliable LTCC substrate which can prevent occurrence of a crack in a castellation conductor layer even if the LTCC substrate is used as a ceramic multilayer substrate. <P>SOLUTION: A low temperature baked ceramic green sheet 11 is generated and a through hole 13 is formed so that it straddles a splitting line 12. The through hole 13 is filled with conductor paste and a conductor layer 14 is formed. The conductor layer with which the through hole is filled is opened by using a first pin or a metallic mold whose diameter is smaller than width of the through hole, and an opening part 15 is formed. Small holes 15a and 15b are formed on the splitting lines 12 at both ends in a longitudinal direction of the through hole by using a second pin whose size is equal to the first pin or is larger than it. The castellation conductor layers 14a and 14b are formed and they are laminated and press-fitted so as to form a ceramic green block. It is baked and is cut along the splitting lines 12. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、低温焼成セラミックス(LTCC)グリーンシートを複数層積層および圧着してセラミックスグリーンブロックを形成し、800−1000℃程度の比較的低温で焼成し、その後個片基板に切断して形成する低温焼成セラミックス多層基板(LTCC基板)に係り、特にその端面電極の形成方法に関する。   In the present invention, a ceramic green block is formed by laminating and pressing a plurality of layers of low-temperature fired ceramic (LTCC) green sheets, and fired at a relatively low temperature of about 800-1000 ° C., and then cut into individual substrates. The present invention relates to a low-temperature fired ceramic multilayer substrate (LTCC substrate), and more particularly to a method for forming an end face electrode thereof.

従来から、セラミックス多層基板の端面電極として、端面に凹部(キャスタレーション)を設け、該凹部に内部電極と接続するキャスタレーション導体層(電極)を設けることが知られている(特許文献1)。係るキャスタレーション導体層は、セラミックスグリーンシートを複数層積層および圧着してセラミックスグリーンブロックを形成し、多数個取り基板の分割線に沿ってスルーホールを形成し、このスルーホール内周面全面に吸引法で導体ペーストを印刷すると共に、入出力ランドパターンを印刷して形成している。すなわち、このキャスタレーション導体層は、セラミックスグリーンボックスを吸着板上にセットすると共に、スクリーンマスクをセットし、吸着板に形成された吸引口からスルーホール内に空気吸引力を作用させながらスクリーンマスク上の導体ペーストをスルーホール内周面に塗布して形成することが記載されている(上記文献0003欄)。
特開2001−77507号公報
Conventionally, as an end face electrode of a ceramic multilayer substrate, it is known that a recess (castellation) is provided on the end face, and a castellation conductor layer (electrode) connected to the internal electrode is provided in the recess (Patent Document 1). The castoration conductor layer is formed by laminating and pressing multiple layers of ceramic green sheets to form a ceramic green block, forming through holes along the dividing line of the multi-chip substrate, and sucking the entire inner surface of the through hole. The conductor paste is printed by this method, and the input / output land pattern is printed. That is, this castellation conductor layer has a ceramic green box set on the suction plate and a screen mask set on the screen mask while applying an air suction force from the suction port formed on the suction plate into the through hole. Is applied to the inner peripheral surface of the through-hole (see column 0003 above).
JP 2001-77507 A

しかしながら、セラミックス多層基板として焼成を低温で行える低温焼成セラミックス(LTCC)基板を用いる場合には、キャスタレーション導体層(Ag)と、LTCC基板とは、その熱膨張係数が大きく異なり、その熱膨張係数の差から、キャスタレーション導体層にクラックが進行し、そのクラックにより導電機構が破断され、その結果オープン不良となる恐れがあるという問題がある。   However, when a low-temperature fired ceramic (LTCC) substrate that can be fired at a low temperature is used as the ceramic multilayer substrate, the thermal expansion coefficient differs greatly between the castellation conductor layer (Ag) and the LTCC substrate. Therefore, there is a problem that a crack progresses in the castellation conductor layer, and the conductive mechanism is broken by the crack, resulting in an open failure.

本発明は上述した事情に基づいてなされたもので、セラミックス多層基板としてLTCC基板を用いた場合にも、キャスタレーション導体層(Ag)にその熱膨張係数の差から、クラックが発生することを防止することができる、信頼性の高いLTCC基板の端面電極形成方法を提供することを目的とする。   The present invention has been made based on the above-mentioned circumstances, and even when an LTCC substrate is used as the ceramic multilayer substrate, cracks are prevented from occurring in the castellation conductor layer (Ag) due to the difference in thermal expansion coefficient. An object of the present invention is to provide a highly reliable method of forming an end face electrode of an LTCC substrate.

本発明のLTCC基板の端面電極形成方法は、低温焼成セラミックスグリーンシートを作成し、前記グリーンシートを多数の個片基板に切断する分割線に跨るようにスルーホールを形成し、前記スルーホールに導体ペーストを充填して導体層を形成し、前記スルーホールの幅よりも小径の第1のピンまたは金型を用いて前記スルーホールに充填した導体層を開口して、開口部を形成し、前記スルーホールの長手方向両端部の前記分割線上に前記ピンと同等もしくはそれ以上のサイズの第2のピンを用いて、小穴を形成し、前記スルーホールの側縁部にキャスタレーション導体層を形成し、前記グリーンシートを複数層積層および圧着してセラミックスグリーンブロックを形成し、焼成し、前記分割線に沿って切断することを特徴とする。   In the method for forming an end face electrode of an LTCC substrate of the present invention, a low-temperature fired ceramic green sheet is prepared, a through hole is formed so as to straddle a dividing line for cutting the green sheet into a number of individual substrates, and a conductor is formed in the through hole. Filling the paste to form a conductor layer, opening the conductor layer filled in the through hole using a first pin or mold having a diameter smaller than the width of the through hole, forming an opening, Using a second pin having a size equal to or larger than the pin on the dividing line at both longitudinal ends of the through hole, a small hole is formed, and a castellation conductor layer is formed on a side edge of the through hole, A plurality of green sheets are laminated and pressed to form a ceramic green block, fired, and cut along the dividing line.

本発明によれば、前記の構成で、LTCC基板の端面電極を形成するので、完成段階のLTCC基板の温度サイクル試験等において、LTCC基板とキャスタレーション導体層(Ag)との熱膨張係数の差から発生する応力を前記小穴部分に逃がすことができ、これによりキャスタレーション導体層にクラックが発生することを防止でき、クラックにより導電機構が破断されるという問題を解決することができる。   According to the present invention, since the end face electrode of the LTCC substrate is formed with the above-described configuration, the difference in thermal expansion coefficient between the LTCC substrate and the castellation conductor layer (Ag) in the temperature cycle test of the LTCC substrate at the completion stage or the like. Can be released to the small hole portion, thereby preventing the castellation conductor layer from being cracked, and the problem that the conductive mechanism is broken by the crack can be solved.

さらに、前記キャスタレーション導体層の中間部に、前記第1のピンと同等もしくはそれ以上のサイズの第2のピンを用いて小穴をさらに形成することで、LTCC基板とキャスタレーション導体層との熱膨張係数の差から発生する応力の分散効果をより高めることができ、より信頼性の高いLTCC基板の端面電極を形成することができる。   Further, a small hole is further formed in the middle portion of the castellation conductor layer using a second pin having a size equal to or larger than that of the first pin, whereby thermal expansion between the LTCC substrate and the castellation conductor layer is achieved. The effect of dispersing the stress generated from the difference in coefficients can be further increased, and a more reliable end face electrode of the LTCC substrate can be formed.

以下、本発明の一実施形態について、添付図面を参照して説明する。図1は、本発明の低温焼成セラミックス多層基板の端面電極形成方法を工程順に示す。   Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows a method for forming an end face electrode of a low-temperature fired ceramic multilayer substrate according to the present invention in the order of steps.

まず、アルミナとガラス材料等からなる低温焼成が可能なセラミックス粉末に、樹脂、可塑剤、分散剤などを加えたスラリーを用いてドクターブレード等の方法でセラミックスグリーンシートを作成し、適当な大きさのグリーンシート11に切り出す。このグリーンシート11は多数個取りのシートであり、分割線12により最終的に多数の個片基板に切断される((a)参照)。   First, a ceramic green sheet is prepared by a method such as a doctor blade using a slurry in which resin, plasticizer, dispersant, etc. are added to ceramic powder made of alumina and glass material that can be fired at low temperature. The green sheet 11 is cut out. The green sheet 11 is a multi-piece sheet, and is finally cut into a large number of individual substrates by dividing lines 12 (see (a)).

次に、打ち抜き型やパンチングマシンを使用して分割線12に跨るようにスルーホール13を形成する((b)参照)。そして、スルーホール13にAgペーストをメタルマスク等を用いて充填し、乾燥して導体層14を形成する((c)参照)。そして、スルーホールの幅よりも小径の第1のピンを用いてスルーホール13に充填した導体層14を連続的にパンチングして、開口部15を形成する((d)参照)。この実施形態では、スルーホールの幅0.4mm程度に対し直径0.3mm程度のピンを用いて、導体層を開口して開口部15を形成することが好ましい。   Next, a through hole 13 is formed so as to straddle the dividing line 12 using a punching die or a punching machine (see (b)). Then, the through hole 13 is filled with Ag paste using a metal mask or the like and dried to form the conductor layer 14 (see (c)). Then, the conductor layer 14 filled in the through hole 13 is continuously punched by using the first pin having a diameter smaller than the width of the through hole to form the opening 15 (see (d)). In this embodiment, it is preferable to form the opening 15 by opening the conductor layer using a pin having a diameter of about 0.3 mm with respect to the width of the through hole of about 0.4 mm.

次に、スルーホール13の長手方向両端部の分割線12上に第1のピンと同等もしくはそれ以上のサイズの第2のピンを用いて、小穴15a,15bを形成し、スルーホール13の側縁部にキャスタレーション導体層14a,14bを形成する((e)参照)。さらに、キャスタレーション導体層14a,14bの中間部分に、導体層14の開口の形成に用いた第1のピンと同等もしくはそれ以上のサイズの第2のピンを用いて小穴15c、15dを形成する。これにより、スルーホール13内の分割線12の両側のキャスタレーション導体層14a,14bをそれぞれその中間で絶縁分離し、キャスタレーション導体層14c,14d,14e,14fを形成する((f)参照)。   Next, small holes 15 a and 15 b are formed on the dividing line 12 at both ends in the longitudinal direction of the through hole 13 using a second pin having a size equal to or larger than the first pin, and the side edges of the through hole 13 are formed. Castoration conductor layers 14a and 14b are formed in the portion (see (e)). Further, small holes 15c and 15d are formed in the middle portion of the castellation conductor layers 14a and 14b using a second pin having a size equal to or larger than the first pin used for forming the opening of the conductor layer 14. Thus, the castellation conductor layers 14a and 14b on both sides of the dividing line 12 in the through hole 13 are insulated and separated in the middle thereof to form castellation conductor layers 14c, 14d, 14e, and 14f (see (f)). .

その後、スクリーン印刷等の方法で内部電極パターンを形成する。そして、上記手順により製作した複数層のグリーンシートを積層し、一軸プレスや静水圧プレスなどにより圧着してセラミックスグリーンブロックを形成する。そして、分割線12に沿ってハーフカットを形成し、800〜1000℃の範囲で焼成する。さらに、必要に応じてメッキ処理、分割処理等を行い、内部回路配線パターンを備えたLTCC基板が完成する。そして、必要に応じて表層には各種電子部品が搭載される。   Thereafter, an internal electrode pattern is formed by a method such as screen printing. Then, a plurality of green sheets produced by the above procedure are stacked and pressed by a uniaxial press or an isostatic press to form a ceramic green block. And a half cut is formed along the parting line 12, and it bakes in the range of 800-1000 degreeC. Furthermore, if necessary, a plating process, a dividing process, etc. are performed to complete an LTCC substrate having an internal circuit wiring pattern. Various electronic components are mounted on the surface layer as necessary.

図2は、本発明のLTCC基板の端面電極部分の詳細構造例を示す。一例として、キャスタレーション導体層間の間隔Aは0.3mm程度であり、キャスタレーション(凹部)間の間隔Bは0.4mm程度である。従って、キャスタレーション導体層の厚みは0.05mm程度である。これに対して、小穴15a,15b,15c,15dの直径C,Dは、スルーホール13に充填した導体層14を連続的にパンチングして開口し、開口部15を形成する第1のピンと同等もしくはそれ以上のサイズの第2のピンを用いて形成したものであり、キャスタレーション導体間の間隔Aと同等かもしくはそれ以上のサイズとなっている。   FIG. 2 shows a detailed structure example of the end face electrode portion of the LTCC substrate of the present invention. As an example, the distance A between the castellation conductor layers is about 0.3 mm, and the distance B between the castellations (recesses) is about 0.4 mm. Therefore, the thickness of the castellation conductor layer is about 0.05 mm. On the other hand, the diameters C and D of the small holes 15a, 15b, 15c, and 15d are equivalent to the first pin that forms the opening 15 by continuously punching and opening the conductor layer 14 filled in the through hole 13. Alternatively, it is formed using a second pin having a size larger than that, and the size is equal to or larger than the distance A between the castellation conductors.

上記構造例のシミュレーション結果では、LTCC基板の熱膨張係数を5.5×10−6/K、キャスタレーション導体層(Ag)の熱膨張係数を19.6×10−6/Kとすると、キャスタレーション導体層(Ag)にかかる熱応力は170〜220MPa程度となる。 In the simulation result of the above structural example, when the thermal expansion coefficient of the LTCC substrate is 5.5 × 10 −6 / K and the thermal expansion coefficient of the castellation conductor layer (Ag) is 19.6 × 10 −6 / K, the caster The thermal stress applied to the insulation conductor layer (Ag) is about 170 to 220 MPa.

ところで、通常のアルミナ基板からなるHTCC基板では、その主要構成材料の熱膨張係数は、アルミナ7.0×10−6/K、タングステン4.5×10−6/K、モリブデン5.5×10−6/Kであり、LTCC基板のキャスタレーション導体層にかかる熱応力はHTCC基板の場合と比較してはるかに大きいことが分かる。 By the way, in the HTCC board | substrate which consists of a normal alumina board | substrate, the thermal expansion coefficient of the main component material is an alumina 7.0 * 10 < -6 > / K, tungsten 4.5 * 10 < -6 > / K, molybdenum 5.5 * 10. a -6 / K, the thermal stress on the castellation conductor layers of the LTCC substrate is seen much larger compared to the case of the HTCC substrate.

本発明によれば、小穴を少なくともキャスタレーション導体層の両側に2カ所(15a,15b)、好ましくはキャスタレーション導体層の中間にさらに2カ所(15c,15d)を設けることで、LTCC基板とその導体層との間の熱膨張係数の差から生じる応力を各小穴部分に分散させることができ、LTCC基板とその導体層との間にかかる応力を緩和させ、キャスタレーション導体層14c,14d,14e,14fにクラックが発生することを防止することができる。   According to the present invention, there are provided two small holes (15a, 15b) on both sides of the castellation conductor layer (15a, 15b), preferably two (15c, 15d) in the middle of the castellation conductor layer. The stress resulting from the difference in thermal expansion coefficient with the conductor layer can be dispersed in each small hole portion, and the stress applied between the LTCC substrate and the conductor layer can be relaxed, and the castellation conductor layers 14c, 14d, and 14e. , 14f can be prevented from cracking.

従って、このLTCC基板では耐熱性・耐湿性に優れる他、配線導体として低抵抗損失のAgを使用することで、高周波回路において良好な損失特性(周波数特性)が得られるという長所を生かしつつ、端面電極における信頼性を高めることができる。また、本発明では、グリーンシートの各層毎にスルーホールの幅よりも小径の第1のピンを用いてスルーホールに充填した導体層を連続的にパンチングして開口部を形成し、小穴を設けてキャスタレーション導体層を形成し、これを積層および圧着してLTCC基板のキャスタレーション導体層を形成するので、スルーホールの長手方向長さが可変の場合にも同一のピンを用いて効率的にキャスタレーション導体層を形成できる。   Therefore, this LTCC substrate is excellent in heat resistance and moisture resistance, and by using Ag having a low resistance loss as a wiring conductor, while taking advantage of good loss characteristics (frequency characteristics) in a high frequency circuit, the end face Reliability in the electrode can be increased. Further, in the present invention, for each layer of the green sheet, the conductor layer filled in the through hole is continuously punched using the first pin having a diameter smaller than the width of the through hole to form the opening, and the small hole is provided. The caster conductor layer is formed, and the caster conductor layer of the LTCC substrate is formed by laminating and press-bonding the cast conductor layer. Therefore, even when the longitudinal length of the through hole is variable, the same pin can be used efficiently. A castellation conductor layer can be formed.

また、1枚のグリーンシートが50〜200μm程度と比較的薄いので、導体ペーストの印刷でスルーホールを充填し導体層を形成することが可能であり、1枚のグリーンシート毎にキャスタレーション導体層を形成するので、キャスタレーション導体層とLTCC基板との密着性を良好なものとすることができる。また、特許文献1のキャスタレーション導体層の形成に必要とされる吸引装置などを必要とせず、効率的にキャスタレーション導体層を形成できる。   In addition, since one green sheet is relatively thin, about 50 to 200 μm, it is possible to fill a through hole by printing a conductor paste to form a conductor layer, and a castellation conductor layer for each green sheet. Therefore, the adhesion between the castellation conductor layer and the LTCC substrate can be improved. In addition, the castoration conductor layer can be efficiently formed without the need for a suction device or the like required for forming the castellation conductor layer of Patent Document 1.

なお、上記実施形態ではスルーホールに充填した導体層の開口部の形成に小径のピンを用いて連続的にパンチングして形成する例について説明したが、開口部の形成に金型を用いてもよい。   In the above embodiment, an example in which the opening of the conductor layer filled in the through hole is formed by continuously punching using a small-diameter pin has been described, but a mold may be used for forming the opening. Good.

これまで本発明の一実施形態について説明したが、本発明は上述の実施形態に限定されず、その技術的思想の範囲内において種々異なる形態にて実施されてよいことは言うまでもない。   Although one embodiment of the present invention has been described so far, it is needless to say that the present invention is not limited to the above-described embodiment, and may be implemented in various forms within the scope of the technical idea.

本発明の一実施形態の低温焼成セラミックス多層基板の端面電極形成方法の工程順を示す平面図である。It is a top view which shows the process order of the end surface electrode formation method of the low-temperature baking ceramic multilayer substrate of one Embodiment of this invention. 本発明の一実施形態の低温焼成セラミックス多層基板の端面電極の配置を示す平面図である。It is a top view which shows arrangement | positioning of the end surface electrode of the low-temperature baking ceramic multilayer substrate of one Embodiment of this invention.

符号の説明Explanation of symbols

11 グリーンシート
12 分割線
13 スルーホール
14 導体層
15 小穴
11 Green sheet 12 Dividing line 13 Through hole 14 Conductor layer 15 Small hole

Claims (4)

低温焼成セラミックスグリーンシートを作成し、
前記グリーンシートを多数の個片基板に切断する分割線に跨るようにスルーホールを形成し、
前記スルーホールに導体ペーストを充填して導体層を形成し、
前記スルーホールの幅よりも小径の第1のピンまたは金型を用いて前記スルーホールに充填した導体層を開口して、開口部を形成し、
前記スルーホールの長手方向両端部の前記分割線上に前記第1のピンと同等もしくはそれ以上のサイズの第2のピンを用いて、小穴を形成し、前記スルーホールの側縁部にキャスタレーション導体層を形成し、
前記グリーンシートを複数層積層および圧着してセラミックスグリーンブロックを形成し、焼成し、前記分割線に沿って切断することを特徴とする低温焼成セラミックス多層基板の端面電極形成方法。
Create a low-temperature fired ceramic green sheet,
A through hole is formed so as to straddle a dividing line for cutting the green sheet into a large number of individual substrates,
Filling the through hole with a conductor paste to form a conductor layer,
Opening the conductor layer filled in the through hole using a first pin or mold having a smaller diameter than the width of the through hole, forming an opening,
A small hole is formed on the dividing line at both ends in the longitudinal direction of the through hole using a second pin having a size equal to or larger than the first pin, and a castellation conductor layer is formed on a side edge of the through hole. Form the
A method of forming an end face electrode of a low-temperature fired ceramic multilayer substrate, wherein a plurality of green sheets are laminated and pressed to form a ceramic green block, fired, and cut along the dividing line.
前記キャスタレーション導体層の中間部に、前記第1のピンと同等もしくはそれ以上のサイズの第2のピンを用いて小穴をさらに形成することを特徴とする請求項1記載の低温焼成セラミックス多層基板の端面電極形成方法。   2. The low-temperature fired ceramic multilayer substrate according to claim 1, wherein a small hole is further formed in the middle portion of the castellation conductor layer using a second pin having a size equal to or larger than the first pin. End electrode forming method. 前記導体ペーストが銀ペーストであることを特徴とする請求項1記載の低温焼成セラミックス多層基板の端面電極形成方法。   2. The method for forming an end face electrode of a low-temperature fired ceramic multilayer substrate according to claim 1, wherein the conductor paste is a silver paste. 前記スルーホールの幅よりも小径の第1のピンを用いて連続的にパンチングして、前記スルーホールに充填した導体層を開口し、開口部を形成することを特徴とする請求項1記載の低温焼成セラミックス多層基板の端面電極形成方法。
2. An opening is formed by continuously punching using a first pin having a diameter smaller than the width of the through hole to open a conductor layer filled in the through hole. A method for forming an end face electrode of a low-temperature fired ceramic multilayer substrate.
JP2007138549A 2007-05-25 2007-05-25 End electrode forming method of low-temperature baked ceramic multilayer substrate Pending JP2008294246A (en)

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US9265159B2 (en) 2013-04-26 2016-02-16 Fujitsu Limited Stacked structure and manufacturing method of the same

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JP2003101225A (en) * 2001-09-26 2003-04-04 Kyocera Corp Ceramic substrate and divided circuit board
JP2004112751A (en) * 2002-07-26 2004-04-08 Toyo Commun Equip Co Ltd Surface mounted electronic device, insulating substrate base material, insulating substrates, and manufacturing method thereof
JP2007095927A (en) * 2005-09-28 2007-04-12 Koa Corp Wiring board and its production method

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Publication number Priority date Publication date Assignee Title
JP2003101225A (en) * 2001-09-26 2003-04-04 Kyocera Corp Ceramic substrate and divided circuit board
JP2004112751A (en) * 2002-07-26 2004-04-08 Toyo Commun Equip Co Ltd Surface mounted electronic device, insulating substrate base material, insulating substrates, and manufacturing method thereof
JP2007095927A (en) * 2005-09-28 2007-04-12 Koa Corp Wiring board and its production method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9265159B2 (en) 2013-04-26 2016-02-16 Fujitsu Limited Stacked structure and manufacturing method of the same

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