JP2006147913A - Circuit board and its manufacturing method - Google Patents

Circuit board and its manufacturing method Download PDF

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JP2006147913A
JP2006147913A JP2004337264A JP2004337264A JP2006147913A JP 2006147913 A JP2006147913 A JP 2006147913A JP 2004337264 A JP2004337264 A JP 2004337264A JP 2004337264 A JP2004337264 A JP 2004337264A JP 2006147913 A JP2006147913 A JP 2006147913A
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resistor
circuit board
wiring pattern
ceramic green
hole
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Hisao Miura
久雄 三浦
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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Priority to JP2004337264A priority Critical patent/JP2006147913A/en
Priority to CNA2005101254970A priority patent/CN1780527A/en
Priority to KR1020050111148A priority patent/KR100753231B1/en
Publication of JP2006147913A publication Critical patent/JP2006147913A/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/22—Apparatus or processes specially adapted for manufacturing resistors adapted for trimming
    • H01C17/24—Apparatus or processes specially adapted for manufacturing resistors adapted for trimming by removing or adding resistive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive circuit board with sufficient productivity in which a resistor is easily trimmed, and also to provide the manufacturing method of the board. <P>SOLUTION: The circuit board is provided with a multilayer substrate 1 formed of a plurality of ceramic insulating layers 2, wiring patterns 3 installed in the multilayer substrate 1, and resistors 5a and 5b arranged in lamination of the multilayer substrate 1. Holes 1b are made in positions confronted with the resistors 5a and 5b in the insulating layer 2 forming the multilayer substrate 1. The resistors 5a and 5b can be trimmed through the holes 1b. Thus, the resistors 5a and 5b can be trimmed after the multilayer substrate 1 is formed. The multilayer substrate 1, the wiring patterns 3 and the resistors 5a and 5b can easily be manufactured compared to a conventional case, productivity is sufficient, cost is inexpensive and trimming is realized through the holes 1b. Thus, the resistor is easily trimmed without deleting the insulating layer 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は近距離無線装置等の種々の電子機器や電子回路ユニット等に適用して好適な回路基板、及びその製造方法に関する。   The present invention relates to a circuit board suitable for application to various electronic devices such as a short-range wireless device, an electronic circuit unit, and the like, and a manufacturing method thereof.

従来の回路基板、及びその製造方法に係る図面を説明すると、図６は従来の回路基板の要部断面図、図７は従来の回路基板の製造方法に係る第１工程を示す説明図、図８は従来の回路基板の製造方法に係る第２工程を示す説明図、図９は従来の回路基板の製造方法に係る第３工程を示す説明図である。   FIG. 6 is a cross-sectional view of a main part of a conventional circuit board, and FIG. 7 is an explanatory view showing a first step according to the conventional circuit board manufacturing method. 8 is an explanatory view showing a second step according to a conventional method for manufacturing a circuit board, and FIG. 9 is an explanatory view showing a third step according to a conventional method for manufacturing a circuit board.

次に、従来の回路基板の構成を図６に基づいて説明すると、多層基板５１は、アルミナ基板５２と、このアルミナ基板５２上に設けられたガラスからなる複数の絶縁層５３とで形成されている。   Next, the configuration of the conventional circuit board will be described with reference to FIG. 6. The multilayer substrate 51 is formed of an alumina substrate 52 and a plurality of insulating layers 53 made of glass provided on the alumina substrate 52. Yes.

また、多層基板５１の表面と積層内には、配線パターン５４が設けられ、表面と積層内の配線パターン５４間は、接続導体５５によって接続されると共に、多層基板５１の積層内には、配線パターン５４に接続され、且つ、絶縁層５３で覆われた抵抗体５６が設けられ、更に、多層基板５１の表面には、電子部品５７が搭載されて、従来の回路基板が形成されている。（例えば、特許文献１参照）   In addition, a wiring pattern 54 is provided on the surface of the multilayer substrate 51 and in the stack, and the wiring pattern 54 in the stack and the surface of the multilayer substrate 51 is connected by a connection conductor 55. A resistor 56 connected to the pattern 54 and covered with the insulating layer 53 is provided, and an electronic component 57 is mounted on the surface of the multilayer substrate 51 to form a conventional circuit board. (For example, see Patent Document 1)

次に、従来の回路基板の製造方法を図７〜図９に基づいて説明すると、先ず、図７に示すように、アルミナ基板５２上には、導電ペーストを印刷した後、導電ペーストを焼成して配線パターン５４を形成し、しかる後、抵抗ペーストを印刷した後、抵抗ペーストを焼成して抵抗体５６を形成する。   Next, a conventional circuit board manufacturing method will be described with reference to FIGS. 7 to 9. First, as shown in FIG. 7, after the conductive paste is printed on the alumina substrate 52, the conductive paste is baked. Then, the wiring pattern 54 is formed, and then the resistance paste is printed, and then the resistance paste is baked to form the resistor 56.

次に、図８に示すように、アルミナ基板５２と配線パターン５４と抵抗体５６上には、ガラスペーストを印刷した後、ガラスペーストを焼成して、１層目の絶縁層５３を形成する。   Next, as shown in FIG. 8, after the glass paste is printed on the alumina substrate 52, the wiring pattern 54, and the resistor 56, the glass paste is baked to form the first insulating layer 53.

次に、図９に示すように、１層目の絶縁層５３上には、ガラスペーストを印刷した後、ガラスペーストを焼成して、２層目の絶縁層５３を形成し、しかる後、２層目の絶縁層５３上には、ガラスペーストを印刷した後、ガラスペーストを焼成して、３層目の絶縁層５３を形成し、更に、３層目の絶縁層５３上には、導電ペーストを印刷した後、導電ペーストを焼成して配線パターン５４を形成し、しかる後、電子部品５７を搭載すると、従来の回路基板の製造が完了する。（例えば、特許文献１参照）   Next, as shown in FIG. 9, after the glass paste is printed on the first insulating layer 53, the glass paste is baked to form the second insulating layer 53, and then 2 After the glass paste is printed on the third insulating layer 53, the glass paste is baked to form the third insulating layer 53. Further, the conductive paste is formed on the third insulating layer 53. After printing, the conductive paste is baked to form the wiring pattern 54. After that, when the electronic component 57 is mounted, the manufacture of the conventional circuit board is completed. (For example, see Patent Document 1)

また、従来の回路基板、及びその製造方法にあっては、抵抗体５６のトリミングが図７に示す抵抗体５６を焼成した後、或いは、図８に示す１層目の絶縁層５３を形成した後に行うようになっているが、何れの場合も、トリミングされた後に、２層目、３層目の絶縁層５３と表面に形成される配線パターン５４のそれぞれは、別工程で印刷と焼成によって形成されるため、その製造が面倒で、生産性が悪く、コスト高になるばかりか、多層基板５１が形成された後に、抵抗体５６のトリミングを行う場合は、絶縁層５３を削る必要があり、その作業性が悪くなる。   Further, in the conventional circuit board and the manufacturing method thereof, trimming of the resistor 56 is performed after the resistor 56 shown in FIG. 7 is fired, or the first insulating layer 53 shown in FIG. 8 is formed. In each case, after trimming, the second and third insulating layers 53 and the wiring pattern 54 formed on the surface are separately printed and fired in separate steps. Therefore, when the multi-layer substrate 51 is formed and the trimming of the resistor 56 is performed, the insulating layer 53 needs to be cut off. The workability becomes worse.

特開平６−２４４３６２号公報JP-A-6-244362

従来の回路基板、及びその製造方法にあっては、抵抗体５６がトリミングされた後に、２層目、３層目の絶縁層５３と表面に形成される配線パターン５４のそれぞれは、別工程で印刷と焼成によって形成されるため、その製造が面倒で、生産性が悪く、コスト高になるばかりか、多層基板５１が形成された後に、抵抗体５６のトリミングを行う場合は、絶縁層５３を削る必要があり、その作業性が悪くなるという問題がある。   In the conventional circuit board and the manufacturing method thereof, after the resistor 56 is trimmed, the second and third insulating layers 53 and the wiring pattern 54 formed on the surface are formed in separate steps. Since it is formed by printing and baking, the manufacturing is troublesome, the productivity is poor, the cost is increased, and when the resistor 56 is trimmed after the multilayer substrate 51 is formed, the insulating layer 53 is formed. There is a problem that it is necessary to cut and the workability is deteriorated.

そこで、本発明は生産性が良く、安価であると共に、抵抗体のトリミングの容易な回路基板、及びその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit board that has good productivity, is inexpensive, and that allows easy trimming of a resistor, and a method of manufacturing the circuit board.

上記課題を解決するための第１の解決手段として、セラミックの複数の絶縁層からなる多層基板と、この多層基板の表面と積層内に設けられた配線パターンと、この配線パターンに接続された状態で、前記多層基板の積層内に設けられた抵抗体とを備え、前記多層基板を形成する前記絶縁層には、前記抵抗体と対向する位置に、前記抵抗体の表面を露出するための孔が設けられ、前記孔を通して前記抵抗体のトリミングを可能とした構成とした。   As a first means for solving the above problems, a multilayer substrate composed of a plurality of ceramic insulating layers, a wiring pattern provided on the surface of the multilayer substrate and in the stack, and a state connected to the wiring pattern And a resistor provided in a stack of the multilayer substrate, and the insulating layer forming the multilayer substrate has a hole for exposing a surface of the resistor at a position facing the resistor. And the resistor can be trimmed through the hole.

また、第２の解決手段として、前記孔内には、ガラス、或いは絶縁樹脂からなる封止部が設けられた構成とした。
また、第３の解決手段として、前記孔の上部には、前記配線パターンに接続された状態で、電子部品が配置された構成とした。 As a second solving means, a sealing portion made of glass or insulating resin is provided in the hole.
As a third solving means, an electronic component is arranged above the hole in a state of being connected to the wiring pattern.

また、第４の解決手段として、請求項１記載の回路基板を備え、前記配線パターンと前記抵抗体が設けられた前記絶縁層を形成するための第１のセラミックグリーンシートには、表面に前記配線パターンが設けられ、且つ、前記抵抗体と対向する位置に前記孔を設けた前記絶縁層を形成するための第２のセラミックグリーンシートを重ね合わされた後、或いは、前記配線パターンと前記抵抗体が設けられた前記絶縁層を形成するための前記第１のセラミックグリーンシートには、前記抵抗体と対向する位置に前記孔を設けた前記絶縁層を形成するための前記第２のセラミックグリーンシートが重ね合わされ、前記第２のセラミックグリーンシートの表面に前記配線パターンを形成した後、前記配線パターン、前記抵抗体、及び前記第１，第２のセラミックグリーンシートを同時に焼成し、しかる後、前記孔を通して前記抵抗体のトリミングを行うようにした製造方法とした。   As a fourth solution, the first ceramic green sheet for forming the insulating layer provided with the circuit board according to claim 1 and provided with the wiring pattern and the resistor is provided on the surface thereof. After the second ceramic green sheet for forming the insulating layer provided with the hole is provided at a position facing the resistor and the wiring pattern is overlaid, or after the wiring pattern and the resistor The first ceramic green sheet for forming the insulating layer provided with the second ceramic green sheet for forming the insulating layer provided with the hole at a position facing the resistor. And the wiring pattern is formed on the surface of the second ceramic green sheet, and then the wiring pattern, the resistor, and the first and second Firing the ceramic green sheets simultaneously, thereafter, it was manufacturing method to perform the trimming of the resistor through the holes.

また、第５の解決手段として、前記抵抗体のトリミングを行った後、前記孔内には、ガラス、或いは絶縁樹脂が充填された後、前記ガラスは焼成されると共に、前記絶縁樹脂は加熱によって硬化させて、前記孔を塞ぐ封止部を形成した製造方法とした。   As a fifth solution, after trimming the resistor, the hole is filled with glass or insulating resin, and then the glass is baked and the insulating resin is heated. It was made into the manufacturing method which hardened and formed the sealing part which block | closes the said hole.

本発明の回路基板は、セラミックの複数の絶縁層からなる多層基板と、この多層基板の表面と積層内に設けられた配線パターンと、この配線パターンに接続された状態で、多層基板の積層内に設けられた抵抗体とを備え、多層基板を形成する絶縁層には、抵抗体と対向する位置に、抵抗体の表面を露出するための孔が設けられ、孔を通して抵抗体のトリミングを可能としたため、多層基板の形成後、抵抗体のトリミングが可能となって、従来に比して、多層基板、配線パターン、及び抵抗体の製造が容易で、生産性が良く、安価であると共に、トリミングが孔を通して行えるため、絶縁層を削ることが無く、トリミングの容易なものが得られる。   The circuit board according to the present invention includes a multilayer board composed of a plurality of ceramic insulating layers, a wiring pattern provided on the surface of the multilayer board and in the lamination, and a multilayer board in a state of being connected to the wiring pattern. The insulating layer that forms the multilayer substrate is provided with a hole to expose the surface of the resistor at a position facing the resistor, and the resistor can be trimmed through the hole. Therefore, after the multilayer substrate is formed, the resistor can be trimmed, and the multilayer substrate, the wiring pattern, and the resistor can be easily manufactured, and the productivity is good, and the cost is low. Since trimming can be performed through the holes, the insulating layer is not cut and an easy trimming can be obtained.

また、孔内には、ガラス、或いは絶縁樹脂からなる封止部が設けられたため、埃や湿気等から抵抗体が封止部で保護できて、性能の良好なものが得られる。   In addition, since the sealing portion made of glass or insulating resin is provided in the hole, the resistor can be protected from the dust and moisture by the sealing portion, and a good performance can be obtained.

また、孔の上部には、配線パターンに接続された状態で、電子部品が配置されたため、スペースファクタが良くなって、小型化できる。   In addition, since the electronic components are arranged in the state of being connected to the wiring pattern above the holes, the space factor is improved and the size can be reduced.

また、回路基板を備え、配線パターンと抵抗体が設けられた絶縁層を形成するための第１のセラミックグリーンシートには、表面に配線パターンが設けられ、且つ、抵抗体と対向する位置に孔を設けた絶縁層を形成するための第２のセラミックグリーンシートを重ね合わされた後、或いは、配線パターンと抵抗体が設けられた絶縁層を形成するための第１のセラミックグリーンシートには、抵抗体と対向する位置に孔を設けた絶縁層を形成するための第２のセラミックグリーンシートが重ね合わされ、第２のセラミックグリーンシートの表面に配線パターンを形成した後、配線パターン、抵抗体、及び第１，第２のセラミックグリーンシートを同時に焼成し、しかる後、孔を通して抵抗体のトリミングを行うようにしたため、多層基板の形成後、抵抗体のトリミングが可能となって、従来に比して、多層基板、配線パターン、及び抵抗体の製造が容易で、生産性が良く、安価であると共に、トリミングが孔を通して行えるため、絶縁層を削ることが無く、トリミングの容易なものが得られる。   In addition, the first ceramic green sheet provided with a circuit board and forming an insulating layer provided with a wiring pattern and a resistor has a wiring pattern on the surface and has a hole at a position facing the resistor. The first ceramic green sheet for forming the insulating layer provided with the wiring pattern and the resistor is overlapped with the second ceramic green sheet for forming the insulating layer provided with the wiring pattern or the resistor. A second ceramic green sheet for forming an insulating layer having a hole at a position facing the body is overlaid, and after forming a wiring pattern on the surface of the second ceramic green sheet, the wiring pattern, the resistor, and Since the first and second ceramic green sheets were fired at the same time and then the resistor was trimmed through the holes, the multilayer substrate was formed. The resistor can be trimmed, and it is easier to manufacture multilayer substrates, wiring patterns, and resistors than before. The layer can be easily trimmed without cutting the layer.

また、抵抗体のトリミングを行った後、孔内には、ガラス、或いは絶縁樹脂が充填された後、ガラスは焼成されると共に、絶縁樹脂は加熱によって硬化させて、孔を塞ぐ封止部を形成したため、埃や湿気等から抵抗体が封止部で保護できて、性能の良好なものが得られる。   In addition, after trimming the resistor, the hole is filled with glass or insulating resin, and then the glass is baked and the insulating resin is cured by heating to form a sealing portion that closes the hole. Since it was formed, the resistor can be protected from the dust and moisture by the sealing portion, and a product with good performance can be obtained.

本発明の回路基板、及びその製造方法に係る図面を説明すると、図１は本発明の回路基板の要部断面図、図２は本発明の回路基板の製造方法に係る第１工程を示す説明図、図３は本発明の回路基板の製造方法に係る第２工程を示す説明図、図４は本発明の回路基板の製造方法に係る第３工程を示す説明図、図５は本発明の回路基板の製造方法に係る第４工程を示す説明図である。   FIG. 1 is a cross-sectional view of an essential part of a circuit board according to the present invention, and FIG. 2 is a diagram illustrating a first step according to the method for manufacturing a circuit board according to the present invention. FIG. 3 is an explanatory view showing a second step according to the method for manufacturing a circuit board according to the present invention, FIG. 4 is an explanatory view showing a third step according to the method for manufacturing a circuit board according to the present invention, and FIG. It is explanatory drawing which shows the 4th process which concerns on the manufacturing method of a circuit board.

次に、本発明の回路基板の構成を図１に基づいて説明すると、多層基板１は、低温焼成セラミック（ＬＴＣＣ）等のセラミックからなる複数（３層）の絶縁層２の積層によって形成され、厚み方向に設けられた複数の小さい孔１ａと大きな孔１ｂを有する。   Next, the configuration of the circuit board of the present invention will be described with reference to FIG. 1. The multilayer substrate 1 is formed by laminating a plurality (three layers) of insulating layers 2 made of a ceramic such as a low-temperature fired ceramic (LTCC). It has a plurality of small holes 1a and large holes 1b provided in the thickness direction.

また、多層基板１の表面と積層内には、配線パターン３が設けられ、表面と積層内の配線パターン３間は、孔１ａに設けられた接続導体（スルーホール）４によって接続されると共に、多層基板１の積層内には、配線パターン３に接続された厚膜からなる複数の抵抗体５ａ，５ｂが設けられている。   In addition, a wiring pattern 3 is provided on the surface of the multilayer substrate 1 and in the laminate, and the surface and the wiring pattern 3 in the laminate are connected by a connection conductor (through hole) 4 provided in the hole 1a. In the multilayer substrate 1, a plurality of resistors 5 a and 5 b made of thick films connected to the wiring pattern 3 are provided.

この抵抗体５ａ、５ｂの上部には、孔１ｂが対向した位置にあって、抵抗体５ａ、５ｂの表面が露出した状態となり、孔１ｂを通して抵抗体５ａ、５ｂのトリミングが可能で、トリミングされた後、孔５ａ、５ｂ内には、ガラス、或いは絶縁樹脂からなる封止部６が設けられている。   On top of the resistors 5a and 5b, the hole 1b is located opposite to the surface of the resistors 5a and 5b. The resistors 5a and 5b can be trimmed through the hole 1b. After that, a sealing portion 6 made of glass or insulating resin is provided in the holes 5a and 5b.

ＩＣ部品等からなる電子部品７は、多層基板１の表面に設けられた配線パターン３に接続された状態で搭載され、所望の電気回路が形成されると共に、この電子部品７の少なくとも１個は、孔５ａ、或いは５ｂの上部に配置されて、本発明の回路基板が形成されている。   An electronic component 7 composed of an IC component or the like is mounted in a state of being connected to a wiring pattern 3 provided on the surface of the multilayer substrate 1 to form a desired electric circuit, and at least one of the electronic components 7 is The circuit board of the present invention is formed by being arranged above the holes 5a or 5b.

このような構成を有する本発明の回路基板は、ここでは図示しないが、電気機器のマザー基板上に載置され、多層基板１の下面に設けた配線パターン（端子）３がマザー基板の回路パターンに半田付けされて、回路基板が面実装されるようになっている。   Although the circuit board of the present invention having such a configuration is not shown here, the circuit pattern of the mother board is placed on the mother board of the electric device, and the wiring pattern (terminal) 3 provided on the lower surface of the multilayer board 1 is the circuit pattern of the mother board. The circuit board is surface-mounted by soldering.

なお、この実施例では、絶縁層２が３層のもので説明したが、２層、或いは４層以上のものでも良く、また、抵抗体５ａ、５ｂは、何れか一方でも良く、更に、４層以上の場合にあっては、抵抗体を積層内の適宜箇所に設けても良い。   In this embodiment, the insulating layer 2 has been described as having three layers. However, the insulating layer 2 may be two layers or four or more layers, and either one of the resistors 5a and 5b may be used. In the case of more layers, a resistor may be provided at an appropriate location in the stack.

次に、本発明の回路基板の製造方法を図１〜図５に基づいて説明すると、先ず、図２に示すように、孔１ａを設けた絶縁層２を形成するための第１のセラミックグリーンシート２ａを用意し、この第１のセラミックグリーンシート２ａの表面には、配線パターン３を形成するための導電ペーストが印刷されると共に、この導電ペーストに接続された状態、抵抗体５ａを形成するための抵抗ペーストが印刷される。   Next, a method for manufacturing a circuit board according to the present invention will be described with reference to FIGS. 1 to 5. First, as shown in FIG. 2, a first ceramic green for forming an insulating layer 2 provided with holes 1a is provided. A sheet 2a is prepared, and a conductive paste for forming the wiring pattern 3 is printed on the surface of the first ceramic green sheet 2a, and a resistor 5a is formed in a state connected to the conductive paste. Resistive paste for printing.

次に、図３に示すように、孔１ａ、１ｂを設けた第２のセラミックグリーンシート２ｂが第１のセラミックグリーンシート２ａ上に重ね合わされ後、第２のセラミックグリーンシート２ｂの表面には、配線パターン３を形成するための導電ペーストが印刷されると共に、この導電ペーストに接続された状態、抵抗体５ｂを形成するための抵抗ペーストが印刷され、また、孔１ａ内には、接続導体４を形成するための導電ペーストが充填される。   Next, as shown in FIG. 3, after the second ceramic green sheet 2b provided with the holes 1a and 1b is overlaid on the first ceramic green sheet 2a, the surface of the second ceramic green sheet 2b is A conductive paste for forming the wiring pattern 3 is printed, and a resistance paste for forming the resistor 5b is printed in a state connected to the conductive paste, and the connection conductor 4 is formed in the hole 1a. The conductive paste for forming the is filled.

この時、第２のセラミックグリーンシート２ｂに設けられた孔１ｂは、抵抗体５ａに対向した状態となっている。
なお、ここでは、第２のセラミックグリーンシート２ｂが第１のセラミックグリーンシート２ａ上に重ね合わされ後、第２のセラミックグリーンシート２ｂ上に導電ペーストと抵抗ペーストを設けたもので説明したが、導電ペーストと抵抗ペーストを第２のセラミックグリーンシート２ｂ上に設けた後、第２のセラミックグリーンシート２ｂを第１のセラミックグリーンシート２ａ上に重ね合わせるようにしても良い。 At this time, the hole 1b provided in the second ceramic green sheet 2b is in a state of facing the resistor 5a.
Note that here, the second ceramic green sheet 2b is overlaid on the first ceramic green sheet 2a and then the conductive paste and the resistance paste are provided on the second ceramic green sheet 2b. After the paste and the resistance paste are provided on the second ceramic green sheet 2b, the second ceramic green sheet 2b may be superposed on the first ceramic green sheet 2a.

次に、図４に示すように、孔１ａ、１ｂを設けた第３のセラミックグリーンシート２ｃが第２のセラミックグリーンシート２ｂ上に重ね合わされ後、第３のセラミックグリーンシート２ｃの表面には、配線パターン３を形成するための導電ペーストが印刷されると共に、孔１ａ内には、接続導体４を形成するための導電ペーストが充填される。   Next, as shown in FIG. 4, after the third ceramic green sheet 2c provided with the holes 1a and 1b is overlaid on the second ceramic green sheet 2b, the surface of the third ceramic green sheet 2c is A conductive paste for forming the wiring pattern 3 is printed, and a conductive paste for forming the connection conductor 4 is filled in the holes 1a.

この時、第３のセラミックグリーンシート２ｃに設けられた孔１ｂは、抵抗体５ａに対向した状態となっている。
なお、ここでは、第３のセラミックグリーンシート２ｃが第２のセラミックグリーンシート２ｂ上に重ね合わされ後、第３のセラミックグリーンシート２ｃ上に導電ペーストを設けたもので説明したが、導電ペーストを第３のセラミックグリーンシート２ｃ上に設けた後、第３のセラミックグリーンシート２ｃを第２のセラミックグリーンシート２ｃ上に重ね合わせるようにしても良い。 At this time, the hole 1b provided in the third ceramic green sheet 2c is in a state of facing the resistor 5a.
Note that here, the third ceramic green sheet 2c is overlaid on the second ceramic green sheet 2b and then the conductive paste is provided on the third ceramic green sheet 2c. After being provided on the third ceramic green sheet 2c, the third ceramic green sheet 2c may be superposed on the second ceramic green sheet 2c.

次に、このような状態（３層が重ね合わされた状態）で、配線パターン３，接続導体４，抵抗体５ａ、５ｂ、及び第１〜第３のセラミックグリーンシート２ａ、２ｂ、２ｃが約８５０度で同時に焼成された後、レーザ等の切削装置によって、孔１ｂを通して抵抗体５ａ、５ｂのトリミングを行う。   Next, in such a state (a state in which three layers are overlaid), the wiring pattern 3, the connecting conductor 4, the resistors 5a and 5b, and the first to third ceramic green sheets 2a, 2b, and 2c are about 850. After firing at the same time, the resistors 5a and 5b are trimmed through the holes 1b by a cutting device such as a laser.

次に、図５に示すように、抵抗体のトリミングを行った後、孔１ｂ内には、ガラスの封止部６を形成するためのガラスペースト、或いは絶縁樹脂の封止部６を形成するための熱硬化性絶縁樹脂ペーストが充填された後、ガラスペーストは約６００度で焼成されると共に、熱硬化性絶縁樹脂ペーストは約２００度で加熱されて硬化させることによって、孔１ｂを塞ぐ封止部６を形成する。
そして、図１に示すように、多層基板１の表面には、電子部品７が搭載されると、本発明の回路基板の製造が完了する。 Next, as shown in FIG. 5, after trimming the resistor, a glass paste for forming a glass sealing portion 6 or an insulating resin sealing portion 6 is formed in the hole 1b. After the thermosetting insulating resin paste is filled, the glass paste is baked at about 600 degrees, and the thermosetting insulating resin paste is heated at about 200 degrees and cured to close the hole 1b. A stop 6 is formed.
Then, as shown in FIG. 1, when the electronic component 7 is mounted on the surface of the multilayer substrate 1, the manufacture of the circuit board of the present invention is completed.

本発明の回路基板の要部断面図。The principal part sectional drawing of the circuit board of this invention. 本発明の回路基板の製造方法に係る第１工程を示す説明図。Explanatory drawing which shows the 1st process which concerns on the manufacturing method of the circuit board of this invention. 本発明の回路基板の製造方法に係る第２工程を示す説明図。Explanatory drawing which shows the 2nd process which concerns on the manufacturing method of the circuit board of this invention. 本発明の回路基板の製造方法に係る第３工程を示す説明図。Explanatory drawing which shows the 3rd process which concerns on the manufacturing method of the circuit board of this invention. 本発明の回路基板の製造方法に係る第４工程を示す説明図。Explanatory drawing which shows the 4th process which concerns on the manufacturing method of the circuit board of this invention. 従来の回路基板の要部断面図。Sectional drawing of the principal part of the conventional circuit board. 従来の回路基板の製造方法に係る第１工程を示す説明図。Explanatory drawing which shows the 1st process which concerns on the manufacturing method of the conventional circuit board. 従来の回路基板の製造方法に係る第２工程を示す説明図。Explanatory drawing which shows the 2nd process which concerns on the manufacturing method of the conventional circuit board. 従来の回路基板の製造方法に係る第３工程を示す説明図。Explanatory drawing which shows the 3rd process which concerns on the manufacturing method of the conventional circuit board.

符号の説明Explanation of symbols

１：多層基板
１ａ、１ｂ：孔
２：絶縁層
２ａ：第１のセラミックグリーンシート
２ｂ：第２のセラミックグリーンシート
２ｃ：第３のセラミックグリーンシート
３：配線パターン
４：接続導体
５ａ，５ｂ：抵抗体
６：封止部
７：電子部品
1: multilayer substrate 1a, 1b: hole 2: insulating layer 2a: first ceramic green sheet 2b: second ceramic green sheet 2c: third ceramic green sheet 3: wiring pattern 4: connection conductors 5a, 5b: resistance Body 6: Sealing part 7: Electronic component

Claims (5)

セラミックの複数の絶縁層からなる多層基板と、この多層基板の表面と積層内に設けられた配線パターンと、この配線パターンに接続された状態で、前記多層基板の積層内に設けられた抵抗体とを備え、前記多層基板を形成する前記絶縁層には、前記抵抗体と対向する位置に、前記抵抗体の表面を露出するための孔が設けられ、前記孔を通して前記抵抗体のトリミングを可能としたことを特徴とする回路基板。 A multilayer substrate composed of a plurality of ceramic insulating layers, a wiring pattern provided on the surface of the multilayer substrate and in the laminate, and a resistor provided in the laminate of the multilayer substrate in a state connected to the wiring pattern The insulating layer forming the multilayer substrate is provided with a hole for exposing the surface of the resistor at a position facing the resistor, and the resistor can be trimmed through the hole. A circuit board characterized by that. 前記孔内には、ガラス、或いは絶縁樹脂からなる封止部が設けられたことを特徴とする請求項１記載の回路基板。 The circuit board according to claim 1, wherein a sealing portion made of glass or insulating resin is provided in the hole. 前記孔の上部には、前記配線パターンに接続された状態で、電子部品が配置されたことを特徴とする請求項１、又は２記載の回路基板。 3. The circuit board according to claim 1, wherein an electronic component is disposed above the hole in a state of being connected to the wiring pattern. 4. 請求項１記載の回路基板を備え、前記配線パターンと前記抵抗体が設けられた前記絶縁層を形成するための第１のセラミックグリーンシートには、表面に前記配線パターンが設けられ、且つ、前記抵抗体と対向する位置に前記孔を設けた前記絶縁層を形成するための第２のセラミックグリーンシートを重ね合わされた後、或いは、前記配線パターンと前記抵抗体が設けられた前記絶縁層を形成するための前記第１のセラミックグリーンシートには、前記抵抗体と対向する位置に前記孔を設けた前記絶縁層を形成するための前記第２のセラミックグリーンシートが重ね合わされ、前記第２のセラミックグリーンシートの表面に前記配線パターンを形成した後、前記配線パターン、前記抵抗体、及び前記第１，第２のセラミックグリーンシートを同時に焼成し、しかる後、前記孔を通して前記抵抗体のトリミングを行うようにしたことを特徴とする回路基板の製造方法。 A circuit board according to claim 1, wherein a first ceramic green sheet for forming the insulating layer provided with the wiring pattern and the resistor is provided with the wiring pattern on a surface thereof, and After the second ceramic green sheet for forming the insulating layer provided with the hole at a position facing the resistor is overlaid, or the insulating layer provided with the wiring pattern and the resistor is formed. The second ceramic green sheet for forming the insulating layer provided with the hole at a position facing the resistor is overlaid on the first ceramic green sheet for performing the second ceramic green sheet, After forming the wiring pattern on the surface of the green sheet, the wiring pattern, the resistor, and the first and second ceramic green sheets are And baked at, thereafter, a manufacturing method of a circuit board, characterized in that to perform the trimming of the resistor through the holes. 前記抵抗体のトリミングを行った後、前記孔内には、ガラス、或いは絶縁樹脂が充填された後、前記ガラスは焼成されると共に、前記絶縁樹脂は加熱によって硬化させて、前記孔を塞ぐ封止部を形成したことを特徴とする請求項４記載の回路基板の製造方法。
After trimming the resistor, the hole is filled with glass or insulating resin, and then the glass is fired and the insulating resin is cured by heating to seal the hole. The circuit board manufacturing method according to claim 4, wherein a stop portion is formed.
JP2004337264A 2004-11-22 2004-11-22 Circuit board and its manufacturing method Withdrawn JP2006147913A (en)

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CNA2005101254970A CN1780527A (en) 2004-11-22 2005-11-17 Electric circuit substrate and its manufacture
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