JP3109138B2 - Multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for multiplying an analog signal, and more particularly to a multiplier configured on a C-MOS integrated circuit.

[0002]

2. Description of the Related Art As is well known, a Gilbert multiplier is known as a multiplier, which is formed on a bipolar integrated circuit.
FIG. 5 shows a configuration on an S integrated circuit. In FIG. 5, the pseudo Gilbert multiplier includes two differential pair transistors ((M1, M2), (M3, M4)) between a (first) input terminal pair (1, 2), The second input terminal pair (3, 4)
One of the differential pair transistors for driving the respective pairs of the differential pair transistors (M5, M6) disposed, which has so as to drive the one of the differential pair transistors in one of the constant current source I ₀ is there.

That is, two pairs of differential pair transistors ((M
1, M2), (M3, M4)), the drains of one transistor (M1, M3) and the drains of the other transistor (M2, M4) are connected in common, respectively, and the (first) differential pair The gate of one transistor M1 of the transistors (M1, M2) and the gate of the other transistor M3 of the (second) differential pair transistor are commonly connected to one input terminal 1 of the input terminal pair (1, 2). And
The gate of the other transistor M2 of the differential pair transistor (M1, M2) and the gate of the one transistor M3 of the differential pair transistor (M3, M4) are commonly used as the other input terminal of the input terminal pair (1, 2). 2 is connected. And
In one differential pair transistor (M5, M6), one transistor M5 has a drain connected to the source of the differential pair transistor (M1, M2), and a gate connected to one of the input terminal pair (3, 4). The transistor M6 is connected to the input terminal 3 and has a drain connected to the source of the differential pair transistor (M3, M4) and a gate connected to one input terminal 4 of the input terminal pair (3, 4). You.

In this pseudo Gilbert multiplier,
Two input signals (voltage V _1, the V ₂₎ with respect to the differential output current I _1, the difference between the I ₂ (I ₁ -I ₂₎ is as shown in the following Equation 1, voltage V _1, the proportional to the product of V _2. Note that in the formulas, α ₁ and α ₂ are represented by Expressions 2 and 3, where μ _{n is} the mobility of the transistor and C _OX is the capacitance of the gate oxide film.

[0005]

(Equation 1)

[0006]

(Equation 2)

[0007]

(Equation 3)

In equations 2 and 3, W1 / L
1, W5 / L5 is the ratio (W / L) of the gate width W and the gate length L of the transistors M1 and M5, and the W / L of the transistors (M2, M3, M4) is equal to that of the transistor M1 (formula (1)). 4), W / L of the transistor M6 is equal to that of the transistor M5 (Equation 5).

[0009]

(Equation 4)

[0010]

(Equation 5)

[0011]

In the pseudo-Gilbert multiplier described above, the second input voltage (V ₂ )
Since the range of linearity obtained for the first input voltage (V ₁ ) is smaller than the range of linearity obtained for
There is a problem that it is difficult to use as an analog multiplier. Conventionally, the grounds for this problem have not always been clear, but as a result of a detailed study of the derivation process of Equation 1, the grounds have been clarified. This will be described below.

The transistors (M1, M2, M3, M4,
M5, M6) The respective drain currents (I _d1 , I _d2 , I
_d3 , _Id4 , _Id5 , _Id6 ) are given by the following equations 6 to 11.
In the _{formulas, V gsi (i = 1,2,} ......, 6) is a gate-source voltage of the transistor Mi, the V _t is a pinch-off voltage of the transistor.

[0013]

(Equation 6)

[0014]

(Equation 7)

[0015]

(Equation 8)

[0016]

(Equation 9)

[0017]

(Equation 10)

[0018]

[Equation 11]

Here, I _d5 , I _d6 , I ₀ , V ₁ and V ₂ can be expressed by the following equations (12) to (16).

[0020]

(Equation 12)

[0021]

(Equation 13)

[0022]

[Equation 14]

[0023]

(Equation 15)

[0024]

(Equation 16)

Then, if I _V2 is placed as shown in the following Expression 17, from Expressions 14 and 17, I _d5 and I _{d6 become} the following Expression 1.
8 and 19 are obtained.

[0026]

[Equation 17]

[0027]

(Equation 18)

[0028]

[Equation 19]

When I _V1 is set as in the following equation 20, the input voltage V ₁ is obtained as in the following equation 21.

[0030]

(Equation 20)

[0031]

(Equation 21)

Then, I ₁ -I ₂ is given by the following equation (22).
become that way.

[0033]

(Equation 22)

Here, when f (x), g (x), and h (x) are placed as shown in the following Expressions 23 to 25 and h (x) is series-expanded, Expression 26 is obtained.

[0035]

(Equation 23)

[0036]

(Equation 24)

[0037]

(Equation 25)

[0038]

(Equation 26)

In Equation 23, the one-time derivative of f (x) is Equation 27, and the value of x = 0 is Equation 28.
The second derivative of f (x) is given by Expression 29, and x
The value of = 0 is Equation 30. Hereinafter, higher order values are similarly obtained.

[0040]

[Equation 27]

[0041]

[Equation 28]

[0042]

(Equation 29)

[0043]

[Equation 30]

In equation (24), the first derivative of g (x) is equation (31), and the value of x = 0 is equation (32). The second derivative of g (x) is represented by Expression 33, and the value of x = 0 is Expression 34. Hereinafter, higher order values are similarly obtained.

[0045]

(Equation 31)

[0046]

(Equation 32)

[0047]

[Equation 33]

[0048]

(Equation 34)

However, since f (0) = g (0) = 1, h (0) = 0. From the above, h (x) =
ax +..., and eventually I ₁ −I ₂ becomes the following Expression 35, and further, when Expression 20 and 21 are considered, Expression 36 is obtained.

[0050]

(Equation 35)

[0051]

[Equation 36]

[0052] In Equation 36, ignoring the second and subsequent terms, also ignoring V ₁ ^binomial as V ₁ ² = 0, I ₁
−I ₂ is obtained as in the following Expression 37.

[0053]

(37)

Further, when Equation 36 is further expanded into a series, I
_{Since 1−} I ₂ is given by the following equation 38, ignoring the quadratic terms of V ₁ and V ₂ yields equation 39. This is Equation 1 itself.

[0055]

(38)

[0056]

[Equation 39]

Now, from Expression 37, a circuit shown in FIG. 6 can be obtained from Expression 37 as an equalizing circuit of the pseudo Gilbert multiplier shown in FIG. Therefore, I _V1 is
Corresponds to the differential output current of the constant current source I _0/2 in driven differential amplifier (transfer curve) with respect to the input voltage V _1, also, I _V2 is a constant current source I ₀ to the input voltage V ₂ This corresponds to the differential output current (transfer curve) of the driven differential amplifier.

In short, the transfer of the differential amplifier
Since the curve can be regarded as a straight line if the input voltage is small,
Expression 37 shows a multiplier operating in a range where the input voltages V ₁ and V ₂ are small. From Expression 36, the input voltage V _{1 and the} voltage range with good linearity obtained for the input voltage V ₂ good voltage range of linearity obtained for V ₁ is from becoming narrow. For example, in the case of a transistor of the same size, the operating range of input voltages V ₁ is become 1 / √2 of the operating range of the input voltage V _2.

An object of the present invention is to provide a pseudo-Gilbert multiplier capable of greatly improving the linearity by expanding the operating range of the first input voltage.

[0060]

In order to achieve the above object, a multiplier according to the present invention has the following configuration. That is, the multiplier of the present invention is a first and a second differential pair transistor arranged between the first input terminal pair, and the two pairs of differential pair transistors are connected to each other by one of them. The drains of the transistors and the drains of the other transistors are commonly connected, and the first
The gate of one transistor of the differential pair transistor and the gate of the other transistor of the second differential pair transistor are commonly connected to one input terminal (one polarity) of the first input terminal pair. The gate of the other of the one differential pair transistor and the gate of one of the second differential pair transistors are commonly connected to the other input terminal (the other polarity) of the first input terminal pair. First and second differential pair transistors; n (n ≧ 2) pairs of differential pair transistors arranged between the second input terminal pairs, wherein the n pairs of differential pair transistors are: Are connected to the source of the first differential pair transistor in common with the drains, and are connected in common to the second gate in the gate of the first differential pair transistor.
, And the other transistor has a drain connected to the source of the second differential pair transistor in common and a gate connected in common to the second terminal of the second differential pair transistor. N pairs of differential pair transistors commonly connected to the other input terminal (the other polarity) of the pair of input terminals; n constant current sources having the same contents for driving each of the n pairs of differential pair transistors; It is characterized by having.

[0061]

Next, the operation of the multiplier of the present invention configured as described above will be described. The multiplier of the present invention
Two differential pair transistors are arranged between the first input terminal pair, and n sets (n ≧ n) of the same configuration are arranged between the second input terminal pairs.
2) The differential pair transistors are connected in parallel, and the drains of the n sets of differential pair transistors connected in parallel are connected to the corresponding sources of the two sets of differential pair transistors. Each set of differential pair transistors is driven by a constant current source having the same contents. Note that “the same configuration” means that the ratio between the gate width and the gate length is equal.

As a result, the operating range of the first input voltage applied to the first input terminal pair can be expanded, and the linearity can be greatly improved.

[0063]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a multiplier according to one embodiment of the present invention. In FIG. 1, in the pseudo Gilbert multiplier shown in FIG. 5, when one pair of differential pair transistors (M5, M6) has n ≧ 2, (n−1) sets Differential pair transistor (M ｛2
(N + 2) -1}, M {2 (n + 2)}) and the parallel connection, so as to drive each of the n sets including differential pair transistors (M5, M6) in the constant current source I ₀ of the same content is there. Note that (n-1) differential pair transistors (M
{2 (n + 2) -1}, M {2 (n + 2)}) The ratio of the gate width to the gate length is determined by the differential pair transistor (M
5, M6). Hereinafter, the case where n = 2, that is, the case where there is one additional differential pair transistor (this is referred to as M7 and M8) will be described.

The ratio (W / L) of the gate width W to the gate length L of each of the additional transistors M7 and M8 is equal to that of the transistors M5 and M6 (Equation 40).

[0065]

(Equation 40)

Therefore, additional transistors M7 and M8
Currents I _d7 , I _d8 and the input voltage V
_2, the respective relationship of the constant current source I ₀ is the following equation 41 to the 4
4, which are the same as those of the transistors M5 and M6.

[0067]

[Equation 41]

[0068]

(Equation 42)

[0069]

[Equation 43]

[0070]

[Equation 44]

Accordingly, if I _V2 is placed as in the following equation 45 in the same manner as in the above equation 17, from equations 44 and 45,
I _d7 and I _d8 are obtained as in the following Expressions 46 and 47, which are equal to I _d5 and I _d6 .

[0072]

[Equation 45]

[0073]

[Equation 46]

[0074]

[Equation 47]

When I _V1 is set as in the following equation (48), the input voltage V ₁ is obtained as in the following equation (49).

[0076]

[Equation 48]

[0077]

[Equation 49]

Then, I ₁ -I ₂ is given by the following equation (50).
Which is expanded into a series to obtain Equation 51.

[0079]

[Equation 50]

[0080]

(Equation 51)

Then, I ₁ -I ₂ are given by the following equations (48) and (49).
Is considered, the following Expression 52 is obtained.
Ignoring the later sections, also ignoring V ₁ ² wherein the V ₁ ² = 0, obtained as in Equation 53.

[0082]

(Equation 52)

[0083]

(Equation 53)

Here, from equation 53, I _V1 is the differential output current (transfer) of the differential amplifier driven by the constant current source I ₀ (conventionally I _0/2 ) with respect to the input voltage V ₁ . Curve), and I _V2 is the input voltage V
Indicates that the corresponding differential output current of the differential amplifier which is driven by a constant current source I ₀ (transfer curve) for _2.

In short, the transfer of the differential amplifier
Since the curve can be regarded as a straight line if the input voltage is small,
Equation 53 shows a multiplier operating in a range where the input voltages V ₁ and V ₂ are small. This is the same as the pseudo Gilbert multiplier shown in FIG.

However, from the comparison between Expressions 45 and 48,
If they are composed of transistors of the same size, that is, α ₁ =
Assuming that α ₂ , the characteristics of the multiplier become substantially equal for both of the _two input voltages V ₁ and V ₂ , so that the operating range of the input voltage V ₁ is correspondingly reduced by the pseudo Gilbert multiplication shown in FIG. It can be seen that the width is wider than that of the pliers, and the linearity of the multiplier is improved. Specifically, n = 2
In the configuration of (α ₁ = α ₂ ), the width becomes √2 times, and in the general configuration shown in FIG. 1, the width becomes √n times.

From the above, the equalizer circuit of the multiplier having the general configuration shown in FIG. 1 is as shown in FIG. 2, and its characteristics are as shown in FIG. 3 and FIG. Where I
_V1 is the following Expression 54.

[0088]

(Equation 54)

[0089]

As described above, according to the multiplier of the present invention, two pairs of differential pair transistors are arranged between the first input terminal pair, and the same configuration is provided between the second input terminal pair. And n pairs of differential pair transistors are connected in parallel,
The drains of each of the n sets of differential pair transistors connected in parallel are connected to corresponding sources of the two sets of differential pair transistors, and each of the n sets of differential pair transistors is connected to a constant current source having the same contents. Since the driving is performed, the operation range of the first input voltage applied to the first input terminal pair can be expanded, and the linearity can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a multiplier according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the multiplier shown in FIG.

FIG. 3 is a relationship diagram between an input voltage V ₁ and output currents (I ₁ , I ₂ ) when the input voltage V ₂ is used as a parameter.

FIG. 4 is a diagram showing a relationship between an input voltage V ₂ and an output current (I ₁ , I ₂ ) when the input voltage V ₁ is used as a parameter.

FIG. 5 is a circuit diagram of a pseudo Gilbert multiplier.

FIG. 6 is an equalization circuit diagram of a pseudo Gilbert multiplier.

[Explanation of symbols]

First input terminal second input terminal 3 input terminal 4 input terminals M1 transistor M2 transistor M3 transistor M4 transistor M5 transistor M6 transistor M {2 (n + 2) -1} transistor M {2 (n + 2) } transistor I ₀ a constant current source V ₁ input voltage V ₂ input voltage

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-24377 (JP, A) JP-A-63-308687 (JP, A) JP-A-60-146371 (JP, A) JP-A-3-3 72704 (JP, A) JP-A-4-156612 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06G 7/16 H03D 1/18

Claims (1)

(57) [Claims] 1. A first and a second differential pair transistor disposed between a first input terminal pair, wherein the two pairs of differential pair transistors are connected to each other by drains of one of the transistors. And the drains of the other transistors are commonly connected, and the gate of one of the first differential pair transistors and the gate of the other of the second differential pair transistors are commonly connected to the first input terminal pair. Connected to one input terminal (one polarity)
The gate of the other transistor of the first differential pair transistor and the gate of one of the second differential pair transistors are commonly connected to the other input terminal (the other polarity) of the first input terminal pair. First and second differential pair transistors; and n (n
≧ 2) sets of differential pair transistors, wherein one of the n pairs of differential pair transistors has a drain connected in common to the source of the first differential pair transistor, and a gate connected to the other. The other transistor is commonly connected to one input terminal (one polarity) of the second input terminal pair, the other transistor is connected to the source of the second differential pair transistor and the drain is commonly connected, and the gates are connected to each other N sets of differential pair transistors commonly connected to the other input terminal (the other polarity) of the second input terminal pair; n sets of the same contents for driving the n sets of differential pair transistors, respectively; A current source; and a multiplier.