JP2526805B2 - Multiplier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for multiplying analog signals, and more particularly to an analog multiplier composed of bipolar transistors and MOS transistors formed on a semiconductor integrated circuit.

[0002]

2. Description of the Related Art The present applicant has previously developed and applied for a multiplier as shown in FIG. 13 (Japanese Patent Laid-Open No. 3-210683).
Issue). This FIG. 13 is the same as FIG. 2 of the publication, but since there is an error in the mathematical expression for motion analysis, it will be explained again here.

In FIG. 13, this multiplier is M
Although it is composed of an OS transistor, the adder 6 has a ratio of a gate width W and a gate length L (hereinafter referred to as “ability”) (W /
4 MOS transistors (M51, M5) having the same L
2, M53, M54) and a pair of transistors (M51, M54)
52) and two constant current sources I ₀ for driving the corresponding ones of the same (M53, M54), and the first input voltage is applied to both input ends (gates) of one pair of transistors (M51, M52). V ₁ is applied to the other pair of transistors (M5
A second input voltage V ₂ is applied to both input terminals (gates) of M3 and M54.

The first subtractor 7 has the same structure as the adder 6 and includes four MOS transistors (M59, M60, M61, M62) having the same capability (W / L) and a pair of transistors (M59, M60). ) And two constant current sources I ₀ for driving the corresponding ones of the same (M61, M62), but the input mode is slightly different from that of the adder 6. That is, the first input voltage V ₁ is applied to both input terminals (gates) of the paired transistors (M59, M60) (M51, M60).
52) and the second input voltage V ₂ is applied to both input terminals (gates) of the other pair of transistors (M61, M62) in a phase opposite to that of (M53, M54) of the adder 6. Applied in a relationship.

The first squaring circuit 8 drives four MOS transistors (M55, M56, M57, M58) and two corresponding transistors (M57, M58) corresponding to the paired transistors (M55, M56). Although a constant current source I ₀₁ is provided, M55 and M56 and M57 and M58 have different capabilities. Specifically, M55, M56, M57, M58
Ability of W5 / L5, W6 / L6, W7 / L7, W8 /
If L8, then (W6 / L6) / (W5 / L5) = (W
8 / L8) / (W7 / L7) = k (> 1).

In the first squaring circuit 8, M55 and M5
The gate of 8 is connected to the drains of M52 and M54 of the adder 6, and the gates of M56 and M57 are connected to the drains of M51 and M53 of the adder 6.

The second squaring circuit 9 has the same structure as the first squaring circuit 8 and has four MOS transistors (M6).
3, M64, M65, M66) and a pair of transistors (M
63, M64) and two constant current sources I ₀₁ for driving the same ones (M65, M66), and M63 and M6
4, M65 and M66 have different capabilities, and specifically, the relationship is the same as that in the first squaring circuit 8.

In this second squaring circuit 9, M63 and M6
The gate of 6 is connected to the drains of M60 and M62 of the first subtractor 7, and the gates of M64 and M65 are M63 and M6.
5 is connected to the drain of the first subtractor 7
59 and the drain of M61, and further connected to the drain of M56 of the first squaring circuit 8.

Then, M55 and M5 of the first squaring circuit 8
The drain of 7 is connected to the drains of M66 and M64 of the second squaring circuit 9 and constitutes one output end, and the drain of M58 of the first squaring circuit 8 constitutes the other output end. It is an input of the second subtracter 10.

The operation will be described below. In the adder 6, 4
Two MOS transistors (M51, M52, M53, M
54) ability (W1 / L1, W2 / L2, W3 / L3,
Since W4 / L4) are equal, the transconductances are also equal. Therefore, the capability of M51 (W1 / L1)
The transconductance parameter α ₁ using
_{If n} is the mobility and C _OX is the gate oxide film capacitance, α ₁ =
Since (1/2) μ _n C _0x (W1 / L1), the drain currents I _d1 , I _d2 , I _d3 , and I _d4 of M51, M52, M53, and M54 can be expressed by using this formula. It becomes 1.
In Equation 1, V _GSi is a gate-source voltage, and V _TH is a threshold voltage.

[0011]

## EQU1 ## I _d1 = α ₁ (V _GS1 −V _TH ) ² I _d2 = α ₁ (V _GS2 −V _TH ) ² I _d3 = α ₁ (V _GS3 −V _TH ) ² I _d4 = α ₁ (V _GS4- V _TH ) ²

Further, I _d1 + I _d2 = I ₀ , I _d3 + I _d4 = I
₀ , V _GS1 −V _GS2 = V ₁ , V _GS3 −V _GS4 = V ₂ , I _d1 −I _d2 is represented by Formula 2, and I _d3 −I _d4 is Formula 3.
In so represented, the differential output current (I _A -I _B) is Equation 4
Is obtained.

[0013]

## EQU00002 ## I _d1 −I _d2 = α ₁ V ₁ √ {(2I ₀ / α ₁ ) −V ₁ ² }

[0014]

## _EQU00003 ## I _d3 -I _d4 = α ₁ V ₂ √ {(2I ₀ / α ₁ ) -V ₂ ² }

[0015]

## EQU4 ## I _A -I _B = (I _d1 + I _d3 )-(I _d2 + I _d4 ) = (I _d1 -I _d2 ) + (I _d3 -I _d4 ) = α ₁ V ₁ √ {(2I ₀ / α ₁ ) −V ₁ ² } + α ₁ V ₂ √ {(2I ₀ / α ₁ ) −V ₂ ² }

That is, Equations 2 and 3 represent the transfer characteristics of the MOS transistor differential pair, and a differential output current proportional to the input voltage can be obtained at the time of a small signal. Therefore, the differential output current of the adder 6 (I _A -I _B) also,
As can be understood from Expression 4, the two input voltages have an addition characteristic with good linearity when the signal is small. When the adder is used as a subtractor, the second input voltage V
The polarity of ₂ should be reversed.

Therefore, in the first subtractor 7, M59, M
The drain currents of 60, M61 and M62 are I _d11 and I
Assuming _d12 , I _d13 , and I _d14 , the following formulas 5 to 7 are obtained corresponding to formulas 2 to 4.

[0018]

## _EQU00005 ## I _d11 −I _d12 = α ₁ V ₁ √ {(2I ₀ / α
₁₎ -V ₁ ^2}

[0019]

## _EQU6 ## I _d13 −I _d14 = −α ₁ V ₂ √ {(2I ₀ / α
₁₎ -V _{² 2}}

[0020]

## EQU00007 ## I _C -I _D = (I _d11 -I _d13 )-(I _d12 -I _d14 ) = (I _d11 -I _d12 )-(I _d13 -I _d14 ) = α ₁ V ₁ √ {(2I ₀ / α ₁ ) -V ₁₂ ² } -α ₁ V ₂ √ {(2I ₀ / α ₁ ) -V ₂ ² }

Therefore, the differential output voltage V _A of the adder 6 is given by Equation 8, and the differential output voltage V _B of the first subtractor 7 is given by Equation 9. In both equations, R _L is a resistor interposed between each transistor and the power supply V _{DD as} shown in FIG.

[0022]

Equation 8] _{V A = R L (I A} -I B) = R L [α 1 V 1 √ {(2I 0 / α 1) -V 1 2} + α 1 V 2 √ {(2I 0 / α 1 ) -V ₂ ² }]

[0023]

Equation 9] _{V B = R L (I C} -I D) = R L [α 1 V 1 √ {(2I 0 / α 1) -V 1 2} -α 1 V 2 √ {(2I 0 / α ₁₎ -V _{² 2}]}

Next, in the first squaring circuit 8, the pair of transistors (M55, M56) and the pair (M57, M58) have the respective capabilities M55: M56 = M57: M as described above.
Since the ratio of 58 = 1: k, the ability of M55 (W5 /
L5) transconductance parameter α ₂
Using {α ₂ = μ _n (C _OX / 2) (W5 / L5)}, M
If the drain currents I _d5 , I _d6 , I _d7 , and I _d8 of 55, M56, M57, and M58 are expressed, Equation 10 is obtained.

[0025]

[ _Formula 10] I _d5 = α ₂ (V _GS5 −V _TH ) ² I _d6 = kα ₂ (V _GS6 −V _TH ) ² I _d7 = α ₂ (V _GS7 −V _TH ) ² I _d8 = kα ₂ (V _GS8- V _TH ) ²

Further, I _d5 + I _d6 = I ₀₁ , I _d7 + I _d8 =
A _{I 01, V GS5 -V GS6 =} V GS8 -V GS7 = V A,
I _d5 −I _d6 is represented by Formula 11, and I _d7 −I _d8 is represented by Formula 12.
In so represented, the differential output current (I _E -I _F) is Equation 1
Values are found 3 as can be seen in proportion to the square of the input voltage V _A.

[0027]

[Equation 11]

[0028]

(Equation 12)

[0029]

(Equation 13)

The above description is a same in the second squaring circuit 9, a differential output current (I _G -I _H) The formula 14
And is proportional to the input voltage V _B.

[0031]

[Equation 14]

In the second subtractor 10, the two 2
Multiplication circuit of differential output current _{I 1 (= I E -I F} ), the I ₂ (= I _G
Since adding -I _H) in opposite phase, I ₁ -I ₂ is Equation 15 becomes, this V _A of the equation 8 and substituting V _B of Equation 9 and Equation 16. Then, ignoring the square term of the square and V ₂ of V ₁ In Equation 16, I ₁ -I ₂ The formula 17
And the desired multiplier characteristic is obtained.

[0033]

(Equation 15)

[0034]

[Equation 16]

[0035]

[Equation 17]

FIG. 14 shows that R _L = 5 kΩ and I ₀ = 100 μ
A, I ₀₁ = 10 μA, W1 = 20 μ, L1 = 5 μ, W5
= 10μ, L5 = 5μ, k = 5, and C _ox = 320 Å, the simulation results are the same as FIG. 3 of the publication. Although FIG. 14 shows the relationship between the first input voltage V ₁ and the differential output current using the second input voltage V ₂ as a parameter, the same relationship is obtained even if the relationship between V ₁ and V ₂ is exchanged. Simulation results are obtained.

Although FIG. 13 is composed of MOS transistors, an analog multiplier which operates in the same manner can be obtained by replacing it with a bipolar transistor. In this case, the squaring circuit constitutes a differential pair with transistors having different emitter sizes.

[0038]

By the way, as is well known, when a transistor is formed on a semiconductor integrated circuit,
Although there is a minimum unit, and it is desirable to configure with the minimum unit in terms of circuit current, as described above, in the multiplier according to the applicant, the squaring circuit has two differential pairs, Since it is composed of two transistors having different capabilities, it cannot be composed of only the smallest transistor, and there is a problem that the circuit current increases. Further, in this squaring circuit, since each differential pair is provided with a constant current source, two squaring circuits require four constant current sources for convenience, and simplification of the circuit is desired.

The present invention has been made in view of such a problem, and an object thereof is to provide a multiplier capable of simplifying a circuit and reducing current consumption.

[0040]

In order to achieve the above object, the multiplier of the present invention has the following constitution.
That is, in the multiplier of the first aspect of the invention, four transistor pairs whose output terminals are commonly connected are driven by one constant current source; The positive sum voltage is applied to the input ends of the other transistors, and the negative sum voltage of the two signals is applied respectively; the positive phase difference voltage of the two signals multiplied to the input ends of one of the transistors of the second transistor pair is The opposite phase difference voltages of the two signals to be multiplied are applied to the input ends of the other transistors respectively; the input ends of the third and fourth transistor pairs are commonly connected and the DC voltage is applied; the first and third transistor pairs In, the commonly connected output terminals are commonly connected to form one output terminal; and in the second and fourth transistor pairs, the commonly connected output terminals are commonly connected to form the other output terminal; Those characterized by comprising.

The multiplier of the second invention is the multiplier of the first invention; each output terminal of the third and fourth transistor pairs is separated from the output terminal of the multiplier. It is a thing.

Further, in the multiplier of the third invention, two transistor pairs whose output terminals are commonly connected are driven by one constant current source; and the input terminal of one of the transistors of the first transistor pair is multiplied. The positive-phase sum voltage of the two signals is applied to the negative-phase sum voltage of the two signals to be multiplied by the input terminals of the other transistors, respectively. The positive-phase difference of the two signals is multiplied by the input terminals of the one transistor of the second transistor pair. Voltage is applied to the input ends of the other transistors, respectively, and the two signals having opposite phase difference voltages are applied thereto; and the common output ends of the first and second transistor pairs form differential output pairs, respectively. It is characterized by.

[0043]

Next, the operation of the multiplier of the present invention constructed as above will be described. In the present invention, the multiplier is mainly composed of four or two transistor pairs, but since each transistor uses transistors having the same characteristics, it can be constituted by only the minimum number of transistors. Since it is driven by one constant current source, it is possible to provide a multiplier capable of low-voltage operation, simplification of the circuit, and reduction of current consumption. In the second invention, high frequency characteristics can be improved.

[0044]

Embodiments of the present invention will be described below with reference to the drawings. As described above, in the multiplier previously proposed by the applicant, each of the two squaring circuits has the capability (W
There is a problem because it is composed of a pair of transistors having different / L and emitter size) and two constant current sources are required. Therefore, as shown in FIG. 1 (FIG. 3), a multiplier has been developed which drives eight transistors having the same ability by one constant current source.

FIG. 1 shows a multiplier according to the first embodiment of the present invention. This multiplier is composed of bipolar transistors. That is, eight bipolar transistors (Q1, Q2, Q3, Q4, Q5, Q
6, Q7, Q8) are driven by one constant current source I ₀ , but Q1 and Q2, Q3 and Q4, Q5 and Q6, Q7 and Q8
Output terminals (collectors) are commonly connected to each other,
Common connection output terminal (collector) for the first transistor pair (Q1, Q2) and the third transistor pair (Q7, Q8)
The output terminals (collectors) of the second transistor pair (Q5, Q6) and the fourth transistor pair (Q3, Q4) are commonly connected to each other to form one output terminal, and the other output terminal (collector) is commonly connected to the other terminal. Constitutes the output end of.

The third transistor pair (Q7, Q
8) and the fourth transistor pair (Q3, Q4) have their input terminals (bases) connected in common, and the input of one transistor Q1 of the first transistor pair (Q1, Q2) is referred to with this common connection base as a reference. The positive (+) voltage ((1/2) (V ₁ + V) of the two signals (V ₁ , V ₂ ) to be multiplied is applied to the end (base).
_2)} is the input terminal of the other transistor Q2 (the base) reverse phase sum voltage _{{- (1/2) (V 1} + V 2)} are applied respectively. Also, one of the transistors Q5 of the second transistor pair (Q5, Q6) is based on the common connection base.
The positive phase difference voltage {(1/2) (V ₁ −V ₂ )} of the two signals to be multiplied is applied to the input terminal (base) of the same, and the negative phase difference voltage {− (1 / 2) (V ₁ −
V ₂ )} is applied respectively. In short, the DC bias voltage is applied to the common connection base of the transistor pair (Q3, Q4) and the transistor pair (Q7, Q8). This DC bias voltage is a midpoint voltage between the bases of Q1 and Q2, and at the same time, a midpoint voltage between the bases of Q5 and Q6.

In the above structure, the collector current I _Ci of each transistor can be expressed by Equation 18. Note that Equation 18
In, I _S is the saturation current, V _BE is the base-emitter voltage, and V _T is the thermal voltage. V _T is the Boltzmann constant k, the absolute temperature T, and the unit electronic charge q, and V _T = kT
/ Q.

[0048]

I _C1 = I _S exp [{V _BE3 + (1/2) (V ₁
+ V ₂ )} / V _T ] I _C2 = I _S exp [{V _BE3 − (1/2) (V ₁ + V ₂ )} /
V _T ] I _C3 = I _C4 = I _C7 = I _C8 = I _S exp (V _BE3 / V _T ) I _C5 = I _S exp [{V _BE3 + (1/2) (V ₁ −V ₂ )} /
V _T ] I _C6 = I _S exp [{V _BE3 − (1/2) (V ₁ −V ₂ )} /
V _T ]

When α _F is a DC amplification factor, I _C1 + I
_{Since C2} + I _C3 + I _C4 + I _C5 + I _C6 + I _C7 + I _C8 = α _F I ₀ , α _F I ₀ can be obtained by Equation 19, and I _C3 can be obtained by Equation 2
It becomes like 0.

[0050]

[Formula 19]

[0051]

(Equation 20)

Therefore, the differential output current ΔI is expressed by the equation 21, but since coshx ≧ 1, in the equation 21, cosh
When (V ₁ / 2V _T ) cosh (V ₂ / 2V _T ) ≧ 1 is satisfied, the denominator +1 can be ignored and the differential output current ΔI can be approximated by Formula 22.

[0053]

[Equation 21]

[0054]

## EQU22 ## ΔI≈α _F I ₀ tanh (V ₁ / 2V _T ) tanh (V ₂ / 2V _T ) where | V ₁ |, | V ₂ | ≧ 2V _T

The right side of the equation 22 is 1 / α _F of the equation showing the transfer characteristic of the Gilbert multiplier. Therefore, from the equation (21), the circuit shown in FIG. 1 has a multiplier characteristic.

However, in Expression 21, since the denominator has a term of "+1", it is considered that the deviation from the characteristic of the Gilbert multiplier becomes large in the input voltage range of | V ₁ |, | V ₂ | << 2V _T. . However, since the output current at the small signal input is reduced by the term "+1", the nonlinearity rather increases smoothly as a multiplier characteristic, and the characteristic is improved over the Gilbert multiplier. is there.

FIG. 2 shows the transfer curve obtained from the equation 21, which shows that the linearity is improved as compared with the Gilbert multiplier and that it has a limiting characteristic when a large signal is input.

Next, FIG. 3 shows a multiplier according to the second embodiment of the present invention. This multiplier consists of eight MOS transistors (M1, M2, M3, M) with the same capability.
4, M5, M6, M7, M8) are driven by one constant current source I ₀ , and the connection relationship is the same as in the case of FIG.

That is, eight MOS transistors (M1,
M2, M3, M4, M5, M6, M7, M8) are driven by one constant current source I ₀ , but M1 and M2, M3 and M
4, M5 and M6, M7 and M8 have their output terminals (drains) commonly connected to each other, and have a first transistor pair (M
1, M2) and the third transistor pair (M7, M8) have their commonly connected output terminals (drains) commonly connected to form one output terminal, and the second transistor pair (M5, Q8).
In 6) and the fourth transistor pair (Q3, Q4), the commonly connected output terminals (collectors) are commonly connected to form the other output terminal.

The third transistor pair (M7, M
8) and the fourth transistor pair (M3, M4) have their input terminals (bases) connected in common, and the input of one transistor M1 of the first transistor pair (M1, M2) is referred to with this common connection base as a reference. Multiply 2 at the end (gate)
Positive phase sum voltage of signals (V ₁ , V ₂ ) {(1/2) (V ₁ + V
_2)} is the input terminal of the other transistor M2 (gate) reverse phase sum voltage _{{- (1/2) (V 1} + V 2)} are applied respectively. Also, based on the common connection base, the second
The positive phase difference voltage {(1/2) (V ₁ −V ₂ )} of two signals to be multiplied is applied to the input end (gate) of one transistor M5 of the transistor pair (M5, M6) of the other transistor M5.
The negative phase difference voltage {-(1/2) (V
_1- V ₂ )} is applied respectively. In short, transistor pair (M3, M4) and transistor pair (M7, M
The DC bias voltage is applied to the common connection base with 8).

In FIG. 3, assuming that each MOS transistor has the same capability characteristics, and that all MOS transistors are operating in the saturation region, and the square law is established, the drain of each MOS transistor The current I _Di can be expressed by Equation 23. Note that in Equation 23,
The transconductance parameter is β.

[0062]

[ _Equation 23] I _Di = β (V _GSi −V _TH ) ²

Therefore, the drain current I _Di of each MOS transistor in FIG.

[0064]

I _D1 = β {V _GS3 + (1/2) (V ₁ + V ₂ ) −V _TH } ² I _D2 = β {V _GS3 − (1/2) (V ₁ + V ₂ ) −V _TH } ² I _D3 = I _D4 = I _D7 = I _D8 = β (V _GS3 −V _TH ) ² I _D5 = β {V _GS3 + (1/2) (V ₁ −V ₂ ) −V _TH } ² I _D6 = Β {V _GS3 − (1/2) (V ₁ −V ₂ ) −V _TH } ²

Further, I _D1 + I _D2 + I _D3 + I _D4 + I _D5 + I
_D6 + I _D7 + I _D8 = I ₀ . Therefore, the differential output current Δ
I becomes Equation 25.

[0066]

(Equation 25)

FIG. 4 shows the transfer characteristics expressed by the equation 25 using V ₂ as a parameter. From FIG. 4, it can be understood that an ideal multiplier can be obtained if the square law of the MOS transistor is established. It is also shown to have limiting characteristics for large signal inputs.

Next, FIG. 5 shows a multiplier according to the third embodiment of the present invention. This multiplier is the third transistor pair (Q7, Q) in the first embodiment (FIG. 1).
8) and the output terminal of the fourth transistor pair (Q3, Q4) is disconnected from the output terminal of the multiplier, and the power supply voltage V _CC
Is applied.

Since the emitters and the bases of the transistors Q3, Q4, Q7, and Q8 are commonly connected, the collector currents I _C3 ,
The same I _C4 , the same I _C7 , and the same I _C8 are all the same, and as can be understood from Expression 21, in terms of the differential output current, (I _C3 + I
_C4 ) and (I _C7 + I _C8 ) cancel each other out. Therefore, these 4
The collector current of one transistor can be decoupled from the differential output current of the multi-bryer.

In this case, since the number of transistors connected to each terminal forming the differential output terminal of the multiplier is halved, the collector capacitance is halved and the frequency characteristic is improved to about twice. .

The same thing can be applied to the multiplier of the second embodiment (FIG. 3), and as shown in FIG.
The drains of the transistors (M7, M8) and the fourth transistors (M3, M4) can be separated from the output terminal of the multiplier and connected to the power supply voltage V _DD .

Next, FIG. 7 shows a multiplier according to the fifth embodiment of the present invention. This multiplier consists of four bipolar transistors (Q1, Q2,
Q3, Q4) is driven by one constant current source I ₀ ,
Two transistor pairs (Q3, Q4 and Q in FIG.
7 and Q8), and the connection relationship is the same as in the case of FIG. Originally, the two transistor pairs (Q3, Q4 and Q7, Q8) in FIG. 1 have the same bias condition, and when the differential output current is obtained, the respective collector currents are subtracted and canceled. The basic operation does not change even if two transistor pairs (Q3, Q4 and Q7, Q8) are removed.

Assuming that the matching between the elements is good, and ignoring the base width modulation, the collector current of each transistor is expressed by equation (26).

[0074]

(Equation 26)

If α _F is a direct current amplification factor, I
_{Since C1} + I _C2 + I _C3 + I _C4 = α _F I ₀ , α _F I ₀
Is calculated as Equation 27.

[0076]

[Equation 27]

Therefore, the differential output current ΔI is given by equation 28.

[0078]

[Equation 28]

The right side of the equation 28 is 1 / α _F of the equation showing the transfer characteristic of the Gilbert multiplier. Therefore, the circuit shown in FIG. 7 has a multiplier characteristic. However, in Expression 28, since α _F is applied only in the first order, it can be seen that the PN junction has only one stage. That is, since the transistors are not vertically stacked, the power supply voltage can be lowered by one stage of the PN junction as compared with the Gilbert multiplier. Actually, since it is not necessary to consider the input voltage amplitude for each of the two input signal voltages, the power supply voltage can be reduced by about 1V. In FIG.
28 shows a transfer curve obtained from Expression 28. α _F
If is 1, it is equal to Gilbert Multiplier.

Next, FIG. 9 shows a multiplier according to the sixth embodiment of the present invention. This multiplier consists of four MOS transistors (M1, M2, M3,
M4) is driven by one constant current source I ₀ , and two transistor pairs (M3, M4 and M7, M in FIG. 3 are used.
8) is excluded, and the connection relationship is the same as in the case of FIG. Originally, the two transistor pairs (M3, M4 and M7, M8) in FIG. 3 all have the same bias condition, and when the differential output current is obtained, the respective drain currents are subtracted and canceled. The basic operation does not change even if two transistor pairs (M3, M4 and M7, M8) are removed.

It is assumed that the matching between the elements is good, the gate width modulation and the substrate effect are ignored, and the MO operating in the saturation region is operated.
Assuming that the relationship between the drain current of the S transistor and the gate-source voltage follows the square law, each M in FIG.
The drain current I _Di of the OS transistor is given by Formula 29.

[0082]

[Equation 29]

Further, I _D1 + I _D2 + I _D3 + I _D4 = I ₀ . Therefore, the differential output current ΔI is given by Equation 30.

[0084]

[Equation 30]

FIG. 10 shows the transfer characteristic expressed by the equation 30 with V ₂ as a parameter.
From FIG. 10, similarly, it can be understood that an ideal multiplier can be obtained if the square law of the MOS transistor is established. It is also shown to have limiting characteristics for large signals.

In the case of the bipolar multiplier shown in FIGS. 1, 5 and 7, a method of inserting an emitter resistor may be considered for the purpose of expanding the input voltage range. As a method of inserting the emitter resistance, in addition to the method of inserting one into each transistor, a method of sharing the emitter resistance in a pair of transistors whose collectors are commonly connected can be considered. When the emitter resistance is inserted in the differential pair, the transfer characteristic becomes relatively similar to the transfer characteristic of the MOS differential pair, but it is said that the input voltage range of the bipolar multiplier can be expanded by optimizing the emitter degeneration value. There is no end.

In addition, in FIG. 1, FIG. 3, FIG. 7 and FIG.
The sum voltage and the difference voltage of the two signals can be obtained as follows. That is, the difference voltage (V ₁ −V ₂ ) between the two signals is obtained by applying V ₁ to one of the differential input pairs of the differential amplifier and V ₂ to the other. The sum voltage (V ₁ + V ₂ ) is
The resulting reverse-phase voltage -V ₂ of V ₂ to the negative-phase output of the output or the differential amplifier of the inverting amplifier, obtained by applying the V ₁ and the reverse-phase voltage -V ₂ to the respective terminals of the differential input pair To be

When the sum voltage and the difference voltage of the two signals are obtained as the differential output of the differential amplifier as described above, two resistors having the same value are connected in series between the differential output terminals and inserted. For example, since the midpoint voltage of two signals is obtained at the connection point of the two resistors, this may be used as the DC bias voltage of the common connection input terminal.

Further, as a method of constructing the other two-signal adder / subtractor, the conventional circuit shown in FIG. 13 or the IEEE Journ
al of Solid-State Circuits, VOL, SC-22, NO.6, pp.1064-
The circuits shown in FIGS. 11 and 12 disclosed in FIGS. 2 and 4 of 1073, Dec. 1987. (or US patent 4,546,275) can be used.

[0090]

As described above, according to the multiplier of the present invention, four or two transistor pairs using transistors having the same characteristics are driven by one constant current source. It is possible to provide a multiplier that can be configured with only a minimum unit of transistors, can operate at a low voltage, can simplify the circuit, reduce current consumption, and can improve high-frequency characteristics.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a multiplier according to a first embodiment of the present invention.

2 is an input / output characteristic diagram of the multiplier shown in FIG.

FIG. 3 is a circuit diagram of a multiplier according to a second embodiment of the present invention.

FIG. 4 is an input / output characteristic diagram of the multiplier shown in FIG.

FIG. 5 is a circuit diagram of a multiplier according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a multiplier according to a fourth exemplary embodiment of the present invention.

FIG. 7 is a circuit diagram of a multiplier according to a fifth exemplary embodiment of the present invention.

8 is an input / output characteristic diagram of the multiplier shown in FIG.

FIG. 9 is a circuit diagram of a multiplier according to a sixth embodiment of the present invention.

10 is an input / output characteristic diagram of the multiplier shown in FIG.

FIG. 11 is a circuit diagram of an example of an adder circuit.

FIG. 12 is a circuit diagram of another example of the adder circuit.

FIG. 13 is a configuration block diagram of a multiplier proposed in the applicant's earlier application.

FIG. 14 is an input / output characteristic diagram of the multiplier proposed in the applicant's earlier application.

[Explanation of symbols]

I ₀ constant current source M1 to M8 MOS transistor Q1 to Q8 bipolar transistor V ₁ input voltage V ₂ input voltage V _CC power supply voltage V _DD power supply voltage

Claims (4)

(57) [Claims] 1. A constant current source drives four transistor pairs of which output terminals are commonly connected; a positive-sum voltage of two signals multiplied by an input terminal of one transistor of the first transistor pair; , The opposite-phase sum voltage of two signals to be multiplied is applied to the input terminal of the other transistor; the positive-phase difference voltage of two signals to be multiplied to the input terminal of one transistor of the second transistor pair is the input of the other transistor The opposite phase difference voltages of the two signals to be multiplied are applied respectively to the terminals; the input terminals are commonly connected to the third and fourth transistor pairs, and the DC voltage is applied; and the common connection output terminals are applied to the first and third transistor pairs. The two transistors are commonly connected to form one output end; and the second and fourth transistor pairs are commonly connected to each other to form the other output end; Multiplier. 2. The multiplier according to claim 1, wherein the output terminals of each of the third and fourth transistor pairs are separated from the output terminal of the multiplier. 3. The multiplier according to claim 1 or 2, wherein the DC voltage is a midpoint voltage between both input terminals of the first and second transistors, respectively.
Multiplier characterized by that. 4. Two of the transistor pairs whose output terminals are commonly connected are driven by one constant current source; and the positive-sum voltage of two signals multiplied by the input terminal of one transistor of the first transistor pair is , The opposite-phase sum voltage of two signals to be multiplied is applied to the input terminal of the other transistor; the positive-phase difference voltage of two signals to be multiplied to the input terminal of one transistor of the second transistor pair is the input of the other transistor 2. A multiplier, characterized in that opposite phase difference voltages of two signals to be multiplied are respectively applied to the ends; and the common output ends of the first and second transistor pairs form a differential output pair.