JP2616470B2 - Multiplier core circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier core circuit for multiplying two analog signals, and more particularly to a low voltage operable multiplier core circuit formed on a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A multiplier for multiplying two signal values is an indispensable function block in analog signal processing. 2. Description of the Related Art Conventionally used multipliers include those configured by two transistors using the square characteristic of a MOS transistor. That is, assuming that input voltages are a and b, the linear operation of the multiplier is expressed by the following algebraic equation. (A + b) ^2- (ab) ² = 4ab (1) As described above, a method of obtaining a multiplier based on a linear function defined by two square differences is known as a quarter-square technique. .

The drain current of a MOS transistor operating in the saturation region is expressed by the following equation if channel length modulation and the body effect are neglected. I _Di = β (V _GSi −V _TH ) ² (V _GSi > = V _TH ) (2a) I _Di = 0 (V _GSi ≦ V _TH ) (2b) where β = μ (C _OX / 2) (W / L) is a transconductance parameter, μ is effective mobility of carrier, C _OX is gate oxide film capacity per unit area,
W and L represent a gate width and a gate length, respectively. V _GSi represents a gate-source voltage, and V _TH represents a threshold voltage. in this way,
Since the threshold voltage is added to the parameters in the drain current characteristic of the MOS transistor, (1)
When the circuit corresponding to the equation is constituted by MOS transistors, the effect of the threshold voltage is not eliminated.

Therefore, in order to eliminate this, an unnecessary parameter c is further added, and two linear functions expressed by the following equation using the sum and difference of four squares including the parameter are defined. ing. ^{(A + b + c) 2} - (a-b + c) 2 + (a + b-c) 2 - (a-b-c) 2 = 8ab (3) (a + b) 2 - (a-c) 2 + (a + b-c) 2 − (Ab−c) ² = 4ab (4) The multipliers corresponding to these linear functions are four M
It can be realized using an OS transistor.

FIG. 13 shows a configuration of a multiplier core circuit in which an input is floated using a quadritail cell. The sources of the first to fourth MOS transistors 101 to 104 are commonly connected to each other, and are grounded via a constant current source 105. First M
OS transistor 101 and second MOS transistor 1
02 and the drains of the third MOS transistor 103 and the fourth MOS transistor 104 are commonly connected. The sum of the drain currents of the two MOS transistors is obtained by the common connection. The drain current I _R 1 from the drain current I _L 106
07 is output as a differential output current. If all of the four transistors constituting the multiplier core circuit are used in an input voltage range that does not cut off, each transistor operates according to the square law shown in the equation (2a). Therefore, an operation corresponding to the linear functions shown in the equations (3) and (4) can be obtained by the illustrated circuit.

FIG. 14 shows four MOS transistors grounded at the source.
This shows the configuration of a multiplier core circuit using transistors. The same reference numerals are given to the same parts as those in FIG. This multiplier core circuit is different from the one shown in FIG.
To the fourth MOS transistors 101 to 104 are grounded at the source. In this circuit, I _L 1
The difference from 06 to I _R 107 is output as a differential output current, and a multiplier corresponding to the linear function of equation (3) or (4) can be realized.

The differential output current ΔI / β of the multiplier core circuit shown in FIG. 13 or FIG. 14 is expressed by the following equation in an input voltage range where none of the transistors in the circuit is cut off. _{ΔI / β = (V 1 +} V R -V S -V TH) 2 + (V 2 + V R -V S -V TH) 2 - (V 3 + V R -V S -V TH) 2 - (V 4 + V ^{_{R -V S -V TH) 2 =}} V 1 2 + V 2 2 -V 3 2 -V 4 2 + 2c (V 1 + V 2 -V 3 -V 4) (5) However, c = V _R -V _S - V _TH, the V _R DC voltage of the input signal, V _S is the common source voltage, in the case of Figure 14 the source of which is grounded, V _S is "0". In FIG. 13, since the tail current is common, the condition expressed by the following equation is satisfied. I _D1 + I _D2 + I _D3 + I _D4 = I ₀ (6) The following relationship is established for a combination of input voltages that eliminates the term c. V ₁ + V ₂ −V ₃ −V ₄ = 0 (7) Therefore, the expression (5) becomes as follows. ^{_{ΔI / β = V 1 2 +}} V 2 2 -V 3 2 -V 4 2 = (V 1 -V 4) (V 1 + V 4 -V 2 -V 3) (8)

[0008] Heretofore, there are two types of input voltage combination methods in which the characteristics of the differential output current are linearized, the first type proposed by Bult and Wallinga, and the one proposed by Balt. A second type is known, which was re-proposed by Wang and Schaumann. The circuit proposed by Balt et al. Is IEEE Journ
al of Solid-State Circuits, Vol.SC-21, No.3 pp430-43
5, June 1986. Also, the circuit proposed by Balt is disclosed in his Ph, D and dissertation, but has been re-proposed by Wang et al. And is easily available. Wang's re-proposed circuit is the IEE Electron letters, 18th Jan.1
990, Vol.26, No.9. In addition, Wu
The circuit re-proposed by Stuman was an IEE Electron let
ters, 4th July 1991, Vol. 27, No. 14.
The relationship of the input voltage in the first type is represented by the following equation. _{(V 1, V 2, V} 3, V 4) = {(V X + V Y) / 2, - (V X + V Y) / 2, - (V X -V Y) / 2, (V X -V _Y ) / 2｝ (9) Further, the relationship of the input voltage in the second type is represented by the following equation. _{(V 1, V 2, V} 3, V 4) = {V X / 2, -V X / 2 + V Y, V X / 2-V Y, -V X / 2} (10)

FIG. 15 shows a configuration of a first type of multiplier core circuit in which an input is floating and a combination of input voltages thereof. The same reference numerals are given to the same circuit portions as those in FIG. By adjusting the DC voltage V _R of the input signal, each transistor is operated within a range not to cut off.

FIG. 16 shows that four transistors are connected to the source.
Grounded first type of multiplier core circuit
And the combination of the input voltage
It is. The first type of input shown in FIGS.
Each combination of force and voltage is (V₁, V_Two, V_Three,
V_Four) = (A + b, -ab, -a + b, ab)
This is a relation corresponding to the equation (3). these
Substituting into equation (8) gives V₁-V_Four= 2b, V₁+ V_Four
-V_Two-V_Three= 4a (where V₁+ V_Four= -V _Two-V
_Three= 2a), and ΔI / β = 8ab is obtained. This
Thus, the two voltage signals to be multiplied are of the first type
Convert to the combined four voltage signals and
Unnecessary parameters by inputting to each transistor of the
Data c to obtain a multiplier with linear characteristics.
Can be.

FIG. 17 shows that the input is floating.
Of a second type of multiplier core circuit
And the combination of the input voltages. Times
The configuration of the road is the same as that shown in FIG. Input voltage
Is to convert the two voltage signals to be multiplied to V_X, V
_YThen V_X/ 2, -V_X/ 2 + V_Y, V_X/ 2-
V_Y, -V_X/ 2. Also in this circuit,
DC voltage V of input signal _RBy adjusting the
Stars operate within the range that does not cut off
I have.

FIG. 18 shows that four transistors are connected to the source.
Grounded second type of multiplier core circuit
And the combination of the input voltage
It is. The second type of input shown in FIG. 17 and FIG.
Each combination of force and voltage is (V₁, V_Two, V_Three,
V_Four) = (A, -ab, ab, -a)
That is, the relationship corresponds to the expression (4). These are given by equation (8)
Substituting into₁-V _Four= 2a, V₁+ V_Four-V_Two−
V_Three= 2b (where V₁+ V_Four= -V_Two-V_Three= 2
a), and ΔI / β = 4ab is obtained. in this way,
Two input voltages to be a combination of the second type
Is converted to each transistor of the multiplier core circuit.
Multiplier with linear characteristics by applying
Can be obtained.

When the four transistors are grounded at the source, the input voltage range can be widened, and the circuit current can flow until it is restricted by factors such as the internal resistance of the transistors. On the other hand, when four transistors are driven by a constant current source, the circuit current is set by the tail current,
The input voltage range is limited by this tail current. However, in the case of realizing an LSI, it is desirable to employ a floating input and a constant current drive which can avoid the influence of manufacturing variations.

FIG. 19 shows four bipolar transistors.
Configuration of multiplier core circuit composed of
Is expressed. First to fourth bipolar tigers
The emitters of the transistors 111 to 114 are commonly connected to each other.
After that, it is grounded via a constant current source 115. Ma
In addition, the first bipolar transistor 111 and the second
The collectors of the bipolar transistors 112 are commonly connected.
And their collector currents are added to produce an output current I_L1
It is 16. On the other hand, the third bipolar transistor
Of the transistor 113 and the fourth bipolar transistor 114.
The collectors are also connected in common, and their collector currents are added.
Output current I_R117. I _LTo I_RTo
The subtracted differential output current is used for the multiplier core circuit.
Output current. First to fourth bipolar tigers
The bases of the transistors 111 to 114
The voltage value after converting the pressure into a predetermined combination is applied.
It has become so.

The relationship between the collector current and the base-emitter voltage of a bipolar transistor is expressed by the following equation, assuming that it follows an exponential law.

(Equation 1)Where V_BEiIs the base-emitter voltage, I_SIs saturated
It is a current. V_TIs the thermal voltage, V_T= Q / kT and table
Be forgotten. Where q is unit electron charge and k is Boltzmann
The constant, T, is the absolute temperature. Base-emitter voltage V
_BEiIs about 600 mV during normal operation of the transistor.
In other words, the exponent part exp (V _BEi/ V_T) Is
Since the value is about 10th power, the term "-1" can be ignored.
You. Therefore, equation (11) can be expressed as
Can be.

(Equation 2)

[0016] In this case, the collector currents of the transistors of the bipolar quadritail cell shown in FIG. 16 driven by the tail current I _EE is expressed by the assumed and equation as a good consistency between elements.

(Equation 3) However, the V _R DC voltage component of the input signal, V _E is a common emitter voltage. In addition, since the motor is driven by the common tail current by the constant current source, the following conditional expression is satisfied. I _C1 + I _C2 + I _C3 + I _C4 = α _F I ₀ (17) where α _F is a DC current gain of the transistor.

Solving equations (14) to (18) gives the following equation.

(Equation 4) Accordingly, the differential output current ΔI of the bipolar quadritail cell is obtained by the following equation.

(Equation 5)

FIG. 20 shows a state in which the input voltage of the first type combination is applied to the multiplier core circuit using the bipolar quadrature cell. The same circuit portions as those in FIG. 19 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The input is floating by being driven by the constant current source 115. V ₁ was _{(V X + V Y) /} 2, V 2 is - (V _X + V
_Y) / 2, V ₃ is _{- (V X -V Y) /} 2 and V _4, is _{(V X -V Y) / 2} . By substituting these into equation (19), the differential output current ΔI of the bipolar quadritail cell is expressed by the following equation.

(Equation 6) Multiplying the right-hand side of this equation by α _F gives the well-known Gilbert multiplier c
ell) of the differential output current. In a typical bipolar process, α _F is between 0.98 and
0.99, which is almost a value close to “1”.
Therefore, by converting the input voltage into such a combination and applying it to each transistor of the bipolar quadritail cell, it is possible to obtain a multiplier core circuit having almost the same transfer characteristics as the Gilbert multiplier cell. . However, compared to the Gilbert multiplier cell, since the transistors are not stacked vertically, operation at a low voltage is possible. In the case of a bipolar transistor, if the emitter is grounded, it will not operate as a multiplier core circuit. The differential output current ΔI when the emitter is grounded is expressed by the following equation.

(Equation 7) However, it is _{I 0 = I S exp (V} R / V T).

FIG. 21 shows a bipolar quadrilateral cell.
The second type of set in the multiplier core circuit by
It shows the state when the combined input voltage is applied.
It is. The same circuit parts as those in FIG.
The description is omitted as appropriate. V₁Is V_X/ 2, V_TwoIs
-V_X/ 2-V_Y, V_ThreeIs V_X/ 2-V_YAnd V _Four
Is -V_X/ 2. Substitute these into equation (19)
And the differential output current Δ of the bipolar quadritail cell
I is represented by the following equation.

(Equation 8) By multiplying the right side of this equation by α _F , it becomes equal to the one expressing the differential output current of the Gilbert multiplier cell as in the case of FIG. Therefore, it can be operated as a multiplier core circuit. However, the differential output current ΔI when the emitter is grounded is expressed by the following equation.

(Equation 9) In this case, the transmission characteristics cannot be called a multiplier core circuit.

[0020]

In recent years, the process has become finer, and accordingly, the power supply voltage of the LSI has been lowered from 5 V to about 3.3 V or about 3 V. Furthermore, it has been widely accepted that the CMOS process is the most suitable process technology for LSI integration.
There is a demand for a circuit for realizing a multiplier in a process. A conventional multiplier using a Gilbert multiplier cell cannot be operated at a low voltage because a large number of transistors are stacked vertically. On the other hand, in a multiplier core circuit using four transistors, transistors are not stacked vertically and can be operated at a low voltage. However, the combination of the first and second types of voltages proposed at present has a large circuit scale for converting two voltage signals to be multiplied into four voltage signals, and the circuit as a whole multiplier is required. There is a problem that the configuration is complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiplier core circuit having a linear characteristic by a new combination of input voltages and capable of operating at a low voltage.

[0022]

According to the first aspect of the present invention, a sum signal of a reverse phase signal of the first voltage signal and a voltage signal having half the magnitude of the second voltage signal is input to its gate or base. And the sum signal of the first voltage signal and the second voltage signal is input to its gate or base, and its drain or collector is commonly connected to the drain or collector of the first transistor. A second transistor, a third transistor having a gate or a base to which a sum signal of the opposite phase signal of the first voltage signal and the second voltage signal is input, and a first voltage signal and a second voltage signal The sum signal of the voltage signal of half the magnitude of is input to its gate or base,
A fourth core transistor having its drain or collector commonly connected to the drain or collector of the third transistor, and a constant current source for driving the first to fourth transistors with a common tail current are provided in the multiplier core circuit. I have it.

That is, according to the first aspect of the present invention, the first voltage signal to be multiplied is V _X , and the second voltage signal is V V
_Assuming that _Y , the first transistor has −V _X + V _Y /
2, the voltage of the second transistor V _X + V _Y are respectively applied. Further, the third transistor has-
V _X + V _Y, the voltage of V _X + V _Y / 2 are respectively applied to the fourth transistor. By converting the input voltage to such a combination and applying it to each transistor of the multiplier core circuit, a multiplier having a linear characteristic in which the influence of the threshold voltage is eliminated can be obtained. Also, by driving the four transistors with a common tail current, the inputs can be floated and the multiplier core circuit can have limiting characteristics.

According to the second aspect of the present invention, the sum signal of the opposite phase signal of the first voltage signal and the voltage signal having half the magnitude of the second voltage signal is input to its gate and the first source is grounded. And a second MOS transistor having a gate to which a sum signal of the first voltage signal and the second voltage signal is input and grounded at the source, and having a drain commonly connected to a drain of the first MOS transistor A transistor; a third MOS transistor having a gate to which a sum signal of a reverse phase signal of the first voltage signal and a second voltage signal is input and grounded to a source; a first voltage signal and a second voltage signal A fourth MOS transistor having a gate connected to a gate of a sum signal of voltage signals having a magnitude of half of that of the fourth MOS transistor and having a drain commonly connected to a drain of the third MOS transistor And it is provided with a transistor in multiplier core circuit.

That is, according to the second aspect of the present invention, the first voltage signal to be multiplied is V _X , and the second voltage signal is V
_{Assuming Y} , the first MOS transistor has −V _X + V
A voltage of V _X + V _Y is applied to _Y / 2 and the second MOS transistor, respectively. Further, the third MOS transistor is -V _X + V _Y, the fourth MOS transistor voltage V _X + V _Y / 2 in is applied, respectively. By converting the input voltage into such a combination and applying it to each MOS transistor of the multiplier core circuit, a multiplier having a linear characteristic in which the influence of the threshold voltage is eliminated can be obtained. Also,
Since the source is grounded, a constant current source becomes unnecessary. Further, the circuit current can flow until it is limited by factors such as the internal resistance of the MOS transistor, and the input voltage range can be widened.

According to the third aspect of the present invention, the sum signal of the opposite phase signal of the first voltage signal and the voltage signal of half the magnitude of the second voltage signal is input to its gate and the first source is grounded. And a sum signal of the first voltage signal and the second voltage signal is input to its gate and grounded, and its drain is commonly connected to the drain of the first field effect transistor. A second field-effect transistor, a signal having a reverse phase to the first voltage signal, and a second signal;
A third field effect transistor whose gate is input to the gate thereof and whose source is grounded, and a sum signal of a voltage signal having half the magnitude of the first voltage signal and the second voltage signal are the same. The multiplier core circuit has a fourth field-effect transistor having a gate input and a source grounded, and a drain commonly connected to the drain of the third field-effect transistor.

That is, according to the third aspect of the present invention, the multiplication
The first voltage signal of interest is V_X, The second voltage signal to V
_YThen, the first field-effect transistor has -V_X
+ V _Y/ 2, V for the second field-effect transistor_X+
V_YAre applied respectively. In addition, the third
-V for a field effect transistor_X+ V_Y, The fourth electric field
V for effect type transistors_X+ V_Y/ 2 voltage
Is applied. Input voltage to such a combination
Convert and convert each field-effect transformer in the multiplier core circuit.
The threshold voltage
To obtain a multiplier with linear characteristics eliminating the effects of
Can be. Also, since the source is grounded, the constant current source
Becomes unnecessary. The circuit current is controlled by a field-effect transistor.
Flow until it is limited by factors such as the internal resistance of the
Therefore, the input voltage range can be widened.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows the configuration of a multiplier core circuit according to an embodiment of the present invention. First to first
The fourth MOS transistors 11 to 14 are grounded via a constant current source 15 after their sources are commonly connected. The drain of the first and second MOS transistors 11 and 12 are commonly connected, as an output current I _L 16 and the drain current is added. Also, the third and fourth M
The drains of the OS transistors 13 and 14 are also commonly connected, and their drain currents are added to form an output current I _R 17. Differential output current Δ obtained by subtracting I _R from I _L
I is the output current of the multiplier core circuit.

The voltage of the input signal to be multiplied is V_X, V
_Y, The gate of the first MOS transistor 11
In addition, a peripheral circuit (not shown)_X+ V_Y/ 2 is added
Can be obtained. Second MOS transistor
12 gates have V_X+ V _YCan be added
ing. Similarly, the third MOS transistor 13 has-
V_X+ V_YIs applied to the fourth MOS transistor 14
Is V_X+ V_Y/ 2 voltage is applied respectively
Has become.

By the way, 4 including unnecessary parameter c
Using the sum and difference of the two squares, define a linear function such as
Can be justified. (-A + b / 2-c)^Two+ (A + bc)^Two-(-A + bc)^Two− (A + b / 2−c)^Two= 2ab (24) In this case, the combination of input voltages is (V₁, V_Two,
V_Three, V_Four) = (− A + b / 2, a + b, −a + b, a
+ B / 2). Substitute this into equation (8)
And V₁-V_Four= -2a, V₁+ V_Four-V_Two-V_Three= −
b (however, V₁+ V _Four= B, V_Two+ V_Three= 2b)
ΔI / β = 2ab. The relationship between these four voltages
The person in charge of each of the multiplier core circuits shown in FIG.
Corresponds to the voltage applied to the MOS transistor
I do. Therefore, such a combination of voltages
Even if the multiplier with unnecessary parameter c is deleted,
Can be formed.

The drain current of each transistor in the quad tail cell shown in FIG. 1 and composed of four transistors driven by a common tail current is expressed by the following equation.

(Equation 10) However, the V _R DC voltage of the input signal, the V _S is the common source voltage. The following equation is established from the condition of the tail current. I _D1 + I _D2 + I _D3 + I _D4 = I ₀ (29)

The differential output current ΔI of the MOS 4-quadrant analog multiplier is represented by the following equation.

[Equation 11]

Equation (30) is equal to the transfer characteristic of the multiplier proposed by Balt and Waringer and the transfer characteristic of one of the re-proposed multipliers. Also, M
Assuming the square law of the OS transistor, four MOS transistors
In the input voltage range in which none of the transistors are cut off (the range of the expression 30a), ideal multiplier characteristics can be obtained. As the input voltage increases, the MOS transistors in the circuit begin to cut off,
The characteristics gradually deviate from the characteristics of the ideal multiplier.

FIG. 2 shows the transfer characteristics of the multiplier core circuit according to the combination of the input voltages shown in FIG. This represents the transfer characteristic based on equation (30), using V _Y as a parameter. From this figure, it can be seen that the tailor current causes the multiplier core circuit to have limiting characteristics for large signal inputs.

The transconductance characteristic of the multiplier can be obtained by differentiating the equation (30). The following equation shows the result of differentiating the differential output current ΔI with V _X.

(Equation 12)

FIG. 3 shows the transconductance characteristics of the multiplier. This is obtained based on the equation (31). Also, V _Y is represented as a parameter. This is within the range V _X is given as the transconductance characteristic is in a fully flat, it can be seen that the relation between the input voltage and the output current has a linear characteristic which is linearized. Further, it can be seen that with equal transconductance characteristics for any V _X, V _Y.

FIG. 4 shows the multiplier code shown in FIG.
A Multiplier whole circuit with input circuit added to circuit
It shows the configuration. In this circuit, the input voltage V
_YIs converted to half the size by the circuit portion 21
It has become. Input voltage V reduced by half_YIs a tiger
Via the transistors 22, 23, 24, 25
Pressure V_XIs added to the signal of the multiplier core circuit 26.
The gate of transistor 27 has V_X+ V_Y/ 2 voltage is marked
To be added. Also, the transistor 22,
Inputs from the transistor 32 through 28, 29 and 31
Force voltage -V_XAnd the gate of the transistor 33
And -V_X+ V_Y/ 2 voltage is applied
I have. Similarly, the input voltage V_YAre transistors 35, 3
6, 37 and 38, the input voltage V_XIs added to
V at the gate of transistor 39_X+ V_YVoltage is applied
Have been. Also, transistors 35, 41, 42, 32
The input voltage −V_XIs added to the transistor
-V at the gate of 43_X+ V _YVoltage is applied
It has become. In this circuit, an input addition circuit is configured
The number of differential pairs increases, and the current consumption increases. ,Also,
V_YBy the circuit part 21 for halving
Transistors are stacked vertically. For this reason, about 3 volts
Operating voltage is required.

FIG. 5 shows a normal operating range of a quad tail cell driven by a tail current as a multiplier. In a multiplier core circuit whose input is floating, the operating range 51 as an ideal multiplier has a diamond shape as shown. As the MOS transistor starts to cut off, a characteristic deviates from an ideal characteristic as a multiplier. In the figure, the range 52 _{1 to} 52 of the shape like four leaves
₄ is a characteristic range with some defects compared to the characteristics of an ideal multiplier.

FIG. 6 shows the overall circuit configuration of a four-quadrant analog multiplier using a cascode transistor whose source is grounded as an input circuit. When the input circuit consisting of a cascode transistor whose source is grounded is a constant current source drive and the input is a floating input, a differential operation is performed. Thus, the input voltage to the MOS multiplier core circuit will be similar to that re-proposed by Wan. The overall circuit of the CMOS four-quadrant multiplier shown in FIG. 4 has fewer transistors than the Baltic and Waringer proposed multiplier and Wang's re-proposed multiplier overall circuit. Low voltage operation is also possible.

FIG. 7 shows an MO in the case where the source is grounded.
It shows a configuration of an S multiplier core circuit and a combination of input voltages thereof. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
The circuit of FIG. 7 differs from that of FIG. 1 in that each MOS transistor is driven by a constant current source or is grounded. The combination of the input voltages is the same as in FIG. The drain current of each transistor when the input voltage is applied as described above is expressed by the following equation.

(Equation 13)

The differential output current ΔI of the grounded source MOS multiplier core circuit is expressed by the following equation.

[Equation 14]

The conditions under which the transistor is cut off are as follows:
(V _X , V _Y ) differs in each quadrant, and the first quadrant (V _X > =
0, V _Y > = 0), no transistor is cut off. The DC voltage V _R of the input signal in the multiplier core circuit shown in FIG. 7 can be set arbitrarily. Also, each voltage of the input signal can be set to a range in which the transistor is not cut off by an appropriate attenuator. Therefore, equations (32) to (3)
From equation (6), the input voltage range is | V _X | + | V _Y | = <V
_{If R} - _VTH is set, the transistor does not cut off in any quadrant. Equation (36a) expresses the differential output current characteristic when none of the transistors is cut off, and this equation has a linear transfer characteristic. That is, assuming a square characteristic of the MOS transistors, appropriately setting the DC voltage V _R and the input voltage range by using any of the transistors no cut-off area, it is possible to obtain an ideal multiplier characteristics it can.

FIG. 8 shows each transistor with respect to the input voltage.
Indicates a region to be cut off. Oblique in the figure
The line section shows that all four transistors are cut off.
Indicates no area. Input voltage range of this shaded area
Is | V_X| + | V_Y| = <V _R-V_THIs represented by
As the input voltage increases, the MOS transistors in the circuit
As the register begins to cut off, the ideal multiplier
Deviates from characteristics.

When the equation (36a) representing the differential output current when the transistor is not cut off is differentiated by V _X , the trunk conductance characteristic is obtained, and the following equation is obtained.

(Equation 15) A similar result is obtained when the equation (36a) is differentiated by V _Y , and the multiplier core circuit has the same transconductance characteristic for both V _X and V _{Y in} the input voltage range where the transistor is not cut off. You can see that you have.

Next, a multiplier core circuit using bipolar transistors will be described.

FIG. 9 shows the case where a bipolar transistor is used.
Of Multiplier Core Circuit and its Input Voltage
Is a combination. 1st to 4th buy
The emitters of polar transistors 61 to 64 share one another.
And then grounded via the constant current source 65.
You. Further, the first bipolar transistor 61 and the second
The collectors of the bipolar transistors 62 are commonly connected
And their collector currents are added, and the output current I_L
It is 66. On the other hand, the third bipolar transistor
Of the transistor 63 and the fourth bipolar transistor 64
Are also connected in common, their collector currents are added,
Output current I_RIt is 67. I_LTo I_RDeduct
Differential output current is the output voltage of the multiplier core circuit.
It is flowing. In this circuit, the first transistor 6
The base of 1 is V₁= -V_X+ V _Y/ 2 voltage applied
Have been. The base of the second transistor 62 has V
_Two= V_X+ V_YIs applied. Similarly, the third
V is_Three= -V _X+ V_YBut the fourth tran
The register 64 has V_Four= V_X+ V_Y/ 2 applied
Have been. Substituting these voltages into equation (19) gives
The differential output current ΔI of the bipolar quadritail cell is
It is obtained as follows.

(Equation 16) This is equal to equations (20) and (22). That is, it is equal to the well-known difference output current of the Gilbert multiplier cell. Generally, in a bipolar process, α _F ranges from 0.98 to 0.
99, which is close to "1". Therefore, such a combination of input voltages allows the bipolar quadruple retail cell to operate as a multiplier core circuit. Compared with the Gilbert multiplier cell, the transistor is not stacked vertically, so that low voltage operation is possible.

FIG. 10 shows the transfer characteristics of the bipolar multiplier core circuit according to the combination of the input voltages shown in FIG. Based on equation (38), V _Y
Is used as a parameter to express the transfer characteristic. V
_X is in the range of "0" about + -1 V _T around the, are substantially linear characteristics. Also, it can be seen that a large signal input has limiting characteristics due to the tail current.

[0049] Figure 11, the transfer characteristics shown in FIG. 10 V _X
5 shows transconductance characteristics when differentiated by. In this figure, V _Y is represented as a parameter. As can be seen from the figure, when V _X is near “0”, dΔI / dV _X is nearly flat. Therefore, it can be seen that a substantially linear characteristic is obtained as a multiplier. However, it can be seen that a completely linear characteristic is not obtained as in the MOS multiplier core circuit.

When the emitter of each transistor is grounded without being driven by the constant current source 65 as in the bipolar multiplier core circuit shown in FIG. The differential output current is represented by the following equation.

[Equation 17] As can be seen from this equation, when the source is grounded, the transfer characteristic cannot be called a multiplier core circuit. Therefore, when using a bipolar transistor, unless driven by a constant current source,
It cannot operate as a core circuit.

The combination of voltages to be applied to the source or gate of each transistor of the multiplier core circuit can be represented by the following general formula. _{V 1 = aV X + bV Y} (40a) V 2 = (a-c) V X + (b-1 / c) V Y (40b) V 3 = (a-c) V X + bV Y (40c) V 4 _{= aV X + (b-1} / c) V Y (40d) where, a, b, c are arbitrary integers, respectively. The following relationship holds between these equations. V ₁ −V ₃ = V ₄ −V ₂ = cV _X (41a) V ₁ −V ₄ = V ₃ −V ₂ = V _Y / c (41b) Each voltage of V _{1 to} V ₄ is applied to the gate of the MOS transistor. The drain current when applied is given by the following equation according to the square law.

(Equation 18)

Therefore, the output current ΔI of the multiplier core circuit is expressed by the following equation.

[Equation 19] As described above, when the current applied to the gate of each transistor has the relationship represented by the equation (40), the transistor operates as a multiplier.

FIG. 12 shows an outline of an input circuit of a multiplier core circuit for forming such four voltages. V ₁ is a voltage obtained by multiplying V _X by a and V _Y
Is b times the sum of the voltages. These can be configured by an active circuit using a transistor. When the coefficient on the right side of the equation (40) becomes negative, it is necessary to generate a voltage to be applied to the gate or base of each transistor of the multiplier core circuit by such an active circuit element.

If a = 1/2, b = 1 and c = 1, V
Each ₁ ~V ₄ is expressed as follows. _{V 1 = V X + V Y} (44a) V 2 = V X / 2-V Y (44b) V 3 = V X / 2 + V Y (44c) V 4 = V X -V Y (44d) where, V _X if replaced with each other and V _Y and the relation of these voltages match the combination of the input voltage of the multiplier core circuit shown in FIG.

[0055]

According to the invention of claim 1, wherein, as described in the foregoing, when the two input voltages to be multiplied was set to _{V X, V Y, -V X} + V Y / 2, V X + V Y, −V _X +
V _Y, and a voltage is applied is converted into a combination of V _X + V _Y / 2 to each transistor. As a result, a multiplier core circuit having excellent linearity and capable of operating at a low voltage can be obtained. Further, the scale of an input circuit for converting an input voltage to be multiplied can be reduced. Furthermore, if one of the input voltages is used as a signal for controlling the gain, it can be used as an AGC (Auto Gain Control) circuit because it has a predetermined limiting characteristic. When used as an ODA circuit, the circuit configuration of the input circuit can be reduced.

According to the second aspect of the present invention, the MOS
Since the multiplier core circuit is formed using the transistors of the type, the source can be grounded. This eliminates the need for a constant current source and can reduce the circuit scale. Further, the input voltage range can be widened.

Further, according to the third aspect of the present invention, since the multiplier core circuit is constituted by using the field effect transistor, the source can be grounded.
This eliminates the need for a constant current source and can reduce the circuit scale. Further, the input voltage range can be widened.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a MOS multiplier core circuit and a combination of input voltages thereof in an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing input / output characteristics of the MOS multiplier core circuit shown in FIG.

FIG. 3 is a characteristic diagram showing a transconductance characteristic of the MOS multiplier core circuit shown in FIG.

FIG. 4 is a circuit diagram showing an example of a circuit configuration of the entire multiplier using the MOS multiplier core circuit shown in FIG.

FIG. 5: Multiplier with input floating
FIG. 4 is a characteristic diagram illustrating a normal operation range of the core circuit.

FIG. 6 is a circuit diagram showing another example of a circuit configuration of the entire multiplier using the MOS multiplier core circuit shown in FIG.

FIG. 7 is a circuit diagram showing a configuration of a MOS multiplier core circuit whose source is grounded and a combination of input voltages thereof.

8 is a characteristic diagram showing an ideal operation input voltage range of the MOS multiplier core circuit shown in FIG.

FIG. 9 is a circuit diagram showing a configuration of a bipolar multiplier core circuit and a combination of input voltages thereof.

FIG. 10 shows a bipolar multiplier shown in FIG.
FIG. 3 is a characteristic diagram illustrating input / output characteristics of a core circuit.

FIG. 11 shows a bipolar multiplier shown in FIG.
FIG. 4 is a characteristic diagram illustrating a transconductance characteristic of a core circuit.

FIG. 12 is a block diagram showing an outline of a configuration of an input circuit of the multiplier core circuit.

FIG. 13 is a circuit diagram showing a configuration of a MOS multiplier core circuit having a floating input.

FIG. 14 is a circuit diagram showing a configuration of a MOS multiplier core circuit whose source is grounded.

FIG. 15 is a circuit diagram showing a configuration of a conventionally used MOS multiplier core circuit having a floating input proposed by Balut and Warringer and a combination of input voltages thereof.

FIG. 16 is a circuit diagram showing a configuration of a conventionally used MOS multiplier core circuit with a grounded source proposed by Balt and Waringer and a combination of input voltages thereof.

FIG. 17 is a circuit diagram showing a configuration of a conventionally used MOS multiplier core circuit having a floating input and a combination of its input voltages, which is re-proposed by Wan;

FIG. 18 is a circuit diagram showing a configuration of a conventionally used MOS multiplier core circuit with a grounded source proposed by Wu and Stuman and a combination of input voltages thereof.

FIG. 19 is a circuit diagram showing a configuration of a bipolar multiplier core circuit having a floating input.

FIG. 20: MOS proposed by Balt and Waringah
FIG. 3 is a circuit diagram illustrating a configuration of a multiplier core circuit in which the multiplier core circuit is replaced with a bipolar transistor and a combination of input voltages thereof.

FIG. 21 is a circuit diagram showing a configuration of a multiplier core circuit in which a MOS multiplier core circuit re-proposed by Wan is replaced with a bipolar transistor and a combination of input voltages thereof.

[Explanation of symbols]

 11 to 14 MOS transistors 15, 55 Constant current sources 16, 17, 56, 57 Output currents 51, 52, 53, 54 Bipolar transistors 72, 73, 81 Resistors

Claims (3)

(57) [Claims] A first transistor having a gate or a base supplied with a sum signal of a voltage signal having a phase opposite to that of the first voltage signal and half of a voltage signal of the second voltage signal; A second transistor having a gate or a base that receives a sum signal of a voltage signal and the second voltage signal and having a drain or a collector commonly connected to a drain or a collector of the first transistor; A third transistor having a gate or a base to which a sum signal of the opposite phase signal of the voltage signal and the second voltage signal is input to a gate or a base thereof; and a half of the first voltage signal and the second voltage signal. Signal is input to the gate or base of the third transistor and the drain or collector of the third transistor is connected to the drain or collector of the third transistor. And a fourth transistor commonly connected to the first and fourth transistors; and a constant current source for driving the first to fourth transistors with a common tail current. 2. A first MOS transistor having a gate that is supplied with a sum signal of a voltage signal having a phase opposite to that of the first voltage signal and a half of the voltage signal of the second voltage signal and having a source grounded; A second MOS transistor having a gate to which a sum signal of the first voltage signal and the second voltage signal is input and whose source is grounded and whose drain is commonly connected to the drain of the first MOS transistor; A third MOS transistor having a gate to which a sum signal of the opposite phase signal of the first voltage signal and the second voltage signal is input and whose source is grounded; and the first voltage signal and the second voltage A sum signal of a voltage signal having half the magnitude of the signal is input to its gate and grounded, and its drain is connected to the third MO.
Fourth MO commonly connected to the drain of the S transistor
A multiplier core circuit comprising an S transistor. 3. A first field-effect transistor, wherein a sum signal of a voltage signal having a phase opposite to that of the first voltage signal and half the magnitude of the second voltage signal is input to its gate and grounded at the source. A second signal in which a sum signal of the first voltage signal and the second voltage signal is input to the gate thereof, is grounded at the source, and has a drain commonly connected to a drain of the first field effect transistor; A field-effect transistor; a third field-effect transistor having a gate to which a sum signal of the opposite phase signal of the first voltage signal and the second voltage signal is input and grounded at the source; A sum signal of a voltage signal and a voltage signal having half the magnitude of the second voltage signal is input to its gate and grounded at the source, and its drain is connected to the drain of the third field effect transistor. And a fourth field-effect transistor commonly connected to the multiplier core circuit.