JP2626591B2 - Multiplier core circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier core circuit for multiplying two analog signals, and more particularly to a low voltage operable multiplier core circuit formed on a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A multiplier for multiplying two signal values is an indispensable function block in analog signal processing. 2. Description of the Related Art Conventionally used multipliers include those configured by two transistors using the square characteristic of a MOS transistor. That is, assuming that input voltages are a and b, the linear operation of the multiplier is expressed by the following algebraic equation. (A + b) ^2- (ab) ² = 4ab (1) As described above, a method of obtaining a multiplier based on a linear function defined by two square differences is known as a quarter-square technique. .

The drain current of a MOS transistor operating in the saturation region is expressed by the following equation if channel length modulation and the body effect are neglected. I _Di = β (V _GSi −V _TH ) ² (V _GSi > = V _TH ) (2a) I _Di = 0 (V _GSi ≦ V _TH ) (2b) where β = μ (C _OX / 2) (W / L) is a transconductance parameter, μ is effective mobility of carrier, C _OX is gate oxide film capacity per unit area,
W and L represent a gate width and a gate length, respectively. V _GSi represents a gate-source voltage, and V _TH represents a threshold voltage. in this way,
Since the threshold voltage is added to the parameters in the drain current characteristic of the MOS transistor, (1)
When the circuit corresponding to the equation is constituted by MOS transistors, the effect of the threshold voltage is not eliminated.

Therefore, in order to eliminate this, an unnecessary parameter c is further added, and two linear functions expressed by the following equation using the sum and difference of four squares including the parameter are defined. ing. ^{(A + b + c) 2} - (a-b + c) 2 + (a + b-c) 2 - (a-b-c) 2 = 8ab (3) (a + b) 2 - (a-c) 2 + (a + b-c) 2 − (Ab−c) ² = 4ab (4) The multipliers corresponding to these linear functions are four M
It can be realized using an OS transistor.

FIG. 15 shows a configuration of a multiplier core circuit in which an input is floated using a quadritail cell. The sources of the first to fourth MOS transistors 101 to 104 are commonly connected to each other, and are grounded via a constant current source 105. First M
OS transistor 101 and second MOS transistor 1
02 and the drains of the third MOS transistor 103 and the fourth MOS transistor 104 are commonly connected. The sum of the drain currents of the two MOS transistors is obtained by the common connection. The drain current I _R 1 from the drain current I _L 106
07 is output as a differential output current. If all of the four transistors constituting the multiplier core circuit are used in an input voltage range that does not cut off, each transistor operates according to the square law shown in the equation (2a). Therefore, an operation corresponding to the linear functions shown in the equations (3) and (4) can be obtained by the illustrated circuit.

FIG. 16 shows four source-grounded MOSs.
This shows the configuration of a multiplier core circuit using transistors. The same parts as those in FIG. 15 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. This multiplier core circuit is different from the one shown in FIG.
To the fourth MOS transistors 101 to 104 are grounded at the source. In this circuit, I _L 1
The difference from 06 to I _R 107 is output as a differential output current, and a multiplier corresponding to the linear function of equation (3) or (4) can be realized.

The differential output current ΔI / β of the multiplier core circuit shown in FIG. 15 or 16 is expressed by the following equation in an input voltage range where none of the transistors in the circuit is cut off. _{ΔI / β = (V 1 +} V R -V S -V TH) 2 + (V 2 + V R -V S -V TH) 2 - (V 3 + V R -V S -V TH) 2 - (V 4 + V ^{_{R -V S -V TH) 2 =}} V 1 2 + V 2 2 -V 3 2 -V 4 2 + 2c (V 1 + V 2 -V 3 -V 4) (5) However, c = V _R -V _S - V _TH, the V _R DC voltage of the input signal, V _S is the common source voltage, in the case of Figure 16 the source of which is grounded, V _S is "0". In FIG. 15, since the tail current is common, the condition represented by the following equation is satisfied. I _D1 + I _D2 + I _D3 + I _D4 = I ₀ (6) The following relationship is established for a combination of input voltages that eliminates the term c. V ₁ + V ₂ −V ₃ −V ₄ = 0 (7) Therefore, the expression (5) becomes as follows. ^{_{ΔI / β = V 1 2 +}} V 2 2 -V 3 2 -V 4 2 = (V 1 -V 4) (V 1 + V 4 -V 2 -V 3) (8)

[0008] Heretofore, there are two types of input voltage combination methods in which the characteristics of the differential output current are linearized, the first type proposed by Bult and Wallinga, and the one proposed by Balt. A second type is known, which was re-proposed by Wang and Schaumann. The circuit proposed by Balt et al. Is IEEE Journ
al of Solid-State Circuits, Vol.SC-21, No.3 pp430-43
5, June 1986. Also, the circuit proposed by Balt is disclosed in his Ph, D and dissertation, but has been re-proposed by Wang et al. And is easily available. Wang's re-proposed circuit is the IEE Electron letters, 18th Jan.1
990, Vol.26, No.9. In addition, Wu
The circuit re-proposed by Stuman was an IEE Electron let
ters, 4th July 1991, Vol. 27, No. 14.
The relationship of the input voltage in the first type is represented by the following equation. _{(V 1, V 2, V} 3, V 4) = {(V X + V Y) / 2, - (V X + V Y) / 2, - (V X -V Y) / 2, (V X -V _Y ) / 2｝ (9) Further, the relationship of the input voltage in the second type is represented by the following equation. _{(V 1, V 2, V} 3, V 4) = {V X / 2, -V X / 2 + V Y, V X / 2-V Y, -V X / 2} (10)

FIG. 17 shows a configuration of a first-type multiplier core circuit whose input is floating and a combination of input voltages thereof. The same circuit portions as those in FIG. 15 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. By adjusting the DC voltage V _R of the input signal, each transistor is operated within a range not to cut off.

FIG. 18 shows that four transistors are connected to the source.
Grounded first type of multiplier core circuit
And the combination of the input voltage
It is. The first type of input shown in FIG. 17 and FIG.
Each combination of force and voltage is (V₁, V_Two, V_Three,
V_Four) = (A + b, -ab, -a + b, ab)
This is a relation corresponding to the equation (3). these
Substituting into equation (8) gives V₁-V_Four= 2b, V₁+ V_Four
-V_Two-V_Three= 4a (where V₁+ V_Four= -V _Two-V
_Three= 2a), and ΔI / β = 8ab is obtained. This
Thus, the two voltage signals to be multiplied are of the first type
Convert to the combined four voltage signals and
Unnecessary parameters by inputting to each transistor of the
Data c to obtain a multiplier with linear characteristics.
Can be.

FIG. 19 shows that the input is floating.
Of a second type of multiplier core circuit
And the combination of the input voltages. Times
The configuration of the road is the same as that shown in FIG. Input voltage
Is to convert the two voltage signals to be multiplied to V_X, V
_YThen V_X/ 2, -V_X/ 2 + V_Y, V_X/ 2-
V_Y, -V_X/ 2. Also in this circuit,
DC voltage V of input signal _RBy adjusting the
Stars operate within the range that does not cut off
I have.

FIG. 20 shows that four transistors are connected to the source.
Grounded second type of multiplier core circuit
And the combination of the input voltage
It is. The second type of input shown in FIG. 19 and FIG.
Each combination of force and voltage is (V₁, V_Two, V_Three,
V_Four) = (A, -ab, ab, -a)
That is, the relationship corresponds to the expression (4). These are given by equation (8)
Substituting into₁-V _Four= 2a, V₁+ V_Four-V_Two−
V_Three= 2b (where V₁+ V_Four= -V_Two-V_Three= 2
a), and ΔI / β = 4ab is obtained. in this way,
Two input voltages to be a combination of the second type
Is converted to each transistor of the multiplier core circuit.
Multiplier with linear characteristics by applying
Can be obtained.

When the four transistors are grounded at the source, the input voltage range can be widened, and the circuit current can flow until it is restricted by factors such as the internal resistance of the transistors. On the other hand, when four transistors are driven by a constant current source, the circuit current is set by the tail current,
The input voltage range is limited by this tail current. However, in the case of realizing an LSI, it is desirable to employ a floating input and a constant current drive which can avoid the influence of manufacturing variations.

FIG. 21 shows four bipolar transistors.
Configuration of multiplier core circuit composed of
Is expressed. First to fourth bipolar tigers
The emitters of the transistors 111 to 114 are commonly connected to each other.
After that, it is grounded via a constant current source 115. Ma
In addition, the first bipolar transistor 111 and the second
The collectors of the bipolar transistors 112 are commonly connected.
And their collector currents are added to produce an output current I_L1
It is 16. On the other hand, the third bipolar transistor
Of the transistor 113 and the fourth bipolar transistor 114.
The collectors are also connected in common, and their collector currents are added.
Output current I_R117. I _LTo I_RTo
The subtracted differential output current is used for the multiplier core circuit.
Output current. First to fourth bipolar tigers
The bases of the transistors 111 to 114
The voltage value after converting the pressure into a predetermined combination is applied.
It has become so.

The relationship between the collector current and the base-emitter voltage of a bipolar transistor is expressed by the following equation, assuming that it follows an exponential law.

(Equation 1)Where V_BEiIs the base-emitter voltage, I_SIs saturated
It is a current. V_TIs the thermal voltage, V_T= Q / kT and table
Be forgotten. Where q is unit electron charge and k is Boltzmann
The constant, T, is the absolute temperature. Base-emitter voltage V
_BEiIs about 600 mV during normal operation of the transistor.
In other words, the exponent part exp (V _BEi/ V_T) Is
Since the value is about 10th power, the term "-1" can be ignored.
You. Therefore, equation (11) can be expressed as
Can be.

(Equation 2)

[0016] In this case, the collector currents of the transistors of the bipolar quadritail cell shown in FIG. 18 driven by the tail current I _EE is expressed by the assumed and equation as a good consistency between elements.

(Equation 3) However, the V _R DC voltage component of the input signal, V _E is a common emitter voltage. In addition, since the motor is driven by the common tail current by the constant current source, the following conditional expression is satisfied. I _C1 + I _C2 + I _C3 + I _C4 = α _F I ₀ (17) where α _F is a DC current gain of the transistor.

Solving equations (14) to (18) gives the following equation.

(Equation 4) Accordingly, the differential output current ΔI of the bipolar quadritail cell is obtained by the following equation.

(Equation 5)

FIG. 22 shows a state where an input voltage of the first type combination is applied to the multiplier core circuit using the bipolar quadritail cell. The same circuit portions as those in FIG. 21 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The input is floating by being driven by the constant current source 115. V ₁ was _{(V X + V Y) /} 2, V 2 is - (V _X + V
_Y) / 2, V ₃ is _{- (V X -V Y) /} 2 and V _4, is _{(V X -V Y) / 2} . By substituting these into equation (19), the differential output current ΔI of the bipolar quadritail cell is expressed by the following equation.

(Equation 6) Multiplying the right-hand side of this equation by α _F gives the well-known Gilbert multiplier c
ell) of the differential output current. In a typical bipolar process, α _F is between 0.98 and
0.99, which is almost a value close to “1”.
Therefore, by converting the input voltage into such a combination and applying it to each transistor of the bipolar quadritail cell, it is possible to obtain a multiplier core circuit having almost the same transfer characteristics as the Gilbert multiplier cell. . However, compared to the Gilbert multiplier cell, since the transistors are not stacked vertically, operation at a low voltage is possible. In the case of a bipolar transistor, if the emitter is grounded, it will not operate as a multiplier core circuit. The differential output current ΔI when the emitter is grounded is expressed by the following equation.

(Equation 7) However, it is _{I 0 = I S exp (V} R / V T).

FIG. 23 shows a bipolar quadrilateral cell.
The second type of set in the multiplier core circuit by
It shows the state when the combined input voltage is applied.
It is. The same circuit parts as those in FIG.
The description is omitted as appropriate. V₁Is V_X/ 2, V_TwoIs
-V_X/ 2-V_Y, V_ThreeIs V_X/ 2-V_YAnd V _Four
Is -V_X/ 2. Substitute these into equation (19)
And the differential output current Δ of the bipolar quadritail cell
I is represented by the following equation.

(Equation 8) By multiplying the right side of this equation by α _F , it becomes equal to the one expressing the differential output current of the Gilbert multiplier cell as in the case of FIG. Therefore, it can be operated as a multiplier core circuit. However, the differential output current ΔI when the emitter is grounded is expressed by the following equation.

(Equation 9) In this case, the transmission characteristics cannot be called a multiplier core circuit.

[0020]

In recent years, the process has become finer, and accordingly, the power supply voltage of the LSI has been lowered from 5 V to about 3.3 V or about 3 V. Furthermore, it has been widely accepted that the CMOS process is the most suitable process technology for LSI integration.
There is a demand for a circuit for realizing a multiplier in a process. A conventional multiplier using a Gilbert multiplier cell cannot be operated at a low voltage because a large number of transistors are stacked vertically. On the other hand, in a multiplier core circuit using four transistors, transistors are not stacked vertically and can be operated at a low voltage. However, the combination of the first and second types of voltages proposed at present has a large circuit scale for converting two voltage signals to be multiplied into four voltage signals, and the circuit as a whole multiplier is required. There is a problem that the configuration is complicated. Further, in order to generate a voltage to be applied to the multiplier core, it is necessary to generate a reverse phase voltage of the input voltage, which causes a problem that the circuit configuration becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiplier core circuit having a linear characteristic by a new combination of input voltages and capable of operating at a low voltage.

[0022]

According to the first aspect of the present invention, there is provided a first transistor in which a sum signal of a negative phase signal of a first voltage signal and a second voltage signal is input to a gate or a base thereof; A second transistor having a voltage signal twice as large as the first voltage signal input to its gate or base and having its drain or collector commonly connected to the drain or collector of the first transistor;
A third transistor whose first voltage signal is input to its gate or base, and a sum signal of a voltage signal twice as large as the first voltage signal and a reverse phase signal of the second voltage signal are supplied to its gate. Alternatively, a fourth transistor which is input to the base and whose drain or collector is commonly connected to the drain or collector of the third transistor, and a constant current source which drives the first to fourth transistors with a common tail current Are provided in the multiplier core circuit.

That is, according to the first aspect of the present invention, the first voltage signal to be multiplied is V _X , and the second voltage signal is V V
When _Y, the first transistor V _X -V _Y, the second
Are applied with a voltage of 2V _X. Further, the third transistor, V _X, the voltage of 2V _X -V _Y to the fourth transistor are respectively applied. By converting the input voltage to such a combination and applying it to each transistor of the multiplier core circuit, a multiplier having a linear characteristic in which the influence of the threshold voltage is eliminated can be obtained. Also,
By driving the four transistors with a common tail current, the inputs can be floated and the multiplier core circuit can have limiting characteristics.

According to the second aspect of the present invention, the sum signal of the negative phase signal of the first voltage signal and the second voltage signal is input to the gate thereof and the source is grounded. A transistor and a second MOS-type or field-effect type MOS transistor whose gate is supplied with a voltage signal twice as large as the first voltage signal and whose source is grounded and whose drain is commonly connected to the drain of the first transistor. A transistor, a MOS-type or field-effect-type third transistor whose first voltage signal is input to its gate and whose source is grounded, a voltage signal twice as large as the first voltage signal, and a second voltage signal. A MOS type or the like, in which the sum signal of the opposite phase signal of the voltage signal is input to the gate and the source is grounded and the drain is commonly connected to the drain of the third transistor And it is provided with a fourth transistor of the field effect type multiplier core circuit.

That is, according to the second aspect of the present invention, the first voltage signal to be multiplied is V _X , and the second voltage signal is V
When _Y, the first transistor V _X -V _Y, the second
Are applied with a voltage of 2V _X. Further, the third transistor, V _X, the voltage of 2V _X -V _Y to the fourth transistor are respectively applied. By converting the input voltage to such a combination and applying it to each transistor of the multiplier core circuit, a multiplier having a linear characteristic in which the influence of the threshold voltage is eliminated can be obtained. Also,
Since the source is grounded, a constant current source becomes unnecessary. Further, the circuit current can flow until it is limited by factors such as the internal resistance of the transistor, and the input voltage range can be widened.

According to the third aspect of the present invention, the sum signal of a voltage signal having a magnitude of one half of the first voltage signal and a voltage signal having a magnitude of one half of the second voltage signal is supplied to the gate thereof. Alternatively, a first transistor input to the base and a voltage signal of a quarter of the first voltage signal are input to the gate or the base and the drain or the collector is the drain or the collector of the first transistor. A second transistor commonly connected to the collector, and a sum signal of a voltage signal of a quarter of the first voltage signal and a voltage signal of a half of the second voltage signal. A third transistor input to the gate or base and a voltage signal having half the magnitude of the first voltage signal are input to the gate or base and the drain or collector is input to the third transistor. Drain or collector of the transistor and a fourth transistor connected in common, first
And a constant current source for driving the fourth transistor with a common tail current is provided in the multiplier core circuit.

That is, in the invention according to claim 3, the first voltage signal to be multiplied is V _X , and the second voltage signal is V V
_{If Y} , the first transistor has (V _X + V _Y ) /
A voltage of V _X / 4 is applied to the second and second transistors, respectively. Further, the third transistor has V
_X / 4 + _VY / 2, and a voltage of _VX / 2 is applied to the fourth transistor, respectively. By converting the input voltage to such a combination and applying it to each transistor of the multiplier core circuit, a multiplier having a linear characteristic in which the influence of the threshold voltage is eliminated can be obtained. Also, by driving the four transistors with a common tail current, the inputs can be floated and the multiplier core circuit can have limiting characteristics. In addition, 4
Since each of the two voltages is a positive multiple of V _X and V _Y , these voltages can be easily formed by, for example, a resistance voltage dividing circuit, and the input circuit of the multiplier core circuit can be formed with a simple configuration. Can be realized.

According to the fourth aspect of the present invention, the sum signal of a voltage signal having a magnitude of one half of the first voltage signal and a voltage signal having a magnitude of one half of the second voltage signal is supplied to the gate thereof. And a MOS-type or field-effect type first transistor whose source is grounded, a voltage signal having a magnitude of a quarter of the first voltage signal is input to its gate and grounded, and A MOS-type or field-effect type second transistor having a drain commonly connected to the drain of the first transistor; a voltage signal having a magnitude of one-fourth of the first voltage signal; A MOS-type or field-effect-type third transistor whose voltage is summed at the gate thereof and whose source is grounded is connected to a third transistor of the MOS type or the field-effect type. A voltage signal enters its gate By and with the source grounded, its drain is and a fourth transistor of which drain common-connected MOS type or field effect type of the third transistor to the multiplier core circuit.

That is, in the invention according to claim 4, the first voltage signal to be multiplied is V _X , and the second voltage signal is V _{X
If Y} , the first transistor has (V _X + V _Y ) /
A voltage of V _X / 4 is applied to the second and second transistors, respectively. Further, the third transistor has V
_X / 4 + _VY / 2, and a voltage of _VX / 2 is applied to the fourth transistor, respectively. By converting the input voltage to such a combination and applying it to each transistor of the multiplier core circuit, a multiplier having a linear characteristic in which the influence of the threshold voltage is eliminated can be obtained. Further, since the source is grounded, a constant current source becomes unnecessary. Further, the circuit current can flow until it is limited by factors such as the internal resistance of the transistor, and the input voltage range can be widened. Further, since the four voltages are each a positive multiple of V _X and V _Y , these voltages can be easily formed by, for example, a resistor voltage divider, and the input circuit of the multiplier core circuit can be simplified. It can be realized with a simple configuration.

According to the fifth aspect of the present invention, the voltage applied to the gate or the base of the first transistor is equal to the first voltage.
And a second voltage signal generated by a first resistive voltage dividing circuit which internally divides the voltage signal at a voltage dividing ratio of 1: 1. The voltage applied to the gate or base of the second transistor is the first voltage. A voltage generated by a second resistor voltage dividing circuit that internally divides a signal and a ground potential at a voltage dividing ratio of 3: 1 and applied to a gate or a base of the third transistor is:
A voltage generated by a third resistive voltage dividing circuit that internally divides the first voltage signal and the ground potential at a voltage dividing ratio of 1: 1 and applied to the gate or base of the fourth transistor is connected to one end of the fourth transistor. A first resistor to which a first voltage signal is applied;
One end of the first resistor is connected to the other end, a second voltage signal is applied to the other end, and the resistance of the first resistor is set to the first value.
And a third resistor having one end connected to a connection point of the first resistor and the second resistor and the other end grounded at the other end and having a resistance value equal to the first resistance. Is the voltage appearing at the connection point of the first and second resistors of the fourth resistor voltage dividing circuit having

That is, according to the fifth aspect of the present invention, the voltage applied to the gate or source of each transistor is
It is generated by a resistance voltage dividing circuit. Since each of the four voltages is configured by a combination of a positive multiple of V _X and V _Y , these voltages can be easily generated by the resistance voltage dividing circuit.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows a configuration of a multiplier core circuit according to an embodiment of the present invention. First to first
The fourth MOS transistors 11 to 14 are grounded via a constant current source 15 after their sources are commonly connected. The drain of the first and second MOS transistors 11 and 12 are commonly connected, as an output current I _L 16 and the drain current is added. Also, the third and fourth M
The drains of the OS transistors 13 and 14 are also commonly connected, and their drain currents are added to form an output current I _R 17. Differential output current Δ obtained by subtracting I _R from I _L
I is the output current of the multiplier core circuit.

The voltages of the input signals to be multiplied are V _X , V
When the _Y, to the gate of the first MOS transistor 11, so that the V _X -V _Y is applied by a peripheral circuit (not shown). 2V _X is applied to the gate of the second MOS transistor 12. Similarly, the third MOS transistor 13, the voltage of V _X is, the fourth MOS transistor 14, 2V _X -V _Y
Are applied respectively.

By the way, 4 including unnecessary parameter c
Using the sum and difference of the two squares, define a linear function such as
Can be justified. (Abc)^Two+ (2a-c)^Two-(Ac)^Two-(2a-bc)^Two= 2 ab (24) In this case, the combination of input voltages is (V₁, V_Two,
V_Three, V_Four) = (Ab, 2a, a, 2a-b)
Is done. Substituting this into equation (8) gives V₁-V_Four= −
a, V₁+ V_Four-V_Two-V_Three= 2b (where V₁+ V
_Four= 3a + 2b, V _Two+ V_Three= 3a), and ΔI / β
= 2ab. The relationship between these four voltages is exactly
MOS transistors in the multiplier core circuit shown in FIG.
This corresponds to the relationship between the voltages applied to the transistors. But
Therefore, unnecessary power is not available even with such a combination of voltages.
Forming an erased multiplier of parameter c
Can be.

The drain current of each transistor in the quad tail cell composed of four transistors driven by a common tail current shown in FIG. 1 is expressed by the following equation.

(Equation 10) However, the V _R DC voltage of the input signal, the V _S is the common source voltage. The following equation is established from the condition of the tail current. I _D1 + I _D2 + I _D3 + I _D4 = I ₀ (29)

The differential output current ΔI of the MOS 4-quadrant analog multiplier is expressed by the following equation.

[Equation 11]

Equation (30) is equal to the transfer characteristic of the multiplier proposed by Balt and Waringer and the transfer characteristic of Wang's proposed multiplier. Also, MO
Assuming the square law of the S transistor, an ideal multiplier characteristic can be obtained in an input voltage range where all four MOS transistors are not cut off (range of the 30a equation). As the input voltage increases,
MOS transistors in the circuit start to cut off, and the characteristics gradually deviate from the ideal characteristics of the multiplier.

FIG. 2 shows the transfer characteristics of the multiplier core circuit according to the combination of the input voltages shown in FIG. This represents the transfer characteristic based on equation (30), using V _Y as a parameter. From this figure, it can be seen that the tailor current causes the multiplier core circuit to have limiting characteristics for large signal inputs.

By differentiating the equation (30), the transconductance characteristic of the multiplier can be obtained. The following equation shows the result of differentiating the differential output current ΔI with V _X.

(Equation 12)

FIG. 3 shows the transconductance characteristics of the multiplier. This is obtained based on the equation (31). Also, V _Y is represented as a parameter. This is within the range V _X is given as the transconductance characteristic is in a fully flat, it can be seen that the relation between the input voltage and the output current has a linear characteristic which is linearized. Further, it can be seen that with equal transconductance characteristics for any V _X, V _Y.

FIG. 4 shows the multiplier code shown in FIG.
A Multiplier whole circuit with input circuit added to circuit
It shows the configuration. Gate of transistor 21
Has V_XHas been added. Transistors 22, 23,
V copied through 24 _XAnd transistor 25
Obtained V_YOf the diode-connected transformer
The voltage V through the transistor 26_X-V_YIs transistor 2
7 is applied to the gate. Also, tiger
The voltage V_XIs copied and the
2V via the star 29, 31_XVoltage, which is
The voltage is applied to the gate of the transistor 32. This 2V_X
Current corresponding to the voltage of the transistors 33, 34, 3
5 and in addition to the gate of transistor 36
Voltage V_YAfter the difference from the current corresponding to
This is the gate voltage of the diode-connected transistor 37.
Removed as pressure. And this voltage 2V_X-V
_YIs applied to the gate of the transistor 38. This
Thus, the transitions constituting the multiplier core circuit
The gates of the gates 27, 38, 32 and 21 have V
_X-V_Y, 2V_X-V_Y, V_X, 2V_XIs applied
Swelling.

FIG. 5 shows a normal operating range of a quad tail cell driven by a tail current as a multiplier. In a multiplier core circuit whose input is floating, the operating range 51 as an ideal multiplier has a diamond shape as shown. As the MOS transistor starts to cut off, a characteristic deviates from an ideal characteristic as a multiplier. In the figure, the range 52 _{1 to} 52 of the shape like four leaves
₄ is a characteristic range with some defects compared to the characteristics of an ideal multiplier.

FIG. 6 shows the overall circuit configuration of a four-quadrant analog multiplier using a cascode transistor whose source is grounded as an input circuit. When the input circuit consisting of a cascode transistor whose source is grounded is a constant current source drive and the input is a floating input, a differential operation is performed. Thus, the input voltage to the MOS multiplier core circuit is similar to that proposed by Wang. The overall circuit of the CMOS 4-quadrant multiplier shown in FIG. 4 has a smaller number of transistors than the multipliers proposed by Balt and Waringer and those proposed by Wang. Low voltage operation is also possible.

FIG. 7 shows an MO in the case where the source is grounded.
It shows a configuration of an S multiplier core circuit and a combination of input voltages thereof. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
The circuit of FIG. 7 differs from that of FIG. 1 in that each MOS transistor is driven by a constant current source or is grounded. The combination of the input voltages is the same as in FIG. The drain current of each transistor when the input voltage is applied as described above is expressed by the following equation.

(Equation 13)

The differential output current .DELTA.I of the source-grounded MOS multiplier core circuit is expressed by the following equation.

[Equation 14]

The conditions under which the transistor is cut off are as follows:
(V _X , V _Y ) differs in each quadrant, and the first quadrant (V _X > =
0, V _Y > = 0), no transistor is cut off. The DC voltage V _R of the input signal in the multiplier core circuit shown in FIG. 7 can be set arbitrarily. Also, each voltage of the input signal can be set to a range in which the transistor is not cut off by an appropriate attenuator. Therefore, equations (32) to (3)
From equation (6), the input voltage range is set to | V _X | + | V _Y | = <
Is set to _{(V R -V TH) / 2} , the transistor is not cut off at any quadrant. Equation (36a) expresses the differential output current characteristic when none of the transistors is cut off, and this equation has a linear transfer characteristic. That is, assuming a square characteristic of the MOS transistors, appropriately setting the DC voltage V _R and the input voltage range by using any of the transistors no cut-off area, it is possible to obtain an ideal multiplier characteristics it can.

FIG. 8 shows a region where each transistor is cut off with respect to the input voltage. The shaded portions in the figure indicate regions where none of the four transistors are cut off. Input voltage range of this shaded area, | it is expressed by _{= <(V R -V TH)} / 2 | V X | + | V Y. As the input voltage increases, the MO in the circuit
The S transistor starts to cut off, deviating from the ideal characteristics of the multiplier.

The transistors were expressed differential output current (36a) equation in case of no cutoff, Motomari trunk conductance characteristic is differentiated by V _X, it becomes the following equation.

(Equation 15) A similar result is obtained when the equation (36a) is differentiated by V _Y , and the multiplier core circuit has the same transconductance characteristic for both V _X and V _{Y in} the input voltage range where the transistor is not cut off. You can see that you have.

Next, a multiplier core circuit using bipolar transistors will be described.

FIG. 9 shows a configuration of a multiplier core circuit using bipolar transistors and a combination of input voltages thereof. The emitters of the first to fourth bipolar transistors 61 to 64 are commonly connected to each other and then grounded via a constant current source 65. Further, the first bipolar transistor 61 and the second
Collectors of the bipolar transistors 62 are commonly connected, their collector currents are added, and the output current I _L
It is 66. On the other hand, the collectors of the third bipolar transistor 63 and the fourth bipolar transistor 64 are also connected in common, and their collector currents are added.
The output current is I _R 67. The differential output current obtained by subtracting I _R from I _L is the output current of the multiplier core circuit. In this circuit, the first transistor 6
The first base voltage of V ₁ = V _X -V _Y is applied. The base of the second transistor 62 has V ₂ = 2
V _X is applied. Similarly, the third transistor 63
V ₃ = V _X , and the fourth transistor 64
₄ = 2V _X -V _Y is applied.

By substituting these voltages into equation (19),
The differential output current ΔI of the bipolar quadritail cell is obtained by the following equation.

(Equation 16) This is equal to equations (20) and (22). That is, it is equal to the well-known difference output current of the Gilbert multiplier cell. Generally, in a bipolar process, α _F ranges from 0.98 to 0.
99, which is close to "1". Therefore, such a combination of input voltages allows the bipolar quadruple retail cell to operate as a multiplier core circuit. Compared with the Gilbert multiplier cell, the transistor is not stacked vertically, so that low voltage operation is possible.

FIG. 10 shows the transfer characteristics of the bipolar multiplier core circuit according to the combination of the input voltages shown in FIG. Based on equation (38), V _Y
Is used as a parameter to express the transfer characteristic. V
_X is in the range of "0" about + -1 V _T around the, are substantially linear characteristics. Also, it can be seen that a large signal input has limiting characteristics due to the tail current.

[0054] Figure 11, the transfer characteristics shown in FIG. 10 V _X
5 shows transconductance characteristics when differentiated by. In this figure, V _Y is represented as a parameter. As can be seen from the figure, when V _X is near “0”, dΔI / dV _X is nearly flat. Therefore, it can be seen that a substantially linear characteristic is obtained as a multiplier. However, it can be seen that a completely linear characteristic is not obtained as in the MOS multiplier core circuit.

When the emitter of each transistor is grounded without being driven by the constant current source 65 as in the bipolar multiplier core circuit shown in FIG. The differential output current is represented by the following equation.

[Equation 17] As can be seen from this equation, when the source is grounded, the transfer characteristic cannot be called a multiplier core circuit. Therefore, when using a bipolar transistor, unless driven by a constant current source,
It cannot operate as a core circuit.

The combination of voltages to be applied to the source or gate of each transistor of the multiplier core circuit can be represented by the following general formula. _{V 1 = aV X + bV Y} (40a) V 2 = (a-c) V X + (b-1 / c) V Y (40b) V 3 = (a-c) V X + bV Y (40c) V 4 _{= aV X + (b-1} / c) V Y (40d) where, a, b, c are arbitrary integers, respectively. The following relationship holds between these equations. V ₁ −V ₃ = V ₄ −V ₂ = cV _X (41a) V ₁ −V ₄ = V ₃ −V ₂ = V _Y / c (41b) Each voltage of V _{1 to} V ₄ is applied to the gate of the MOS transistor. The drain current when applied is given by the following equation according to the square law.

(Equation 18)

Therefore, the output current ΔI of the multiplier core circuit is expressed by the following equation.

[Equation 19] As described above, when the current applied to the gate of each transistor has the relationship represented by the equation (40), the transistor operates as a multiplier.

FIG. 12 shows an outline of an input circuit of a multiplier core circuit for forming such four voltages. V ₁ is a voltage obtained by multiplying V _X by a and V _Y
Is b times the sum of the voltages. These can be configured by an active circuit using a transistor. When the coefficient on the right side of the equation (40) becomes negative, it is necessary to generate a voltage to be applied to the gate or base of each transistor of the multiplier core circuit by such an active circuit element. On the other hand, when the relations a> = c and b> = 1 / c are satisfied, V _X
And V _Y become positive, the addition can be performed by the resistance voltage dividing circuit, and the input circuit can be simplified.

[0059] Figure 13 shows the outline of the input circuit for generating four such voltages from the two input voltages V _X and V _Y. These internally divide V _X and V _Y at a partial pressure ratio corresponding to the coefficient in each equation. Here, a = 2, b = 1, c = 1, and V
Each ₁ ~V ₄ is expressed as follows. _{V 1 = 2V X + V Y} (44a) V 2 = V X (44b) V 3 = V X + V Y (44c) V 4 = 2V X (44d) where these equations Replacing 2V _X and V _X Is as follows. _{V 1 = V X + V Y} (45a) V 2 = V X / 2 (45b) V 3 = V X / 2 + V Y (45c) V 4 = V X (45d) relative relationship of V ₁ ~V ₄ is each The same is true even if the right side is halved, and can be modified as follows. _{V 1 = (V X + V} Y) / 2 (46a) V 2 = V X / 4 (46b) V 3 = (V X / 2 + V Y) / 2 (46c) V 4 = V X / 2 (46d)

FIG. 14 shows an outline of the configuration of a multiplier in which the input circuit is formed by a resistance voltage dividing circuit. The voltage V ₁ applied to the gate of the first transistor 71 is divided internally between V _X and V _Y by a resistor 72 and a resistor 73 at a voltage division ratio of 1: 1. Voltage applied to the gate of the second transistor 74, the first voltage-quarter of V _X is applied by a resistor 75 and the resistor 76.
Similarly, the voltage divided by the resistors 77 to 79 becomes the third voltage.
The resistor 82 and the resistor 8 are connected to the gate of the transistor 81 of FIG.
3 are applied to the gates of the fourth transistors 84, respectively. A constant voltage source for generating a voltage V _R 85 are those for causing the offset to be higher than the source voltage of the gate voltage of each transistor. The voltage applied to each gate corresponds to the voltage expressed by the equation (46), and it can be seen that the gate can be operated as a multiplier. Thus, (40)
In a voltage combination in which the coefficients on the right side of the equation are all positive, the input circuit of the multiplier core circuit can be constituted only by the voltage dividing circuit by the resistor, so that the circuit structure is simplified. In addition, since the input circuit can be constituted only by the resistors, there is no transistor stacked vertically, and the operation can be started from a low voltage.

Here, the MOS transistor has been described, but when these voltages are applied to each base of a multiplier core circuit constituted by bipolar transistors driven by a common tail current, the circuit operates as a multiplier. Needless to say. That is,
By substituting the four voltages in equation (40) into equation (19), the differential output current of the bipolar quadratic cell becomes the same as equation (38).

[0062] In four-quadrant multiplier, the input voltage -V _X, the output current as -V _Y is V _X V _Y becomes not intended operation of the multiplier is limited by the positive and negative input voltages. Further, when only one of V _X and V _Y is negative, positive and negative output current change places. However, the place you are I _L -I _R a [Delta] I, the way of taking the difference in the opposite, i.e. [Delta] I = I _R if -I _L, V _X and V _Y are both positive if the same output current Can be obtained. Further, V _X and V _Y are each _reduced by half.
Even if it is added, the multiplication characteristic as a multiplier does not change only by reducing the output current to a quarter. Of course, if only one of V _X and V _Y is reduced to one half, the output current will only be reduced to one half and the multiplication characteristics will not change. Therefore, even if the input voltage is reduced to one half by the resistance voltage dividing circuit and applied to each transistor, the transistor naturally operates as a multiplier.

[0063]

According to the invention of claim 1, wherein, as described in the foregoing, when the two input voltages to be multiplied was set to _{V X, V Y, V X} + V Y, -V X + V Y, V X + V _Y / 2,
Is converted to a combination of -V _X + V _Y / 2 applies a voltage to each transistor. As a result, a multiplier core circuit having excellent linearity and capable of operating at a low voltage can be obtained. Further, the scale of an input circuit for converting an input voltage to be multiplied can be reduced. Furthermore, if one of the input voltages is used as a signal for controlling the gain, it can be used as an AGC (Auto Gain Control) circuit because it has a predetermined limiting characteristic. When used as an ODA circuit, the circuit configuration of the input circuit can be reduced.

According to the second aspect of the present invention, the MOS
The source or the ground can be grounded because the multiplier core circuit is formed using transistors of the type or field effect type. This eliminates the need for a constant current source and can reduce the circuit scale. Further, the input voltage range can be widened.

According to the third or fourth aspect of the present invention, when two input voltages to be multiplied are V _X and V _Y , (V _X + V _Y ) / 2, V _X / 4, ( V _X + 2V
_Y) / 4, is converted to a combination of V _X / 2 applies a voltage to each transistor. As a result, a multiplier core circuit having excellent linearity and capable of operating at a low voltage can be obtained. Further, since the four voltages are a combination of a positive multiple of the input voltage, they can be easily converted to these voltages, and the scale of the input circuit can be reduced.

According to the fifth aspect of the present invention, the voltage applied to the gate or source of each transistor is
It is generated by a resistance voltage dividing circuit. Since each of the four voltages is constituted by a combination of a positive multiple of V _X and V _Y , these voltages can be generated by the resistance voltage dividing circuit, and the input circuit can be simplified.
In addition, there is no transistor stacked vertically, and operation can be performed from a low voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a MOS multiplier core circuit and a combination of input voltages thereof in an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing input / output characteristics of the MOS multiplier core circuit shown in FIG.

FIG. 3 is a characteristic diagram showing a transconductance characteristic of the MOS multiplier core circuit shown in FIG.

FIG. 4 is a circuit diagram showing an example of a circuit configuration of the entire multiplier using the MOS multiplier core circuit shown in FIG.

FIG. 5: Multiplier with input floating
FIG. 4 is a characteristic diagram illustrating a normal operation range of the core circuit.

FIG. 6 is a circuit diagram showing another example of a circuit configuration of the entire multiplier using the MOS multiplier core circuit shown in FIG.

FIG. 7 is a circuit diagram showing a configuration of a MOS multiplier core circuit whose source is grounded and a combination of input voltages thereof.

8 is a characteristic diagram showing an ideal operation input voltage range of the MOS multiplier core circuit shown in FIG.

FIG. 9 is a circuit diagram showing a configuration of a bipolar multiplier core circuit and a combination of input voltages thereof.

FIG. 10 shows a bipolar multiplier shown in FIG.
FIG. 3 is a characteristic diagram illustrating input / output characteristics of a core circuit.

FIG. 11 shows a bipolar multiplier shown in FIG.
FIG. 4 is a characteristic diagram illustrating a transconductance characteristic of a core circuit.

FIG. 12 is a block diagram showing an outline of a configuration of an input circuit of the multiplier core circuit.

FIG. 13 is a circuit diagram showing an input circuit constituted by a voltage dividing circuit using resistors.

FIG. 14 is a circuit diagram illustrating a configuration of a multiplier using a voltage dividing circuit including resistors as an input circuit.

FIG. 15 is a circuit diagram showing a configuration of a MOS multiplier core circuit having a floating input.

FIG. 16 is a circuit diagram showing a configuration of a MOS multiplier core circuit whose source is grounded.

FIG. 17 is a circuit diagram showing a configuration of a conventionally used MOS multiplier core circuit having a floating input proposed by Balut and Warringer and a combination of input voltages thereof.

FIG. 18 is a circuit diagram showing the configuration of a conventionally used grounded MOS multiplier core circuit proposed by Balut and Warringer and a combination of input voltages thereof.

FIG. 19 is a circuit diagram showing a configuration of a conventionally used MOS multiplier core circuit having a floating input and a combination of input voltages thereof, re-proposed by Wang.

FIG. 20 is a circuit diagram showing a configuration of a conventionally used MOS multiplier core circuit with a grounded source proposed by Wu and Stuman and a combination of input voltages thereof.

FIG. 21 is a circuit diagram showing a configuration of a bipolar multiplier core circuit having a floating input.

FIG. 22: MOS proposed by Balt and Waringah
FIG. 3 is a circuit diagram illustrating a configuration of a multiplier core circuit in which the multiplier core circuit is replaced with a bipolar transistor and a combination of input voltages thereof.

FIG. 23 is a circuit diagram showing a configuration of a multiplier core circuit in which a MOS multiplier core circuit re-proposed by Wan is replaced with a bipolar transistor and a combination of input voltages thereof;

[Explanation of symbols]

 11 to 14 MOS transistors 15, 55 Constant current sources 16, 17, 56, 57 Output currents 51, 52, 53, 54 Bipolar transistors 72, 73, 81 Resistors

Claims (5)

(57) [Claims] A first transistor having a gate or a base to which a sum signal of a reverse phase signal of the first voltage signal and the second voltage signal is input, and a voltage signal twice as large as the first voltage signal And a second transistor whose drain or collector is commonly connected to the drain or collector of the first transistor, and the first voltage signal is input to its gate or base. A third transistor, a sum signal of a voltage signal twice as large as the first voltage signal and a reverse phase signal of the second voltage signal is input to its gate or base, and its drain or collector is A fourth transistor commonly connected to a drain or a collector of the third transistor, and the first to fourth transistors. Multiplier core circuit, characterized by comprising a constant current source for driving the static in common tail current. 2. A MOS-type or field-effect-type first transistor having a gate to which a sum signal of a reverse phase signal of the first voltage signal and the second voltage signal is input and whose source is grounded, Of which the voltage signal is twice the voltage signal of the first transistor is input to the gate thereof, the source is grounded, and the drain is commonly connected to the drain of the first transistor.
An S-type or field-effect type second transistor; a MOS-type or field-effect type third transistor whose gate receives the first voltage signal and whose source is grounded; A sum signal of a voltage signal of twice the magnitude and a reverse phase signal of the second voltage signal is input to its gate and grounded at its source, and its drain is commonly connected to the drain of the third transistor. MOS
And / or a field effect type fourth transistor. 3. A sum signal of a voltage signal of a half of the first voltage signal and a voltage signal of a half of the second voltage signal is inputted to its gate or base. First
And a voltage signal of a quarter of the first voltage signal is input to its gate or base, and its drain or collector is commonly connected to the drain or collector of the first transistor. A second transistor, a sum signal of a voltage signal having a magnitude of a quarter of the first voltage signal and a voltage signal having a magnitude of a half of the second voltage signal is applied to its gate or base. An input third transistor and a voltage signal having a magnitude half that of the first voltage signal are input to a gate or a base thereof, and a drain or a collector thereof is connected to a drain or a drain of the third transistor. A fourth transistor commonly connected to a collector, and a constant current source for driving the first to fourth transistors with a common tail current And a multiplier core circuit. 4. A sum signal of a voltage signal having a magnitude of a half of the first voltage signal and a voltage signal having a magnitude of a half of the second voltage signal is inputted to its gate and the source is grounded. A MOS-type or field-effect-type first transistor, and a voltage signal having a magnitude of a quarter of the first voltage signal is input to its gate and grounded at its source, and its drain is connected to the first transistor. A MOS-type or field-effect-type second transistor commonly connected to the drains of the first and second transistors, and a voltage signal of a quarter of the first voltage signal and a half of the second voltage signal. A MOS whose input signal is a sum signal of voltage signals of magnitude 1 and whose source is grounded
Or a third transistor of a field-effect type, a voltage signal having a magnitude half of the first voltage signal is input to its gate and grounded at its source, and its drain is connected to the third transistor. And a fourth transistor of a MOS type or a field effect type commonly connected to a drain of the multiplier.
Core circuit. 5. A voltage applied to a gate or a base of the first transistor is a first resistance component which internally divides the first voltage signal and the second voltage signal at a one-to-one voltage dividing ratio. The voltage generated by the voltage circuit and applied to the gate or the base of the second transistor is a second resistor voltage divider that internally divides the first voltage signal and the ground potential at a voltage division ratio of 3: 1. A voltage generated by the circuit and applied to the gate or base of the third transistor internally divides the voltage between the first voltage signal and the ground potential at a one-to-one voltage dividing ratio. And a voltage applied to the gate or base of the fourth transistor is connected to one end of a first resistor to which a first voltage signal is applied, and the other end of the first resistor is connected to one end of the first resistor. And a second voltage signal at the other end The second resistor, which is applied and whose resistance is half of the first resistor, has one end connected to a connection point between the first resistor and the second resistor and the other end grounded at the other end. 5. A voltage appearing at a connection point between a first resistor and a second resistor of a fourth resistor voltage dividing circuit having a third resistor equal to the first resistor. Multiplier core circuit.