JP3022731B2 - Adder and subtractor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder and a subtracter for adding and subtracting two analog signals, and more particularly to a bipolar transistor and an M transistor formed on a semiconductor integrated circuit.
The present invention relates to an adder and a subtractor including OS transistors.

[0002]

2. Description of the Related Art In analog signal processing, an adder and a subtractor are indispensable function blocks. However, in recent years, integrated circuits have become ultra-miniaturized. The voltage has been reduced to 0.3 V or 3 V, and the need for low voltage circuit technology has been further increased.

Also, since the CMOS process has been widely accepted as the most suitable process for LSI, a circuit technique for realizing a multiplier by the CMOS process is required.

[0004]

Therefore, the present inventor (Kimura) proposed an adder and a subtracter capable of operating at a low voltage and widening the input voltage range with good linearity. -210683). In this configuration, as shown in FIG. 5 (adder) and FIG. 6 (subtractor), the output terminals are commonly connected so that the output currents of the two differential pairs are added or subtracted. It has been found that a different configuration can be obtained as an adder and a subtracter using two differential pairs.

The present invention has been made based on such knowledge, and an object of the present invention is to provide an adder and a subtracter capable of operating at a low voltage and widening the input voltage range with good linearity. It is in.

[0006]

Means for Solving the Problems In order to achieve the above object, an adder and a subtractor according to the present invention have the following configurations. That is, the adder according to the first invention includes a first bipolar transistor pair to which a first signal having a half of the first input voltage is differentially input, and a second signal having a half of the second input voltage being a differential signal. A second bipolar transistor pair for inputting, and a common current source for driving the pair of bipolar transistors; emitters of four bipolar transistors of the first bipolar transistor pair and the second bipolar transistor pair are commonly connected; , the collector of the transistors on the side of the same polarity signals between each other the first bipolar transistor pair and a second bipolar transistor pairs are inputted are commonly connected, those characterized that you configure the differential output pair It is.

In the subtractor according to the second invention, a first bipolar transistor pair to which a first signal having a half of the first input voltage is differentially inputted and a second signal having a half of the second input voltage are different. A second bipolar transistor pair for inputting the current and a common current source for driving the pair, and the emitters of the four bipolar transistors of the first and second bipolar transistor pairs are connected in common. together, the collector of the transistors on the side opposite polarity signals between each other the first bipolar transistor pair and a second bipolar transistor pair inputs are connected in common, characterized that you configure the differential output pair Things.

In the adder according to the third invention, the first MOS transistor pair to which the first signal having a half of the first input voltage is differentially inputted and the second signal having a half of the second input voltage are different. A second MOS transistor pair for inputting the current and a common current source for driving the second MOS transistor pair, and the emitters of the four MOS transistors of the first MOS transistor pair and the second MOS transistor pair are commonly connected. With the first M
Collectors each other OS transistor pair and the side of the transistor the same polarity signals between each other the second MOS transistor pair is input is commonly connected and is characterized that you configure the differential output pair.

In a subtractor according to a fourth aspect of the present invention, the first MOS transistor pair to which the first signal having a half of the first input voltage is differentially inputted and the second signal having a half of the second input voltage are different. A second MOS transistor pair for inputting the current and a common current source for driving the second MOS transistor pair, and the emitters of the four MOS transistors of the first MOS transistor pair and the second MOS transistor pair are commonly connected. With the first M
Collectors each other OS transistor pair and the side of the transistor opposite polarity signal is input between each other the second MOS transistor pair are connected in common and is characterized that you configure the differential output pair.

[0010]

Next, the operation of the adder and the subtracter of the present invention configured as described above will be described. According to the present invention, in a quadritail cell in which the emitters or sources of four transistors constituting two pairs of transistors are connected in common and driven by a common current source, between the bases or gates of each of the two pairs of transistors. An adder and a subtractor are configured by differentially inputting the first signal and the second signal therebetween, and connecting the collector or drain of the output pair in common so that the output current is added or subtracted.

Therefore, the input voltage range with good linearity can be widened. Further, since the two transistor pairs are arranged in a horizontal row, low-voltage operation is possible.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an adder according to a first embodiment of the present invention. This adder is constituted by a bipolar transistor, and receives a first signal (voltage V ₁ ) to which a first signal (voltage V ₁ ) is differentially input.
Bipolar transistor pair (Q1, Q2) and a second bipolar transistor pair (Q
3, Q4) and comprises a common current source I ₀ which drives them.

A first bipolar transistor pair (Q1,
In Q2), on the basis of the certain direct current voltage (V _R) positive polarity of the input voltage (V _1/2) is applied to the base of Q1, the base of the negative polarity of the input voltage (-V _1/2) is Q2 Applied. Similarly, the second bipolar transistor pair (Q3,
In Q4), is applied to a base of the DC voltage (V _R) reference to the positive polarity of the input voltage (V _1/2) is Q3, the base of the negative polarity of the input voltage (-V _1/2) is Q4 Applied.

The transistors (Q1 and Q1) on the side to which signals of the same polarity are input between the first bipolar transistor pair and the second bipolar transistor pair
3) The collectors of the same (Q2 and Q4) are commonly connected to form a differential output pair.

Assuming that the matching between the elements is good and ignoring the base width modulation, four transistors (Q1, Q2,
The collector currents (I _C1 , I _C2 , I _C3 , I _C4 ) of each transistor constituting a quadritail cell in which Q 3 and Q 4) are driven by one constant current source I ₀ are expressed by the following equation (1). Where I _S is the saturation current of the transistor,
V _R is the DC voltage of the input signal, and V _A is the common emitter voltage of the quad tail cells. V _T is a thermal voltage, and is expressed as V _T = kT / q using Boltzmann constant k, absolute temperature T, and unit electron charge q.

[0016]

(Equation 1)

Further, the tail current of the quadritail cell, so be expressed by Equation 2, the common term I _S exp included in the formula of the collector current _{{(V R -V A) /} V T} is formula Equation 1 is solved by solving Equation 1. In Equation 2, α is a DC current amplification factor.

[0018]

## EQU2 ## I _C1 + I _C2 + I _C3 + I _C4 = α _F I ₀

[0019]

(Equation 3)

Accordingly, the differential output current ΔI ⁺ {= (I _C1 + I _C3 ) − (I _C2 + I _C4 )} of the bipolar adder is given by the following equation ( ₄ ).
Indicated by

[0021]

(Equation 4)

As can be seen from Equation 4, the bipolar adder is standardized at 4 V _T with respect to the sum voltage of the two signals, and is twice as large as that of the matched differential pair. Therefore, an adder with relatively good linearity can be obtained.

FIG. 2 shows a subtractor according to a second embodiment of the present invention. This subtractor is formed of a bipolar transistor, and a first bipolar transistor pair (Q1, Q2) to which a first signal (voltage V ₁ ) is differentially input.
When and a common current source I ₀ second signal for driving them and the second bipolar transistor pair input differential (Q3, Q4).

The first bipolar transistor pair (Q1,
In Q2), on the basis of the certain direct current voltage (V _R) positive polarity of the input voltage (V _1/2) is applied to the base of Q1, the base of the negative polarity of the input voltage (-V _1/2) is Q2 Applied. Similarly, the second bipolar transistor pair (Q3,
In Q4), is applied to a base of the DC voltage (V _R) reference to the positive polarity of the input voltage (V _1/2) is Q3, the base of the negative polarity of the input voltage (-V _1/2) is Q4 Applied.

Then, transistors (Q1 and Q1) on the side to which signals of opposite polarities are inputted between the first bipolar transistor pair and the second bipolar transistor pair.
4) The same (Q2 and Q3) collectors are commonly connected to form a differential output pair.

The differential output current ΔI of the bipolar subtractor
⁻ {= (I _C1 + I _C4 ) − (I _C2 + I _C3 )} is expressed by Expression 5 using the above-described result, and a subtracter having relatively good linearity can be obtained.

[0027]

(Equation 5)

FIG. 3 shows an adder according to a third embodiment of the present invention. This adder is a MOS adder in which the bipolar transistor of the first embodiment is replaced by a MOS transistor.

Assuming that the matching between the elements is good on the same chip, and neglecting the gate width modulation and the body effect, the relationship between the drain current and the gate-source voltage of the MOS transistor operating in the saturation region is squared. According to the rules, the drain currents (I _D1 , I _D2 , I _D3 , I _D4 ) of each of the MOS transistors constituting the quadritail cell are expressed by Expressions 6, 7, 8, and 9. Where Equation 6
In Expression 9, β is a transconductance parameter, and β = μ (C _OX / 2) (effective mobility μ of carrier, gate oxide film capacitance C _OX per unit area, gate width W, gate length L) W / L). V _A is the common source voltage of the quad tail cell, V _TH
Is the threshold voltage.

[0030]

(Equation 6)

[0031]

(Equation 7)

[0032]

(Equation 8)

[0033]

(Equation 9)

The tail current can be expressed by the following equation (10).

[0035]

## EQU10 ## I _D1 + I _D2 + I _D3 + I _D4 = I ₀

By solving equations (6) to (10), the differential output current ΔI ⁺ ｛of the MOS adder = (I _D1 + I _D4 ) − (I _D2 + I
_D3 )｝ can be expressed as Equation 11.

[0037]

[Equation 11]

From equation 11, it can be seen that, like the bipolar adder, the adder has relatively good linearity.

FIG. 4 shows a subtractor according to a fourth embodiment of the present invention. This subtractor is a MOS subtractor in which the bipolar transistor of the second embodiment is replaced by a MOS transistor.

The differential output current ΔI ⁻ of this MOS subtractor
{= ( _ID1 + _ID3 )-( _ID2 + _ID4 )} can be expressed as Expression 12. It can be seen that, like the bipolar subtractor, the subtractor is relatively linear.

[0041]

(Equation 12)

Since the two differential pairs are arranged in a horizontal row, it can be understood that low voltage operation is possible.

[0043]

As described above, in the adder and the subtracter of the present invention, the emitters or the sources of the four transistors constituting the two transistor pairs are connected in common and driven by the common current source. In the quad tail cell,
A first signal and a second signal are differentially input between bases or gates of two pairs of transistors, and an output pair is added by commonly connecting collectors or drains so that an output current is added or subtracted. And a subtractor. Therefore, there is an effect that an adder and a subtracter which can widen the input voltage range with good linearity and operate at a low voltage can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a bipolar adder according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a bipolar subtractor according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a MOS adder according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a MOS subtractor according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional MOS adder.

FIG. 6 is a circuit diagram of a conventional MOS subtractor.

[Explanation of symbols]

I ₀ constant current source M1 to M4 MOS transistor Q1 to Q4 bipolar transistor

Claims (5)

(57) [Claims] 1. A first bipolar transistor pair to which a first signal having a half of a first input voltage is differentially inputted, and a second bipolar transistor to which a second signal having a half of a second input voltage is differentially inputted. A bipolar transistor pair and a common current source for driving the bipolar transistor pair, wherein the emitters of four bipolar transistors of the first bipolar transistor pair and the second bipolar transistor pair are connected in common, and the first bipolar transistor pair is connected to the first bipolar transistor pair. Between the transistor pair and the second bipolar transistor pair, the collectors of the transistors to which signals of the same polarity are input are commonly connected, and the differential output pair is connected .
Adder characterized that you configure. 2. A first bipolar transistor pair to which a first signal having a half of the first input voltage is differentially inputted, and a second bipolar transistor having a second signal having a half of the second input voltage being differentially inputted. A bipolar transistor pair and a common current source for driving the bipolar transistor pair, wherein the emitters of four bipolar transistors of the first bipolar transistor pair and the second bipolar transistor pair are connected in common, and the first bipolar transistor pair is connected to the first bipolar transistor pair. Between the transistor pair and the second bipolar transistor pair, the collectors of the transistors to which signals of opposite polarities are input are commonly connected, and the differential output pair is
Subtractor characterized that you configure. 3. A first MOS transistor pair to which a first signal having a half of the first input voltage is differentially inputted, and a second MOS transistor having a second signal having a half of the second input voltage being differentially inputted. A pair of MOS transistors and a common current source for driving the pair of MOS transistors;
The emitters of the four MOS transistors of the transistor pair are connected in common, and the collectors of the transistors to which signals of the same polarity are input between the first MOS transistor pair and the second MOS transistor pair are connected in common. adder characterized that you configure the differential output pair. 4. A first MOS transistor pair to which a first signal having a half of the first input voltage is differentially inputted, and a second MOS transistor having a second signal having a half of the second input voltage being differentially inputted. A pair of MOS transistors and a common current source for driving the pair of MOS transistors;
The emitters of the four MOS transistors of the transistor pair are commonly connected, and the collectors of the transistors on the side to which signals of opposite polarities are input between the first MOS transistor pair and the second MOS transistor pair are commonly connected. subtractor characterized that you configure the differential output pair. 5. A first bipolar transistor pair to which a first signal having a half of the first input voltage is differentially inputted, and a second bipolar transistor having a second signal having a half of the second input voltage being differentially inputted. The first bipolar transistor pair and the second bipolar transistor pair are connected in common with each other, and the first bipolar transistor pair and the second bipolar transistor pair are connected in common. Between the bipolar transistor pair and the second bipolar transistor pair, the collectors of the transistors to which signals having the same polarity are input are commonly connected ,
Adder characterized that you configure the differential output pair.