JPH0836616A - Adder and subtractor - Google Patents

Abstract

PURPOSE:To provide an adder and a subtractor in which an input voltage range is widened with excellent linearity and which are operated at a low voltage. CONSTITUTION:Figure indicates a MOS adder. Sources (emitters) of four transistors (TRs) forming two-sets of TR pairs (M1, M2) (M3, M4) are connected in common. In a quadri-tail cell driven by a common current source I0, a 1st signal (voltage V1) and a 2nd signal (voltage V2) are given differentially between gates (bases) of the two sets of TR pairs, and drains (collectors) are connected in common by adding or subtracting output currents at the output pairs to form the adder and subtractor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder and a subtractor for adding and subtracting two analog signals, and more particularly to a bipolar transistor and an M formed on a semiconductor integrated circuit.
The present invention relates to an adder and a subtractor configured with OS transistors.

[0002]

2. Description of the Related Art In analog signal processing, an adder and a subtracter are indispensable function blocks. Recently, however, as integrated circuits have become ultra-fine, the power supply voltage of the integrated circuits has changed from 5V to 3V. The voltage has been reduced to 3 V or 3 V, and the need for low-voltage circuit technology is further increasing.

Since the CMOS process has been widely recognized as an optimum process for LSI, circuit technology for realizing a multiplier in the CMOS process is required.

[0004]

Therefore, the present inventor (Kimura) has proposed an adder and a subtracter capable of operating at a low voltage and widening the input voltage range with good linearity (Japanese Patent Laid-Open No. HEI 3). -210683). As shown in FIG. 5 (adder) and FIG. 6 (subtractor), this one has a configuration in which output terminals are commonly connected so that output currents of two differential pairs are added or subtracted. It has been found that an adder and a subtracter using two differential pairs can have different configurations.

The present invention has been made on the basis of such knowledge, and an object thereof is to provide an adder and a subtracter capable of operating at a low voltage and widening an input voltage range having good linearity. It is in.

[0006]

In order to achieve the above object, an adder and a subtractor of the present invention have the following configurations. That is, the adder of the first invention comprises a first bipolar transistor pair to which the first signal is differentially input; and a second bipolar transistor pair to which the second signal is differentially input;
A common current source for driving them, and the collectors of the transistors on the side to which signals of the same polarity are input are commonly connected between the first bipolar transistor pair and the second bipolar transistor pair. It is characterized by.

The subtractor of the second invention comprises a first bipolar transistor pair to which a first signal is differentially input; a second bipolar transistor pair to which a second signal is differentially input;
A common current source for driving them, and the collectors of the transistors on the side to which signals of opposite polarities are input between the first bipolar transistor pair and the second bipolar transistor pair are commonly connected. It is characterized by.

An adder according to a third aspect of the present invention includes a first MOS transistor pair to which a first signal is differentially input; a second MOS transistor pair to which a second signal is differentially input; And a drain of a transistor on the side to which a signal of the same polarity is input is commonly connected between the first MOS transistor pair and the second MOS transistor pair. Is.

A subtractor according to a fourth aspect of the present invention includes a first MOS transistor pair to which a first signal is differentially input; a second MOS transistor pair to which a second signal is differentially input; And the drains of transistors on the side to which signals of opposite polarity are input are commonly connected between the first MOS transistor pair and the second MOS transistor pair. Is.

[0010]

Next, the operation of the adder and subtracter of the present invention constructed as described above will be described. According to the present invention, in the quadritail cell in which the emitters or sources of the four transistors forming the two pairs of transistors are commonly connected and driven by a common current source, the base or gate of each of the two pairs of transistors is connected. A first signal and a second signal are differentially input between them, and an adder and a subtractor are configured by connecting the output pair to the collector or drain in common so that the output current is added or subtracted.

Therefore, the input voltage range with good linearity can be widened. Further, since the two transistor pairs are arranged in a horizontal row, low voltage operation is possible.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an adder according to the first embodiment of the present invention. This adder is composed of bipolar transistors, and has a first signal (voltage V ₁ ) to which a first signal is differentially input.
Second bipolar transistor pair (Q1, Q2) and a second bipolar transistor pair (Q
3, Q4) and a common current source I ₀ that drives them.

The first bipolar transistor pair (Q1,
In Q2), on the basis of the certain direct current voltage (V _R) positive polarity of the input voltage (V _1/2) is applied to the base of Q1, the base of the negative polarity of the input voltage (-V _1/2) is Q2 Is applied. Similarly, the second bipolar transistor pair (Q3,
In Q4), is applied to a base of the DC voltage (V _R) reference to the positive polarity of the input voltage (V _1/2) is Q3, the base of the negative polarity of the input voltage (-V _1/2) is Q4 Is applied.

Then, between the first bipolar transistor pair and the second bipolar transistor pair, the transistors (Q1 and Q1) on the side to which signals of the same polarity are input.
3), collectors of the same (Q2 and Q4) are commonly connected to form a differential output pair.

Assuming good matching between elements and ignoring base width modulation, four transistors (Q1, Q2,
The collector currents (I _C1 , I _C2 , I _C3 , I _C4 ) of the respective transistors forming the quadritail cell in which Q3 and Q4) are driven by one constant current source I ₀ are represented by Formula 1. However, in Equation 1, I _S is the saturation current of the transistor,
V _R is the DC voltage of the input signal and V _A is the common emitter voltage of the quadritail cell. V _T is a thermal voltage, which is expressed as V _T = kT / q using the Boltzmann constant k, the absolute temperature T, and the unit electronic charge q.

[0016]

[Equation 1]

Further, since the tail current of the quadritail cell is expressed by Equation 2, the common term I _S exp {(V _R −V _A ) / V _T } included in the equation of collector current is Equation 3 is solved by solving 1 and Equation 2. In Equation 2, α is a direct current amplification factor.

[0018]

[Expression 2] I _C1 + I _C2 + I _C3 + I _C4 = α _F I ₀

[0019]

(Equation 3)

Therefore, the differential output current ΔI ⁺ of the bipolar adder {= (I _C1 + I _C3 ) − (I _C2 + I _C4 )} is expressed by the equation 4
Indicated by.

[0021]

[Equation 4]

As can be seen from Equation 4, in this bipolar adder, the sum voltage of the two signals is standardized at 4V _T , which is twice as large as that of the matched differential pair. Therefore, an adder having relatively good linearity can be obtained.

Next, FIG. 2 shows a subtracter according to a second embodiment of the present invention. This subtractor is composed of bipolar transistors, and a first bipolar transistor pair (Q1, Q2) to which a first signal (voltage V ₁ ) is differentially input.
And a second bipolar transistor pair (Q3, Q4) to which the second signal is differentially input, and a common current source I ₀ for driving them.

The first bipolar transistor pair (Q1,
In Q2), on the basis of the certain direct current voltage (V _R) positive polarity of the input voltage (V _1/2) is applied to the base of Q1, the base of the negative polarity of the input voltage (-V _1/2) is Q2 Is applied. Similarly, the second bipolar transistor pair (Q3,
In Q4), is applied to a base of the DC voltage (V _R) reference to the positive polarity of the input voltage (V _1/2) is Q3, the base of the negative polarity of the input voltage (-V _1/2) is Q4 Is applied.

Then, between the first bipolar transistor pair and the second bipolar transistor pair, the transistors (Q1 and Q1) on the side to which signals of opposite polarities are input.
4) and collectors of the same (Q2 and Q3) are commonly connected to form a differential output pair.

Differential output current ΔI of this bipolar subtractor
^- {= (I _C1 + I _C4 )-(I _C2 + I _C3 )} is expressed by the equation 5 using the above-mentioned result, and a subtracter with relatively good linearity can be similarly obtained.

[0027]

(Equation 5)

Next, FIG. 3 shows an adder according to a third embodiment of the present invention. This adder is a MOS adder in which the bipolar transistor of the first embodiment is replaced with a MOS transistor.

Assuming that the matching between the elements is good on the same chip, and ignoring the gate width modulation and the substrate effect, the relation between the drain current and the gate-source voltage of the MOS transistor operating in the saturation region is squared. According to the rule, the drain currents (I _D1 , I _D2 , I _D3 , I _D4 ) of the MOS transistors forming the quadritail cell are represented by Formula 6, Formula 7, Formula 8, and Formula 9. However, Equation 6
In Equation 9, β is a transconductance parameter, and β = μ (C _OX / 2) (as the effective mobility μ of carriers, the gate oxide film capacitance C _OX per unit area, the gate width W, and the gate length L. W / L). V _A is the common source voltage of the quadritail cell, V _TH
Is the threshold voltage.

[0030]

(Equation 6)

[0031]

(Equation 7)

[0032]

(Equation 8)

[0033]

[Equation 9]

Further, the tail current can be expressed by equation 10.

[0035]

[Equation 10] I _D1 + I _D2 + I _D3 + I _D4 = I ₀

Solving the equations 6 to 10, the differential output current ΔI ⁺ {= (I _D1 + I _D4 )-(I _D2 + I of the MOS adder is obtained.
_D3 )} can be expressed as Equation 11.

[0037]

[Equation 11]

From Equation 11, it can be seen that the adder has a relatively good linearity, like the bipolar adder.

Next, FIG. 4 shows a subtracter according to a fourth embodiment of the present invention. This subtractor is a MOS subtractor in which the bipolar transistor of the second embodiment is replaced with a MOS transistor.

Differential output current ΔI ⁻ of this MOS subtractor
{= (I _D1 + I _D3 ) − (I _D2 + I _D4 )} can be expressed as Formula 12. As with the bipolar subtractor, it can be seen that the subtractor has relatively good linearity.

[0041]

(Equation 12)

It should be noted that the two differential pairs are arranged in a horizontal row, so that it can be understood that low voltage operation is possible.

[0043]

As described above, in the adder and the subtracter of the present invention, the emitters or sources of the four transistors forming the two transistor pairs are commonly connected and driven by a common current source. In the Quadritail Cell,
The first signal and the second signal are differentially input between the bases or gates of two pairs of transistors, and the output pair is added by commonly connecting the collectors or drains so that the output current is added or subtracted. And subtractor. Therefore, there is an effect that an input voltage range with good linearity can be widened and an adder and a subtracter capable of low voltage operation can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a bipolar adder according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a bipolar subtractor according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a MOS adder according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a MOS subtractor according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional MOS adder.

FIG. 6 is a circuit diagram of a conventional MOS subtractor.

[Explanation of symbols]

I ₀ constant current source M1 to M4 MOS transistor Q1 to Q4 bipolar transistor

Claims (4)

[Claims] 1. A first bipolar transistor pair to which a first signal is differentially input; a second bipolar transistor pair to which a second signal is differentially input; and a common current source for driving them. An adder, characterized in that the collectors of the transistors to which signals of the same polarity are input are commonly connected between the first bipolar transistor pair and the second bipolar transistor pair. 2. A first bipolar transistor pair to which a first signal is differentially input; a second bipolar transistor pair to which a second signal is differentially input; and a common current source for driving them. The collector of the first bipolar transistor pair and the collector of the transistor on the side to which the signal of the opposite polarity is input are commonly connected between the second bipolar transistor pair and the second bipolar transistor pair. 3. A first MOS for differentially inputting a first signal.
A transistor pair; and a second M to which the second signal is differentially input
An OS transistor pair; and a common current source for driving them; and the drains of the transistors on the side to which signals of the same polarity are input between the first MOS transistor pair and the second MOS transistor pair are common. Connected; an adder characterized in that. 4. A first MOS for differentially inputting a first signal.
A transistor pair; and a second M to which the second signal is differentially input
An OS transistor pair; and a common current source that drives them; and the drains of the transistors on the side to which signals of opposite polarity are input between the first MOS transistor pair and the second MOS transistor pair are common. Connected; a subtractor.