JP2551386B2 - Multiplier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for multiplying two analog signals, and more particularly to a 2-quadrant and 4-quadrant multiplier composed of MOS transistors formed on a semiconductor integrated circuit.

[0002]

2. Description of the Related Art As a two-quadrant analog multiplier, the one shown in FIG. 5 proposed by J. Mavor, for example, is conventionally known. This is based on the document "IEE Electronic
s letter, 13 (1977) ", pages 373 to 374.

As a four-quadrant analog multiplier, the one shown in FIG. 6 is conventionally known. This is a two quadrant analog multiplier of Maeba, which has four quadrants by cross-connecting the input and output.
ge) and Cappon (Proceedings of the Japan Society of Applied Physics 1979 11th Proceedings V _O l.19, Supplement19-
1, pp.265-268 (1980)).

[0004]

By the way, in analog signal processing, a multiplier is an indispensable function block, but recently, as the integrated circuits have become ultra-miniaturized, the power supply voltage of the integrated circuits has also increased. 5V
From 3.3V to 3V or 3V,
The need for low voltage circuit technology is ever increasing.

Since the CMOS process has been widely recognized as an optimum process for LSI, a circuit technique for realizing a multiplier in the CMOS process is required.

However, the conventional multiplier cannot operate at a low voltage in principle and has a circuit limitation. In the MOS, as described above, Mavor's two-quadrant analog multiplier is made into four quadrants by Sage and Cappon.
The second input voltage (V _y + v _{y in} FIG. 5), which does not depend on the average application method, must be applied by a low impedance voltage source, resulting in low voltage, low current consumption, and high frequency. There is a problem that is difficult.

It is an object of the present invention to provide a two-quadrant and four-quadrant multiplier capable of lowering the voltage, reducing the current consumption, increasing the frequency, and widening the input voltage range with good linearity. .

[0008]

In order to achieve the above object, the multiplier of the present invention has the following constitution. That is, the multiplier of the first invention is a triple tail cell in which three MOS transistors are driven by a common constant current source; the first signal is differentially input to and output from the first and second MOS transistors. The ends make up the output pair;
The second signal is input to the third MOS transistor, and a constant current source is interposed between the output terminal and the power source;

The multiplier of the second invention is the first invention.
The output pair comprises two of the multipliers of the invention; the output pairs are mutually connected in common to form a differential output pair, and the first signal is the first and second multipliers of the two multipliers. The differential signal is commonly input to the MOS transistors, and the second signal is differentially input to the third MOS transistors of the two multipliers.

In the multiplier of the second invention, 2
The output terminals of the third MOS transistors are commonly connected, and a common constant current source may be interposed between the power supplies.

[0011]

Next, the operation of the multiplier of the present invention constructed as above will be described. In the present invention, a triple quadrant cell in which three MOS transistors are driven by a common constant current source constitutes a two-quadrant multiplier (first invention). A quadrant multiplier is constructed (second invention). At that time, since an average method of applying the input voltage to the gate is adopted, a high impedance constant current source can be used as the driving source.

Therefore, according to the present invention, lower voltage, lower current consumption, and higher frequency can be achieved. In addition, the CMOS configuration can widen the input voltage range with good linearity.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a multiplier according to a first embodiment of the present invention. In FIG. 1, this multiplier is M1.
In a triple tail cell in which the three MOS transistors of M2 and M3 are driven by a common constant current source I ₀ , the first and second MOS transistors (M1 and M2) have their gates fed with the first signal (V _GS ± (V _1/2)) is input differential output terminal (drain) constitute an output pair, the third MO
In the S transistor M3, the second signal (V _GS + V
₂ ) is input, and a constant current source I _A is interposed between the output terminal (collector) and the power supply VDD.

Assuming that the matching between the elements is good on the same chip, and ignoring the channel length modulation and the substrate effect, the relation between the drain current and the gate-source voltage of the MOS transistor operating in the saturation region is squared. According to the rule, the drain currents (I _D1 , I _D2 , I _D3 ) of the CMOS triple tail cell driven by the tail current I ₀ are represented by Formulas 1, 2 and 3. However, in Equations 1 to 3, β is a transconductance parameter, and β = μ (using the effective mobility μ of carriers, the gate oxide film capacitance C _OX per unit area, the gate width W, and the gate length L. C _OX / 2) (W / L). Also, V _TH
Is the threshold voltage, K is the ratio of capacity (W / L) per unit transistor, and V _GS is the gate-source voltage when there is no signal.

[0015]

[Equation 1]

[0016]

[Equation 2]

[0017]

(Equation 3)

Further, the tail current I ₀ is given by Equation 4.

[0019]

[Equation 4] I _D1 + I _D2 + I _D3 = I ₀

Therefore, the differential output current ΔI _D of the CMOS triple tail cell is expressed by Equation 5 when none of the transistors is cut off.

[0021]

(Equation 5)

However, here, the value of the constant current source I _A driving the transistor M3 is I _A = {K / (K + 2)}
The voltage difference between the two input voltages is eliminated as I ₀ .

From Equation 5, the CMOS triple tail cell shown in FIG. 1 has an offset with respect to V ₂ , but 2
You can see that it is a quadrant multiplier.

Next, FIG. 2 is a principle view of a multiplier according to the second embodiment of the present invention. The multiplier according to the second embodiment is a four-quadrant multiplier composed of two two-quadrant multipliers 1 and 2 of the first embodiment. As described above, the two-quadrant multiplier has a differential pair input terminal including the gates of the first and second MOS transistors and one input terminal including the gates of the third MOS transistor and the first and second MOS transistors. And an output pair consisting of the drains of the transistors.

Therefore, the output pairs of the two-quadrant multipliers 1 and 2 are connected in common to those having different polarities to form a differential output pair, and the first signal V _x is the difference between the two multipliers. The second signal V _y is commonly input to the moving pair input terminal and differentially input to one input terminal of the two multipliers. Specifically, the configuration is as shown in FIG.

Differential output current ΔI _M {= (I _D1 + I _D5 )-(I _D2 + I _D4 )} of a CMOS 4-quadrant multiplier realized by combining two CMOS triple tail cells.
Is expressed by Equation 6 when none of the transistors is cut off.

[0027]

(Equation 6)

The input / output characteristics of the CMOS 4-quadrant multiplier are ideal multiplication characteristics, assuming the square law of MOS transistors.

In FIG. 3, M3 and M6 are each driven by a constant current source I _A , but these two constant current sources I _A
If common, as shown in FIG. 4, even when one of M3 and M6 are cut off, flow through the other transistor of the current outputted from the constant current source (2I _A) is not cut off This can prevent saturation of the constant current circuit.

[0030]

As described above, the multiplier of the present invention constitutes a two-quadrant multiplier by a triple tail cell in which three MOS transistors are driven by a common constant current source (first invention). A two-quadrant multiplier is used to form a four-quadrant multiplier (second invention). At that time, since an average method of applying the input voltage to the gate is adopted, a high impedance constant current source can be used as the driving source. Therefore, according to the present invention, lower voltage, lower current consumption, and higher frequency can be achieved. In addition, the CMOS configuration has the effect of widening the input voltage range with good linearity.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a multiplier according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a principle configuration of a multiplier according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a concrete configuration of a multiplier according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a concrete configuration of a multiplier according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional two-quadrant multiplier.

FIG. 6 is a circuit diagram of a conventional 4-quadrant multiplier.

[Explanation of symbols]

 1 and 2 quadrant multiplier M1 to M6 MOS transistors

Claims (3)

(57) [Claims] 1. A triple tail cell in which three MOS transistors are driven by a common constant current source;
The first signal is differentially input to the second MOS transistor, and the output terminal forms an output pair; the second signal is input to the third MOS transistor, and a constant current source is connected between the output terminal and the power supply. Intervening; Multiplier characterized by the following. 2. The multiplier according to claim 1, comprising two multipliers; output pairs having different polarities are commonly connected to form a differential output pair, and the first signal includes two multipliers. The multiplier is commonly differentially input to the first and second MOS transistors of the pliers, and the second signal is differentially input to the third MOS transistors of the two multipliers. 3. The multiplier according to claim 2, wherein the output terminals of the two third MOS transistors are commonly connected, and a common constant current source is interposed between the power supplies.