JP3117048B2 - Multiplication circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplying circuit which is a component of a high-frequency IC used for radio equipment, communication equipment and the like.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional double-balanced multiplying circuit using a common-emitter amplifier circuit. Output current I in each differential circuit composed of the transistor Q ₅ and Q ₆
a is the upper transistors Q ₁ and Q ₂ and Q ₃ and Q ₄
This is a two-stage vertically stacked differential circuit configuration in which the current of the differential circuit consisting of The input voltage Vc ₁ = V _{1 is} applied to the first and second terminals 1 and 2.
−V ₂ , the input voltage Vc ₂ = V _{3 is} applied to the third and fourth terminals 3 and 4.
The output current is obtained from the fifth and sixth terminals 5 and 6 by applying −V ₄ . When the transistor Q ₁ to constitute a Q ₆ in the bipolar transistor, the output current of the multiplier circuit Iou
t is

[0003]

(Equation 1) When the condition of

[0004]

(Equation 2) And the input voltages Vc ₁ and Vc ₂ are multiplied.

[0005] Here, V _T the threshold voltage of the transistor, I _a constant current source current, R ₁ and R ₂ are the output resistance. When the transistor Q ₁ to constitute a Q ₆ in the field effect transistor is not become the (1), becomes a multiplication circuit in the case of small signal input is universal.

[0006]

In the above prior art,
A differential circuit has a two-stage vertically stacked configuration, and at least three transistors including a constant current source and a current-voltage conversion circuit such as a resistor are vertically stacked, and a power supply voltage of 3.5 V or more is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiplier circuit which minimizes the number of vertically stacked transistors and which is advantageous for lowering the voltage.

[0008]

A multiplying circuit according to the present invention has a gate terminal or a base terminal of a first and a second transistor commonly connected, and a source terminal or an emitter terminal of the second transistor and a third terminal. A transistor circuit in which a drain terminal or a collector terminal of a transistor is commonly connected to a gate terminal or a base terminal of a fourth transistor is defined as a basic circuit.
The first and second transistors of each of the basic circuits are connected to a common gate terminal or base terminal, and a gate terminal or base terminal of a third transistor. Is the terminal B and the drain terminal or the collector terminal of the fourth transistor is the terminal C, the first input terminal pair composed of the first terminal and the second terminal of the multiplication circuit, and the third terminal and the fourth terminal The terminal A of the first and third basic circuits is the first terminal, and the terminal A of the second and fourth basic circuits is the second input terminal pair.
Are connected to the second terminal, the terminals B of the first and fourth basic circuits are connected to the third terminal, and the terminals B of the second and third basic circuits are connected to the fourth terminal, respectively. The terminals C of the circuits are commonly connected, and the terminals C of the third and fourth basic circuits are commonly connected.

The source terminal or the emitter terminal of the first and fourth transistors in all the basic circuits is connected to a common constant current source, and / or the source of the third transistor in all the basic circuits is The terminal or the emitter terminal is connected to another common constant current source.

[0010]

In the present invention, the vertical stacking of the transistors is reduced from two to three even if the transistors for the constant current source are included, and the power supply voltage of 2 V or less can be reduced.

[0011]

【Example】

Embodiment 1 FIG. 1 shows a basic circuit U used in a multiplication circuit according to the present invention. In FIG. 1, the gate terminals of the first and second transistors Q ₁ and Q ₂ are connected to the terminal A, the source of the _second transistor Q _{2 and} the drain of the third transistor Q ₃ are connected, fourth drain of the transistor Q ₄ to which the gate of the transistor Q ₃ is connected to the terminal B is connected to the terminal C, the gate the second, third transistor Q _2, the source-drain connection connected to Q ₃ Have been. When the voltage V ₁ is input to the terminal A and the voltage V ₂ is input to the terminal B with reference to the potential Vss, the gate-source voltage of the first transistor Q ₁ becomes V ₁ , and the third transistor Q ₃
Is V ₂ . Since the second transistor Q ₂ drain current flows equal to the third transistor Q _3, the second transistor Q ₂ Gate
Source voltage is equal to V _2. At this time, the gate-source voltage of the fourth transistor Q ₄ are, because the difference between the potential and the second source terminal potential of the transistor Q ₂ terminal A, the V ₁ -V _2.

Assuming that the fourth transistor Q ₄ is a field-effect transistor and operates in a saturation region, the terminal C
Fourth of the drain current I of the transistor Q ₄ that appears in the
_D4 is represented by the following equation.

[0013]

(Equation 3) Here, V _T first threshold voltage of the transistor Q _1, K is a constant gate length, gate width, as determined by electron mobility and the like.

The multiplication circuit of the first embodiment has such a basic circuit.
First and second transistors Q in path U ₁ , Q_Two , And the first
3 transistor Q_Three Ground the source terminals of the
FIG. 2 shows a circuit diagram of this circuit.

U1 to U4 are the first to U1 of the configuration shown in FIG.
The fourth basic circuit constitutes a multiplication circuit. That is, of the first input terminal pair composed of the first terminal 1 and the second terminal 2 and the second input terminal pair composed of the third terminal 3 and the fourth terminal 4, The terminal A of the basic circuits U1 and U3 is connected to the first terminal 1, the second and fourth terminals.
The terminal A of the basic circuits U2 and U4 is the second terminal 2, and the terminal B of the first and fourth basic circuits U1 and U4 is the third terminal 3.
The terminals B of the second and third basic circuits U2 and U3 are respectively connected to the fourth terminal 4, the terminals C of the first and second basic circuits U1 and U2 are commonly connected, and the third and The terminals C of the four basic circuits U3 and U4 are commonly connected.

The first basic circuits U1, U3 of this multiplication circuit
Voltages V ₁ to the first terminal 1, the basic circuit U2, the voltage V ₂ to the second terminal 2 of U4, the basic circuit U1, U4 third terminal 3 to the voltage V ₃ of the fourth terminal 4 of the basic circuit U2, U3 When a voltage is applied to V _4, the current at the output terminal of each of the basic circuits U1~U4 is as follows.

[0017]

(Equation 4) Using the above equations (4a) to (4d), the output current of the first embodiment is obtained as follows.

[0018]

(Equation 5) The above equation (5) is a product of the input differential voltages V ₁ -V ₂ and the input differential voltages V ₃ -V ₄ , and the first embodiment operates as a multiplier.

In the first embodiment, a bipolar transistor can be used. In that case, the gate terminal is a base terminal, the drain terminal is a collector terminal, and the source terminal is an emitter terminal.

First, the two-phase input voltage is applied to the first input terminal pair (first and second terminals 1 and 2) and the second input terminal pair (third and fourth terminals 3 and 4) of FIG. Is applied. With the reference voltages to both terminal pairs being V _R and V _Q , respectively, the voltage V
_A, the application of a V _B, each of the terminal voltage is expressed as follows.

[0021]

(Equation 6) Assuming that the transistor operates in the saturation region, the collector current Ic is expressed by the following equation.

[0022]

(Equation 7) Here, V _B is a gate-emitter voltage, I _S is a constant determined by the emitter cross-sectional area, base width, diffusion constant, base impurity concentration, and the like.

When the current at the terminal C of each basic circuit is obtained by using the above equation (7) in the same manner as in the case of the field effect transistor, the following is obtained.

[0024]

(Equation 8) Using the above equations (8a) to (8d), the output current of the first embodiment is obtained as follows.

[0025]

(Equation 9) Therefore, the first embodiment operates as a multiplier even if it is constituted by a bipolar transistor. [Embodiment 2] In Embodiment 1 of FIG. 2, the input terminal voltage itself is the gate-source voltage of the connected transistor. For this reason, the fluctuation of the input terminal voltage directly changes the output, and there is no tolerance for the fluctuation of the input voltage. This is improved in Example 2, and the circuit diagram is shown in FIG.
Shown in

[0026] In FIG. 3, the source terminal of the first transistor Q ₁ and the second transistor Q ₄ of the basic circuits U1~U4 the constant current source I _a, the source terminal of the third transistor Q ₃ constant current It is connected to the source I _b. Thereby, the fluctuation of the input voltage is reduced. Even when the constant current sources _Ia and _Ib are connected as shown in FIG. 3, the equation in the first embodiment is satisfied, and the circuit operates as a multiplication circuit. Third Embodiment FIG. 4 is a circuit diagram of a third embodiment of the present invention.
The first transistor Q ₁ and the fourth the basic circuits U1~U4
The source terminal of the transistor Q ₄ only connect the constant current source I _a, are unified to two transistors stacked vertically number in the case of using a transistor in the constant current source I _a. Also in this case, the equation in the first embodiment is satisfied, and the circuit operates as a multiplication circuit. In the case where the constant current sources _Ia and _Ib are constituted by transistors as described above, the number of cascaded stages in the first embodiment is two transistors or one transistor + load resistance, and the second embodiment is three transistors or two transistors + load. The third embodiment has two resistors or two transistors and a load resistor, and can operate at a lower power supply voltage than the conventional three-stage transistor and load resistor of FIG. 5 which is a conventional circuit. For example, it has been difficult to reduce the voltage to 3.5 V or less in the conventional circuit, but it is possible to reduce the voltage to 2 V or less by using the multiplying circuit of this embodiment.

Although not shown, in the embodiment of FIG. 3, the constant current source Ia may be removed and only the constant current source Ib may be used.

[0028]

As described in detail above, the present invention provides the first
And the gate terminal or the base terminal of the second transistor is commonly connected, and the source terminal or the emitter terminal of the second transistor, the drain terminal or the collector terminal of the third transistor, and the gate terminal or the base terminal of the fourth transistor are connected. A transistor circuit connected in common is a basic circuit, and four of the basic circuits are first, second, and second.
The first and third circuits are configured as third and fourth circuits.
And when the commonly connected gate or base terminal of the second transistor is terminal A, the gate or base terminal of the third transistor is terminal B, and the drain or collector terminal of the fourth transistor is terminal C, A first input terminal pair including a first terminal and a second terminal of the multiplication circuit and a second input terminal pair including a third terminal and a fourth terminal.
, The terminal A of the first and third basic circuits is the first terminal, the terminal A of the second and fourth basic circuits is the second terminal, and the input terminals of the first and fourth basic circuits are Terminal B is third
Terminals B of the second and third basic circuits are respectively connected to terminals, terminals C of the first and second basic circuits are commonly connected, and terminals of the third and fourth basic circuits are connected to the terminals. Since Cs are commonly connected, the number of vertically stacked transistors is reduced as compared with the conventional case, so that low voltage driving becomes possible.

The source terminal or the emitter terminal of the first and fourth transistors in all the basic circuits is connected to a common constant current source, and / or the source of the third transistor in all the basic circuits is Since the terminal or the emitter terminal is configured to be connected to another common constant current source, there is an advantage that an allowable range exists for the input voltage fluctuation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic circuit in an embodiment of the present invention.

FIG. 2 is a diagram illustrating a multiplication circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a multiplication circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a multiplication circuit according to a third embodiment of the present invention.

FIG. 5 is a diagram showing an example of a multiplying circuit conventionally used for both-phase input.

[Explanation of Signs] 1 first terminal 2 second terminal 3 third terminal 4 fourth terminal A terminal B terminal C terminal Q ₁ first transistor Q ₂ second transistor Q ₃ third transistor Q ₄ fourth Transistor R ₁ output resistance R ₂ output resistance UI 1st basic circuit U2 2nd basic circuit U3 3rd basic circuit U4 4th basic circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06G 7/163

Claims (2)

(57) [Claims] 1. A gate terminal or a base terminal of a first transistor and a second transistor are commonly connected, and a source terminal or an emitter terminal of the second transistor, a drain terminal or a collector terminal of a third transistor, and a fourth transistor. A transistor circuit having a gate terminal or a base terminal connected in common is used as a basic circuit, and four basic circuits are used as first, second, third, and fourth circuits. A gate terminal or a base terminal of the second transistor, which is connected in common, is connected to terminal A,
When the gate terminal or the base terminal of the transistor is a terminal B and the drain terminal or the collector terminal of the fourth transistor is a terminal C, a first input terminal pair composed of a first terminal and a second terminal of the multiplication circuit; Of the second input terminal pair composed of the third terminal and the fourth terminal, the terminal A of the first and third basic circuits is the first terminal, and the terminal A of the second and fourth basic circuits is the second terminal. 2
A terminal, a terminal B of the first and fourth basic circuits is connected to a third terminal, a terminal B of the second and third basic circuits is connected to a fourth terminal, respectively, and a terminal of the first and second basic circuits is connected. C are commonly connected to each other, and terminals C and C of the third and fourth basic circuits are connected.
A multiplying circuit characterized in that they are commonly connected to each other. 2. The source terminal or the emitter terminal of the first and fourth transistors in all the basic circuits,
2. The method according to claim 1, wherein the third transistor in all the basic circuits is connected to a common constant current source or / and the source terminal or the emitter terminal of the third transistor is connected to another common constant current source. Multiplier circuit as described.