JPH061901B2 - A buffer circuit using MOS transistors - Google Patents

Description

The present invention relates to a circuit including a MOS transistor in a bipolar circuit, and more particularly to a buffer circuit having a good transfer characteristic.

Conventionally, a circuit including a MOS transistor in a bipolar circuit has been devised. In particular, since the input impedance of MOS transistors is extremely high, they are often used in buffer circuits such as sampling and holding. At this time, the input / output transfer characteristics of the buffer circuit and its output impedance have been of great concern from the past.

A conventional buffer circuit is shown in FIG. 1,
2 is a MOS transistor, 3 is a current source, and 4 and 5 are transistors. The MOS transistors 1 and 2 in the figure are shown as P-channel MOS.

The sources of the MOS transistors 1 and 2 are commonly connected, and a current source 3 is further applied. The collectors of the transistors 4 and 5 are connected to the drains of the MOS transistors 1 and 2, respectively. The emitters of the transistors 4 and 5 are both grounded, and their bases are commonly connected. The collector of the transistor 4 is also connected to the common base and has a diode configuration. The gate of the MOS transistor 2 is connected to the drain and has a diode configuration, and the output is taken out from the common point. Also MO
The second gates (or also called back gates) of the S transistors 1 and 2 are connected to the source side (high potential side), respectively. Furthermore, in each case, the source side of the MOS transistor pair is common.

Next, the operation will be described. The input voltage V _IN is applied to the gate of the MOS transistor 1, and a voltage represented by the following equation is generated at its source.

V _S = V _IN + V _GS1 V _GS1 > 0 (1) where V _GS1 is the gate-source voltage of the MOS transistor 1 and V as a function of the drain current I _D1.
It is represented by _GS1 (I _D1 ). Further, the above-mentioned V _S is connected to the source of the diode-connected MOS transistor 2, and the output voltage V _OUT is generated from the drain (or gate) thereof according to the following equation.

V _OUT = V _S + V _GS2 V _GS2 > 0 (2) Therefore, from the above equations (1) and (2), the output voltage V _OUT and the input voltage V _IN have the following equation.

V _OUT = V _IN + V _GS1 (I _D1 ) −V _DS2 (I _D2 ) (3) Here, considering the relationship between V _GS1 (I _D1 ) and V _GS2 (I _D2 ), the current of the current source 3 is calculated. If 2I ₀ , then 2I ₀ = I _D1 + I _D2 (4). On the other hand, transistors 4 and 5 are connected to the drain of the MOS transistor 1 and the drain of the MOS transistor 2 in a current mirror configuration. That is, if the emitter currents of the transistors 4 and 5 are I _E4 and I _E5 and both transistors are manufactured with the same characteristics, I _{E4 E5} (5) is obtained, ignoring the influence of the base current. Here, the manufacture of transistor pairs having the same characteristics is easily realized in the same chip IC. At this time, since I _D1 I _E4 and I _D2 I _E5 (6), it is eventually expressed as I _D1 I _D2 = I ₀ (7). Therefore, if the MOS transistors 1 and 2 are manufactured with the same characteristics, V _GS1 (I _D1 ) V _GS2 (I _D2 ) (8) is obtained, and the V _GS of both MOS transistors 1 and 2 are substantially the same. Therefore, the input and output voltages match from Eq. (3).

Now let's examine the characteristics of V _GS in detail. V _DS -I _D characteristic of the MOS transistor is as generally Figure 2 is represented by the V _GS as a parameter. That is, the drain current I
_{If the} drain-source voltage V _DS is different even if _D is made equal, a slight difference voltage occurs in V _GS . That is, V _GS is I
It is known to be a function of _D and V _DS . Therefore, even if I _D1 = I _D2 in the above equation (8), Then, equation (8) does not hold. That is, equation (3) becomes the following equation.

V _OUT −V _IN = V _GS1 (I _D1 , V _DS1 ) −V _GS2 (I _D2 , V _DS2 ) (9) Here, the first term on the right side of the equation (9) is a function of V _GS1 being I _D1 and V _D1 . And the second term indicates that V _GS2 is a function of I _D2 and V _DS2 .

Therefore, referring to FIG. 1, V _DS is given by the following equation.

V _DS1 = V _IN + V _GS1 −V _BE4 (10) V _DS2 = V _GS2 (11) where V _BE4 is the base-emitter voltage of the transistor 4. Therefore, if V _GS1 V _GS2 , then V _DS1
The difference voltage between V _DS2 and V _DS2 is expressed by the following equation.

ΔV _DS = V _DS1 −V _DS2 V _IN −V _BE4 (12) Therefore, from the formula (9), V _OUT −V _IN V _GS1 (V _DS1 ) −V _GS2 (V _DS2 ) = ΔV _GS (V _IN −V _BE4 ). (13) Here, ΔV _GS means the difference voltage of V _GS due to the difference of V _DS , and the difference of V _DS is represented by the equation (12). When V _{BE4 is} constant, the input / output differential voltage ΔV is given by the following equation.

−ΔV = V _OUT −V _IN ΔV _GS (V _IN ) (14) Here, the V _GS −V _DS characteristics when I _{D is} constant are generally not necessarily linear.

Looking at equation (14), the output voltage V _OUT does not match the input voltage V _IN, the error voltage [Delta] V _GS (V further according to the input voltage V _IN
IN ). This has a serious drawback that not only DC voltage is not accurately transmitted but also distortion occurs in AC signal transmission, for example.

Further, the V _GS -V _DS characteristic has a drawback that it causes a temperature characteristic error in the V _GS temperature characteristic due to the difference in V _DS .

In addition, the impedance of a diode-connected MOS transistor is generally as large as several KΩ, and there is a drawback that a low-impedance output as a buffer circuit cannot be expected.

An object of the present invention is to provide a buffer circuit that accurately transmits a DC level without depending on an input signal level and reduces AC signal transmission distortion.

The main object of the present invention is to equalize the drain currents of the MOS transistor pairs and equalize the drain-source voltages to eliminate the voltage error during DC transmission and to equalize the temperature characteristics.

An embodiment of the present invention will be described below with reference to FIG. In the figure, 1 and 2 are MOS transistors, 6 and 7 are transistors, and 8 and 9 are current sources. MOS transistors 1 and 2
Is a P-channel MOS, the drains of which are commonly connected, and the current source 9 is also connected. The sources of the MOS transistors 1 and 2 are connected to the emitters of the transistors 6 and 7, respectively, and the bases of both transistors are commonly connected. The collector of the transistor 6 is connected to the base, and the current source 8 is further applied. MOS
The input voltage V _IN is applied to the gate of the transistor 1,
The drain and gate of the MOS transistor 2 are connected,
The output voltage V _OUT is being output.

Next, the operation will be described. The drain current of the MOS transistor 1 and the emitter current of the transistor 6 are equal.
_Set to ₁ . Similarly, the drain current of the MOS transistor 2 and the emitter current of the transistor 7 are also equal to each other and are set to I ₂ . The output voltage V _{OUT at} this time is given by the following equation.

V _OUT = V _IN + V _GS1 (I ₁ , V _DS1 ) + V _BE6 −V _BE7 −V
_GS2 (I ₂ , V _DS2 ) (15) where V _BE6 and V _BE7 are the base-emitter voltages of the transistors 6 and 7, and V _GS1 and V _GS2 > 0. Here, it is assumed that the MOS transistors 1 and 2 and the transistors 6 and 7 are manufactured to have the same characteristics.

Now, try to find I ₁ and I ₂ . A current source 8 is connected to the base and collector of the diode-connected transistor 6, and the current source I ₀ almost flows to the emitter of the transistor 6. That is, I ₁ E56EI ₀ . on the other hand,
Since the current value of the current source 9 is 2I ₀ , the current I ₁ becomes 2I ₀ = I ₁ + I ₂ I ₀ + I ₂ (16) Therefore, I ₂ I ₀ becomes I ₁ I ₂ . That is, the drain currents of the MOS transistors 1 and 2 and the emitter currents of the transistors 6 and 7 are almost equal.

Next, consider the drain-source voltage V _DS of the MOS transistors 1 and 2. Since the drains of the MOS transistors 1 and 2 are common, the difference between their source voltages may be considered. At this time, V _S1 = V _IN + V _GS1 (I _{1 ,,} V _DS1 ) (17) V _S2 = V _OUT + V _GS2 (I _{2 ,,} V _DS2 ) (18) Substituting equation (15) into equation (18) gives V _S2 = V _IN + V _GS1 (I ₁ , V _DS1 ) + V _BE6 −V _BE7 (19). Wherein the emitter current of the transistor 6 and 7 may be a V _BE6 E56EV _BE7 than approximately equal. Therefore, the equation (19) is almost equal to the equation (17): V _S2 V _S1 = V _IN + V _GS1 (I ₁ , V _DS1 )
(20) Therefore, V _DS1 V _DS2 (21) Therefore, the following equation holds from I ₁ I ₂ .

V _GS1 (I ₁ , V _DS1 ) V _GS2 (I ₂ , V _DS2 ) (22) Therefore, the equation (15) is V _OUT = V _IN + {V _GS1 (I ₁ , V _DS1 ) −V _GS2 (I ₂ ,
V _DS2 )} + (V _BE6 −V _BE7 ) V _IN + {V _GS1 (I ₁ , V _DS1 ) −V _GS2 (I ₂ ,
_{V DS2)} V IN (23} ) , and the output voltage V _OUT is not affected by the V _IN is always equal to the input voltage V _IN.

At the same time, the temperature characteristics of V _GS also become equal and no temperature drift occurs.

Next, FIG. 4 shows an embodiment of the present invention using an N-channel MOS transistor. In the figure, 10 and 11 are MOS transistors, 12 and 13 are transistors, and 3 and 14 are current sources. The configuration is the polarity of FIG. 3 reversed, and the operating characteristics are exactly the same as those of FIG. Where MOS transistor 1
Reference numerals 0 and 11 are N-channel MOS transistors, and therefore the second gate (or back gate) is connected to the source side (low potential side).

As described above, in the present invention, the drain side of the MOS transistor pair is commonly connected, and the source potentials of the MOS transistor pairs are made equal by the transistor means, whereby the drain-source voltage V _DS is set to be equal.

In the above embodiment, two current sources are required, but an embodiment in which only one current source is used is shown in FIG. 5 and FIG. FIG. 5 is a modification of FIG. 3, and FIG. 6 is a modification of FIG. Fifth
In the figure, the current source 8 has a current mirror configuration of transistors 81 and 82, and the drain currents I _D1 and I _D2 of the MOS transistors 1 and ₂ are always equal. Therefore, as can be easily understood from the above description, the input / output characteristic is V _OUT = V
You can see that it will be _IN . Similarly, in FIG. 6, the current source 14 has a current mirror configuration of the transistors 141 and 142, and therefore similar input / output characteristics can be obtained.

In the configurations shown in FIGS. 5 and 6, it is understood that even if the current source 9 and the current source 3 are replaced by resistance elements, the drain currents of the respective MOS transistors change depending on the input signal V _IN, but they are always equal. See. That is, similar input / output characteristics can be obtained.

Next, another embodiment of the present invention in which the buffer circuit has a low output impedance is shown in FIG. 3rd in the figure
Those having the same functions as those in FIGS. 5 and 5 are designated by the same reference numerals. First, the source of the MOS transistor 1 is connected to the emitter of the transistor 6, the base and collector of the transistor 6 are commonly connected, and the current source 3 and the MOS transistor 2 are connected.
Connected to the source. The gate of the MOS transistor 2 is connected to the drain, and further connected to the current source 14 and the base of the transistor 7. Transistor 7
The emitter of is commonly connected to the drain of the MOS transistor 1 and further connected to the current source 9 for output. The input signal V _IN is applied to the gate of the MOS transistor 1.

To explain the operation, the drain current of the MOS transistor 1 is I ₁ , the drain current of the MOS transistor 2 is I ₂ , and the emitter current of the transistor 7 is I ₃ . At this time I ₁ ,
I ₂ , I ₃ and the output voltage V _OUT are expressed by the following equations.

V _OUT = V _IN + V _GS1 (I ₁ , V _DS1 ) + V _BE6 −V _GS2 (I ₂ ,
V _DS2 ) -V _BE7 (24) I ₁ + I ₂ = 2I ₀ (25) I ₂ = I ₀ (26) I ₁ + I ₃ = 2I ₀ (27) From Formulas (25) to (27) I ₁ = I ₂ = I ₃ = I ₀ (28), so V _BE6 = V _BE7 (29) _Now consider V _DS1 and V _DS2 . In this case _{V DS1 = (V IN + V} GS1) -V OUT (30) V DS2 = (V IN + V GS1 + V BE6) - (V OUT + V BE7)
(31) Therefore, V _DS1 −V _DS2 = V _BE7 −V _BE6 = 0 and V
_DS1 = V _DS2 .

Therefore, V _GS1 (I ₁ , V _DS1 ) V _GS2 (I ₂ , V _DS2 ) (32) Substituting equations (29) and (32) into equation (24) yields the following equation.

V _OUT E56EV _IN (33) The output impedance Z _{OUT at} this time is Z _OUT = γ ₆ + 1 / h _FE · γ _MOS . Here, γ ₆ is the emitter resistance of the transistor 7 and is usually about several tens Ω. Also h _FE is transistor 7
, Γ _MOS is the resistance value of the MOS transistor 2, and h _FE is usually several hundreds. Therefore γ _MOS / h _FE
Is several tens of Ω, and Z _OUT is 100 Ω or less at maximum, which is extremely small.

Next, another embodiment of the present invention is shown in FIG. In the figure, parts having the same functions as those in FIGS. 3, 4, and 5 are designated by the same reference numerals. Here, the MOS transistors 10 and 11 are N
This is a channel MOS, and the overall configuration is the polarity of FIG. 7 reversed. The operating characteristics are exactly the same as in Fig. 7,
The output impedance Z _OUT is as small as 100Ω or less.

Next, as shown in FIGS. 5 and 6 with respect to FIGS. 3 and 4, an embodiment in which the current sources 3 and 9 of FIGS. Show. In FIG. 9, the current source 3 has a current mirror configuration of transistors 31 and 32, and the emitter area is doubled so that a current twice as large as that of the transistor 32 flows through the transistor 31. Therefore MO
The currents of the S-transistors 1 and 2 and the transistors 6 and 7 are all the same, and similar input / output characteristics are obtained. Similarly, in FIG. 10, the current source 9 has the current mirror configuration of the transistors 91 and 92 (the emitter area of the transistor 91 is twice as large as that of the transistor 92, of course), whereby exactly the same input / output characteristics are obtained. It will be easy to understand.

According to the present invention, by equalizing the drain-source voltage of the MOS transistor pair, the error of the gate-source voltage can be eliminated, and the input voltage and the output voltage can be accurately matched. Further, the distortion of the output voltage caused by the change of the input signal can be reduced. Furthermore, since the output impedance can be made sufficiently low, it has an effect of bringing it closer to an ideal buffer circuit.

[Brief description of drawings]

1 is a circuit diagram showing a conventional example, FIG. 2 is a characteristic diagram of a MOS transistor, FIG. 3 is a circuit diagram showing an embodiment of the present invention,
4 to 10 are circuit diagrams showing another embodiment of the present invention. 1, 2, 10, 11 ... MOS transistors 4, 5, 6, 7 ... Transistors 12, 13 ... Transistors 3, 8, 9, 14 ... Current sources

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideo Nishijima, Inventor Hideo Nishijima, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Home Appliances Research Laboratory, Hitachi, Ltd. (72) Kazumi Kuwahara, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa (72) Inventor, Makoto Furihata, No. 111 Nishiyokote-cho, Takasaki City, Gunma Prefecture Takasaki Plant, Hitachi, Ltd.

Claims (4)

[Claims] 1. A first MO in which an input signal is applied to a gate.
An S transistor (1, 10), a second MOS transistor (2, 11) whose gate and drain are conductively connected, and a first MOS transistor commonly connected to the drains of the first and second MOS transistors. A diode-connected first bipolar transistor (6, 12) having a current source (9, 3), an emitter connected to the source of the first MOS transistor, and a conductively connected base and collector; A second bipolar transistor (7, 1) having an emitter connected to the source of the second MOS transistor, a base connected to the base and collector of the first bipolar transistor, and a collector connected to a power supply.
3) and a second current source (8, 14) connected to the base and collector of the first bipolar transistor, wherein the current value of the first current source is that of the second current source. A buffer circuit using a MOS transistor, which is approximately twice the current value, wherein the gate and drain of the second MOS transistor are on the output side. 2. A first MO in which an input signal is applied to the gate.
An S transistor (1, 10), a second MOS transistor (2, 11) whose gate and drain are conductively connected, and a first MOS transistor commonly connected to the drains of the first and second MOS transistors. A diode-connected first bipolar transistor (6, 12) having a current source (9, 3), an emitter connected to the source of the first MOS transistor, and a conductively connected base and collector; A second bipolar transistor (7, 13) having an emitter connected to the source of the second MOS transistor and a base connected to the base and collector of the first bipolar transistor; and the first bipolar transistor. Collector commonly connected to the base and collector of the second bipolar transistor and the base of the second bipolar transistor Third bipolar transistor having a source connected to the emitter (81,14
1) and a diode-connected fourth bipolar transistor (82, 142) having a base and a collector connected to the collector of the second bipolar transistor, and an emitter connected to a power supply. A buffer circuit using a MOS transistor, wherein the fourth bipolar transistor has a current mirror connection configuration, and the gate and drain of the second MOS transistor are used as output terminals. 3. A first MO in which an input signal is applied to the gate.
An S transistor (1, 10), a second MOS transistor (2, 11) whose gate and drain are conductively connected, an emitter connected to the source of the first MOS transistor, and a conductively connected base A first bipolar transistor (6, 12) of diode connection type having a collector and a collector, and a second bipolar transistor having a base connected to the gate and drain of the second MOS transistor and a collector connected to a power supply A transistor (7, 13); a first current source (9, 3) commonly connected to the drain of the first MOS transistor and the emitter of the second bipolar transistor; A second current commonly connected to the gate and drain and the base of the second bipolar transistor. (14, 8), and a third current source (3, 9) commonly connected to the base and collector of the first bipolar transistor and the source of the second MOS transistor. The current value of the current source is approximately twice the current value of the second current source, the current value of the third current source is substantially equal to the current value of the first current source, and A buffer circuit using a MOS transistor, characterized in that the emitter of the bipolar transistor is used as an output terminal. 4. A first MO in which an input signal is applied to the gate.
An S transistor (1, 10), a second MOS transistor (2, 11) whose gate and drain are conductively connected, an emitter connected to the source of the first MOS transistor, and a conductively connected base A diode-connected first bipolar transistor (6, 12) having a collector and a collector; a second bipolar transistor (7, 13) having a base connected to the gate and drain of the second MOS transistor; A third bipolar transistor (31, 91) having a base and a collector of the first bipolar transistor and a collector commonly connected to the source of the second MOS transistor, and a collector and a third of the second bipolar transistor. And a base connected to the base of the bipolar transistor of And a diode-connected fourth bipolar transistor (32, 92) having a transistor, the first current source being commonly connected to the drain of the first MOS transistor and the emitter of the second bipolar transistor. (9, 3), and a second current source (14, 8) commonly connected to the gate and drain of the second MOS transistor and the base of the second bipolar transistor. The current value of the current source is approximately twice the current value of the second current source, the third and fourth bipolar transistors have a current mirror connection configuration, and the emitter of the second bipolar transistor is Is a buffer circuit using a MOS transistor.