JPH04354075A - Multiplier - Google Patents

Abstract

PURPOSE:To improve linearity by connecting two sets of differential paired transistors between a first input terminal pair, and simultaneously, connecting plural two or more sets of the differential paired transistors in parallel between a second input terminal pair in a pseudo Gilbert multiplier. CONSTITUTION:In the multiplier, two sets of the differential paired transistors (M1, M2), (M3, M4) are arranged between the first input terminal pair 1, 2. Between the second input terminal pair 3,4, n-sets of the differential paired transistors (M5, M6)..., (M(2(n+2)-l),M(2(n+2)), (n=2) are connected in parallel. All the ratios of gate width to gate length of the transistors M5, M6, etc., are made equal. n-sets of the differential paired transistors (M5, M6), etc., are driven by the constant current sources I0 of the same contents. Thus, the characteristics of the multiplier about input voltages V1, V2 come nearly equal, and the linearity becomes n<1/2>-times wider than in the case of n=1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for multiplying analog signals, and more particularly to a multiplier constructed on a C-MOS integrated circuit.

0002

2. Description of the Related Art As is well known, a Gilbert multiplier is known as a multiplier, and this multiplier is constructed on a bipolar integrated circuit.
If it is constructed on an integrated circuit, it will be as shown in FIG. In FIG. 5, this pseudo-Gilbert multiplier is
Two sets of differential pair transistors ((M1, M2), (M3, M4)) are arranged between the (first) input terminal pair (1, 2), and the (second) input terminal pair (3 , 4) Arrange one differential pair transistor (M5, M6) that drives each of the two sets of differential pair transistors between them, and drive this one differential pair transistor with one constant current source I0. It was designed to do so.

That is, two sets of differential pair transistors ((M1
, M2), (M3, M4)), the drains of one transistor (M1, M3) and the drains of the other transistor (M2, M4) are connected in common, and the (first) differential pair transistor The gate of one transistor M1 of (M1, M2) and the gate of the other transistor M3 of the (second) differential pair transistors are commonly connected to one input terminal 1 of the input terminal pair (1, 2). , the gate of the other transistor M2 of the differential pair transistors (M1, M2) and the gate of one transistor M3 of the differential pair transistors (M3, M4) are commonly connected to the input terminal pair (
1 and 2). And 1
In the differential pair transistors (M5, M6), one transistor M5 has a drain and a drain is a differential pair transistor (M5, M6).
1, M2), and the gate is connected to the input terminal pair (
3, 4), and one transistor M6 is connected to one input terminal 3 of the transistor M6, whose drain is connected to the differential pair transistor (M
3, M4), and the gate is connected to the input terminal pair (
3 and 4).

In this pseudo-Gilbert multiplier,
For two input signals (voltages V1 and V2), the difference (I1 - I2) between the differential output currents I1 and I2 is proportional to the product of the voltages V1 and V2, as shown in Equation 1 below. In addition, in the formula, α1 and α2 are the mobility of the transistor as μn and the gate oxide film capacitance as COX,
It is shown by formulas 2 and 3.

[0005]

[Math 1]

[0006]

[Math 2]

[0007]

[Math 3]

[0008] Also, in equations 2 and 3, W1/L1
, W5/L5 is the gate width W of transistor M1 and M5.
and the gate length L (W/L), but the transistor (
W/L of transistor M2, M3, M4) is equal to that of transistor M1 (Equation 4), and W/L of transistor M6 is equal to that of transistor M5 (Equation 5).

[0009]

[Math 4]

0010

[Math 5]

[0011]

Problem to be Solved by the Invention In the configuration of the pseudo-Gilbert multiplier described above, the second input voltage (V2
) The linearity range obtained for the first input voltage (V1) is narrower than the linearity range obtained for the first input voltage (V1), so there is a problem that it is difficult to use it as an analog multiplier. The basis for this problem has not always been clear, but as a result of a detailed study of the process of deriving Equation 1, the basis for this problem has become clear. This will be explained below.

Transistors (M1, M2, M3, M4,
M5, M6) respective drain currents (Id1, Id2
, Id3, Id4, Id5, Id6) are expressed by the following Equations 6 to 11. In the formula, Vgsi (i=1, 2, . . . , 6) is the gate-source voltage of the transistor Mi, and Vt is the pinch-off voltage of the transistor.

[0013]

[Math 6]

[0014]

[Math 7]

[0015]

[Math. 8]

[0016]

[Math. 9]

[0017]

[Math. 10]

[0018]

[Math. 11]

Here, Id5, Id6, I0, V1
, V2 can be set using the following Equations 12 to 16.

[0020]

[Math. 12]

[0021]

[Math. 13]

[0022]

[Math. 14]

[0023]

[Math. 15]

[0024]

[Math. 16]

When IV2 is set as shown in Equation 17 below, Id5 and Id6 are determined from Equations 14 and 17 as shown in Equations 18 and 19 below.

[0026]

[Math. 17]

[0027]

[Math. 18]

[0028]

[Math. 19]

Furthermore, if IV1 is set as shown in the following equation 20, the input voltage V1 is determined as shown in the following equation 21.

[0030]

[Math. 20]

[0031]

[Math. 21]

[0032] Then, I1 - I2 becomes as shown in Equation 22 below.

[0033]

[Math. 22]

Here, if f(x), g(x), and h(x) are set as shown in Equations 23 to 25 below, and h(x) is expanded into a series, Equation 26 is obtained.

[0035]

[Math. 23]

[0036]

[Math. 24]

[0037]

[Math. 25]

[0038]

[Math. 26]

In Equation 23, the first differential of f(x) is Equation 27, and the value of this when x=0 is Equation 28. Also, the second derivative of f(x) is Equation 29, and this x
The value of =0 is Equation 30. Thereafter, higher-order values are found in the same way.

[0040]

[Math. 27]

[0041]

[Math. 28]

[0042]

[Math. 29]

[0043]

[Math. 30]

Further, in Equation 24, the first differential of g(x) is Equation 31, and the value of this when x=0 is Equation 32. Further, the second differential of g(x) is expressed by Expression 33, and the value of this when x=0 is expressed by Expression 34. Thereafter, higher-order values are found in the same way.

[0045]

[Math. 31]

[0046]

[Math. 32]

[0047]

[Math. 33]

[0048]

[Math. 34]

However, since f(0)=g(0)=1, h(0)=0. From the above, h(x)=a
As a result, I1 - I2 becomes the following equation 35, and further considering the relationship between equations 20 and 21, it becomes equation 36.

[0050]

[Math. 35]

[0051]

[Math. 36]

[0052] In Equation 36, if we ignore the second and subsequent terms and also ignore the V12 term by setting V12=0, we get
I1 - I2 can be found as shown in Equation 37 below.

[0053]

[Math. 37]

Further, when formula 36 is further expanded into a series, I
1 −I2 becomes the following formula 38, so V1 , V
2 Ignoring each quadratic or higher order term, Equation 39 is obtained. This is the same as Equation 1 above.

[0055]

[Math. 38]

[0056]

[Math. 39]

Now, from Equation 37, the circuit shown in FIG. 6 is obtained as the equalization circuit of the pseudo Gilbert multiplier shown in FIG. 5. Therefore, IV1 corresponds to the differential output current (transfer curve) of the differential amplifier driven by the constant current source I0/2 for the input voltage V1, and IV2 corresponds to the constant current source I0 for the input voltage V2. This indicates that it corresponds to the differential output current (transfer curve) of the differential amplifier being driven.

In short, the transfer ratio of the differential amplifier is
The curve can be regarded as a straight line if the input voltage is small, so
Equation 37 shows a multiplier that operates within a small range of input voltages V1 and V2, but from Equation 36,
The voltage range with good linearity obtained with the input voltage V1 is narrower than the voltage range with good linearity obtained with the input voltage V2. For example, in the case of using transistors of the same size, the operating range of the input voltage V1 is 1/√2 of the operating range of the input voltage V2.

An object of the present invention is to provide a pseudo-Gilbert multiplier that can significantly improve linearity by expanding the operating range of the first input voltage.

[0060]

Means for Solving the Problems In order to achieve the above object, the multiplier of the present invention has the following configuration. That is, the multiplier of the present invention includes first and second differential pair transistors arranged between a first pair of input terminals, and between these two sets of differential pair transistors,
The drains of one transistor and the drains of the other transistor are connected in common, and the gate of one transistor of the first differential pair transistor and the drain of the second transistor are connected in common.
The gate of the other transistor of the first differential pair transistors is commonly connected to one input terminal (one polarity) of the first input terminal pair, and the gate of the other transistor of the first differential pair transistor first and second differential pair transistors in which the gates of one transistors of the two differential pair transistors are commonly connected to the other input terminal (the other polarity) of the first input terminal pair; n (n≧2) sets of differential pair transistors arranged between input terminal pairs of The transistors are connected to the sources of the dynamic pair transistors, their gates are commonly connected to one input terminal (one polarity) of the second input terminal pair, and the drains of the other transistor are commonly connected to the second input terminal pair. n sets of differential pair transistors connected to the sources of the dynamic pair transistors and whose gates are commonly connected to the other input terminal (the other polarity) of the second input terminal pair; It is characterized by comprising: n constant current sources having the same content that drive each of the transistors; and;

[0061]

[Operation] Next, the operation of the multiplier of the present invention constructed as described above will be explained. The multiplier of the present invention is
Two sets of differential pair transistors are arranged between the first pair of input terminals, and n sets of the same configuration (n≧2
) differential pair transistors are connected in parallel and the drains of the n sets of differential pair transistors connected in parallel are connected to the corresponding sources of the two sets of differential pair transistors, and Each of the differential pair transistors is driven by a constant current source having the same content. Note that "same configuration" means that the ratio of gate width to gate length is the same.

As a result, the operating range of the first input voltage applied to the first input terminal pair can be expanded, and linearity can be significantly improved.

[0063]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a multiplier according to one embodiment of the invention. In FIG. 1, this multiplier consists of (n-1) pairs of differential pair transistors (M5, M6) in the pseudo Gilbert multiplier shown in FIG. Differential pair transistor (M{2(
n+2)-1}, M{2(n+2)}) are connected in parallel,
Each of n sets including differential pair transistors (M5, M6) is driven by a constant current source I0 having the same content. Note that (n-1) differential pair transistors (M{2(
n+2)-1}, M{2(n+2)}), the gate width and gate length ratios are the same as the differential pair transistors (M5, M
It is made equal to that of 6). Below, when n=2, that is, when there is one additional differential pair transistor (this is defined as M
7, M8) will be explained.

The additional transistors M7 and M8 have a gate width W to gate length L ratio (W/L) equal to that of the transistors M5 and M6, respectively (Equation 40).

[0065]

[Math. 40]

Therefore, additional transistors M7 and M8
The relationship between the drain currents Id7 and Id8 and these and the input voltage V2 and constant current source I0 is expressed by the following equation 41.
~44, but these are transistors M5 and M6
is the same as that of

[0067]

[Math. 41]

[0068]

[Math. 42]

[0069]

[Math. 43]

[0070]

[Math. 44]

[0071] Therefore, if IV2 is set as shown in the following equation 45 in the same way as the above equation 17, Id7 and Id8 can be found as shown in the following equations 46 and 47 from equations 44 and 45, and these are Equal to Id5 and Id6.

[0072]

[Math. 45]

[0073]

[Math. 46]

[0074]

[Math. 47]

Further, if IV1 is set as shown in the following equation 48, the input voltage V1 is determined as shown in the following equation 49.

[0076]

[Math. 48]

[0077]

[Math. 49]

Then, I1 - I2 becomes as shown in the following equation 50, which is expanded into a series to become as shown in equation 51.

[0079]

[Number 50]

[0080]

[Math. 51]

[0081] Then, I1 - I2 becomes as shown in the following equation 52 by considering equations 48 and 49, and furthermore,
If the second term and subsequent terms are ignored, and the V12 term is ignored by setting V12=0, Equation 53 is obtained.

[0082]

[Math. 52]

[0083]

[Math. 53]

Here, from Equation 53, IV1 is a constant current source I0 (conventionally I0 /2
), and IV2 corresponds to the differential output current (transfer curve) of the differential amplifier driven by the constant current source I0 with respect to the input voltage V2. (transfer curve).

In short, the transfer ratio of the differential amplifier is
The curve can be regarded as a straight line if the input voltage is small, so
Equation 53 indicates a multiplier that operates within a small range of input voltages V1 and V2. In this respect, it is similar to the pseudo Gilbert multiplier shown in FIG.

However, from a comparison between Equation 45 and Equation 48,
If configured with transistors of the same size, that is, α1
= α2, the characteristics of the multiplier will be almost the same for both input voltages V1 and V2, so
It can be seen that the operating range of the input voltage V1 is correspondingly wider than that of the pseudo Gilbert multiplier shown in FIG. 5, and the linearity of the multiplier is improved. Specifically, in the configuration where n=2 (α1 =α2), the width is increased by √2 times, and in the general configuration shown in FIG. 1, the width is increased by √n times.

From the above, the equalization circuit of the multiplier having the general configuration shown in FIG. 1 is as shown in FIG. 2, and its characteristics are as shown in FIGS. 3 and 4. However, IV
1 is the following formula 54.

[0088]

[Math. 54]

[0089]

As explained above, according to the multiplier of the present invention, two sets of differential pair transistors are arranged between the first input terminal pair, and the same structure is arranged between the second input terminal pair. n sets of differential pair transistors are connected in parallel and arranged,
The drains of each of the n sets of differential pair transistors connected in parallel are connected to the corresponding sources of the two sets of differential pair transistors, and each of the n sets of differential pair transistors is connected to a constant current source having the same content. Since the first input voltage is driven, the operating range of the first input voltage applied to the first input terminal pair can be expanded, and the linearity can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a multiplier according to an embodiment of the present invention.

FIG. 2 is an equalization circuit diagram of the multiplier shown in FIG. 1;

FIG. 3 is a diagram showing the relationship between input voltage V1 and output current (I1, I2) when input voltage V2 is used as a parameter.

FIG. 4 is a diagram showing the relationship between input voltage V2 and output current (I1, I2) when input voltage V1 is used as a parameter.

FIG. 5 is a circuit diagram of a pseudo-Gilbert multiplier.

FIG. 6 is an equalization circuit diagram of a pseudo-Gilbert multiplier.

[Explanation of symbols]

1 Input terminal 2 Input terminal 3 Input terminal 4 Input terminal M1 Transistor M2 Transistor M3 Transistor M4 Transistor M5 Transistor M6 Transistor M{2(n+2)-1} Transistor M{2(n+)
2)} Transistor I0 Constant current source V1 Input voltage V2 Input voltage

Claims (1)

[Claims] Claim 1: A first input terminal disposed between a first pair of input terminals.
and a second differential pair of transistors, in which the drains of one transistor and the drains of the other transistor are connected in common, and The gate of one transistor of the pair of transistors and the gate of the other transistor of the second differential pair of transistors are commonly connected to one input terminal (one polarity) of the first pair of input terminals, and the first difference The first and second transistors in which the gate of the other transistor of the dynamic pair transistors and the gate of one transistor of the second differential pair transistors are commonly connected to the other input terminal (the other polarity) of the first input terminal pair. a second differential pair of transistors; n(
n≧2) sets of differential pair transistors, in which one of the transistors has its drains commonly connected to the source of the first differential pair transistor, and its gates are commonly connected to one input terminal (one polarity) of the second input terminal pair, and the drains of the other transistors are commonly connected to the sources of the second differential pair transistors, and the gates of the other transistors are commonly connected to one input terminal (one polarity) of the second input terminal pair. n sets of differential pair transistors that are commonly connected to the other input terminal (the other polarity) of the second input terminal pair;
A multiplier characterized by comprising: constant current sources;