JP2541868B2 - MOS transistor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a MOS transistor circuit.

[Prior Art] Since a MOS transistor exhibits a square characteristic in a saturation region,
Various circuit configurations have been conventionally proposed so as to obtain a linear transfer characteristic.

[Problems to be Solved] However, it is difficult to perform a highly accurate amplification operation with the conventional circuit configuration.

An object of the present invention is to provide a MOS transistor circuit having a simple circuit configuration and capable of highly accurate amplification operation.

[Means for Solving the Problems] In a MOS transistor circuit according to the present invention, first to fourth MOS transistors are provided on the same semiconductor substrate, and sources of the first and second MOS transistors are connected to each other (first Connection point), the sources of the third and fourth MOS transistors are connected (second connection point), and the difference between the current flowing through the first connection point and the current flowing through the second connection point is made constant. Holding current control circuit, first MOS transistor and third
Keep the voltage between each gate of the MOS transistor of
And a voltage control circuit that keeps the voltage between the gates of the second MOS transistor and the fourth MOS transistor constant and keeps the voltage between the first connection point and the second connection point constant. It is a thing.

Embodiments Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 shows a transconductor cell, which will be used to explain the basic concept of the present invention.

The transconductor cell consists of a differential pair of two MOS transistors. The first MOS transistor M1 and the second MOS transistor M2 form a first differential pair, and the third MOS transistor M3 and the fourth MOS transistor M4 form a second differential pair. These first to fourth MOS transistors M1 to M4 are formed close to each other on the same silicon substrate and have uniform characteristics. Each of the MOS transistors M1 to M4 operates in the saturation region, and its current-voltage characteristic is represented by the following equation.

Id = K (Vgs-Vt) ² (1) However, Id ... Drain current Vgs ... Gate-source voltage Vt ... Threshold voltage SN1 is the first connection point, and MOS transistor M1 and
It is a common source node for M2. SN2 is second
And a common source node for the MOS transistors M3 and M4.

VL1 and VL2 are ideal voltage sources, and a constant voltage “Vc” is applied between the gate nodes of MOS transistors M1 and M3 and between the gate nodes of MOS transistors M2 and M4.
One that holds at 1 ".

In the transconductor cell described above, node SN1
The potential difference between the node SN2 and the node SN2 is held at a constant value "Vc2", and the difference between the current "Is1" flowing at the node SN1 and the current "Is2" flowing at the node SN2 is held at a constant value "Ic".

 The following equation is obtained from the above conditions.

Is1−Is2 = i1 + i2− (i3 + i4) = Ic = constant (2) Vc1 + Vc2 = Vc = constant (3) Although the added value of the voltages “Vc1” and “Vc2” should not normally be zero, The value of either "Vc1" or "Vc2" can be zero. In particular, when the voltage "Vc2" is zero, the nodes SN1 and SN2 are virtually short-circuited.

Using the above equations (1), (2) and (3),
The differential output currents “Io1” and “Io2” are as follows.

Io1 = i1-i2 = Vin.K {(Ic / 2KVc) + Vc} = Vin.gm1 (4) Io2 = i3-i4 = Vin.K {(Ic / 2KVc) -Vc} = Vin.gm2 ... (5) ) However, Vin = Vgs1−Vgs2 = Vgs3−Vgs4 However, Vgs1… Gate-source voltage of MOS transistor M1 Vgs2… Gate-source voltage of MOS transistor M2 Vgs3… Gate-source voltage of MOS transistor M3 Vgs4… The voltage between the gate and the source of the MOS transistor M4 The equations (4) and (5) show the linear transfer characteristics of the transconductor cell shown in FIG.
Since the values of "Vc", "Ic" and "K" are all constant, very high linearity can be obtained.

The nodes "N1", "N2", "N3" and "N" shown in FIG.
Parallel coupling (short-circuiting between N1-N2 and N3-N4 respectively) and cross-coupling (short-circuiting between N1-N3 and N2-N4 respectively) of 4 "results in the differential output currents shown below, respectively.

Io3 = (i1 + i3)-(i2 + i4) = Vin (Ic / Vc) = Vin.gm3 (6) Io4 = (i1 + i4)-(i2 + i3) = Vin.2KVc = Vin.gm4 (7) By the way, FIG. 2 The bias currents “Is1” and “Is2” shown in are expressed by the following equations.

Is1 = i1 + i2 = (K / 2) [{(Ic / 2KVc) + Vc} 2 + Vin 2] ...
(8) Is2 = i3 + i4 = (K / 2) [{(Ic / 2KVc) -Vc} 2 + Vin 2] ...
(9) Here, the maximum linear output current ranges “Io1max” and “Io2max” are expressed by the following equations.

Io1max ＝ Is1o ＋ Is2o… （10） Io2max ＝ 2Is2o… （11） However, Is1o… Is1 "zero signal (Vin = 0) value Is2o…" Is2 "zero signal (Vin = 0) value As shown in Fig. 2 The circuit shown in is a class AB operation, and the output currents "Io1" and "Io2" are larger than the quiescent currents "Iso1" and "Iso2".

If the "current" Is1 "is larger than the current" Is2 ", the maximum linear input voltage range is limited by the MOS transistors M3 and M4 forming a differential pair. ) Equation (for example,
Io2 (Vinmax) = Is2 (Vinmax)), the maximum linear input voltage range "Vinmax" is as follows.

Vinmax = (Ic / 2KVc) −Vc (12) According to detailed analysis, “Ic” and “Vc” need to satisfy the following conditions.

Ic> 2KVc ² (13) However, this condition does not affect the generality of the present invention.

By the way, as is clear from the equation (6), when the output nodes N1 to N4 are connected in parallel, the transconductance value "gm3 = Ic / Vc" can be completely controlled by an external parameter. That is,
Since "gm3" does not include the parameter "K", the transfer characteristics are independent of factors such as process parameters, geometrical parameters or operating temperature. Therefore, a highly accurate on-chip automatic tuning circuit can be constructed.
It is only necessary to pay attention to the matching of S transistors. However, since the MOS transistors of the transconductor cell are usually formed close to each other, the matching between the MOS transistors is extremely good.

In addition, as shown in the above equation (7), the output nodes N1 to
When N4 is cross-connected, the transconductance "gm4" includes the parameter "K", but even in this case, highly accurate class AB operation can be achieved.

Next, a specific circuit example of the present invention will be described with reference to FIG. The reference numerals in FIG. 1 and FIG. 2 correspond to each other.

M5 to M10 are MOS transistors, and MOS transistors M
It is formed on the same silicon substrate as 1 to M4. CR is an ideal current source that supplies a constant current “Ic”, and VL is an ideal voltage source that holds a constant voltage “Vc”. ZL is the load. The NIC is a negative impedance converter, which virtually short-circuits the nodes SN1 and SN2. Negative impedance converter NI
Since the output currents of C are equal, the difference between the currents "Is1" and "Is2" is equal to the current value "Ic" of the current source CR. This negative impedance converter NIC is, for example, "The CMO
S Negative Impedance Converter "(RLBrennan, TR
Viswanathan, JV Hanson, IEEE J. Solid-State Cire., V
o123, Oct.1988., pp.1272-1275) or `` Analysis a
nd design of snalog integrated circuits "(J. Wiley
& Sons, New York, 1984, 2nd edition, p.734). AL is an active load, is composed of a p-channel current mirror, and supplies current to the nodes N1 to N4. Negative impedance converter NIC, MOS above
The transistors M9 and M10 form a current control circuit, and the above-mentioned negative impedance converter NI
A voltage control circuit is constituted by C, MOS transistors M5, M6, M7 and M8.

Next, a computer simulation of the circuit example shown in FIG. 2 will be described.

The element sizes of the MOS transistors M1 to M4 used in the simulation are a channel width W = 6 micrometers and a channel length L = 24 micrometers, and each source is connected to a substrate. Also, the transconductance gm1 to g
The values of m4 are 34, 26, 60 and 8 microsiemens, respectively.

As a result of computer simulation using the above parameters, total harmonic distortion of output currents Io1, Io2, Io3, and Io4 obtained via the load ZL (hereinafter referred to as "THD").
Became as follows. THD for single-ended inputs with 1 to 2 peak and 2 volt peak to peak.
Were less than 0.1% and less than 0.25%, respectively. In addition, THD is 0.015% each for balanced input with peak to peak of 1 volt, 2 volt and 4 volt.
Below, it was below 0.04% and below 0.17%. Thus, it can be seen that the transconductor cell of this example has very excellent characteristics.

[Effect] The MOS transistor circuit according to the present invention can achieve highly accurate operation with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of the present invention, and FIG. 2 is an electric circuit diagram showing the basic concept of the present invention. M1 ... First MOS transistor M2 ... Second MOS transistor M3 ... Third MOS transistor M4 ... Fourth MOS transistor SN1 ... First connection point SN2 ... Second connection point NIC ... Negative impedance converter M4 to M10 … MOS transistors

Claims (1)

(57) [Claims] 1. A first MOS formed on the same semiconductor substrate.
A transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; a first connection point to which the sources of the first MOS transistor and the second MOS transistor are connected; A second connection point where the sources of the third MOS transistor and the fourth MOS transistor are connected to each other, and a constant difference between the current flowing through the first connection point and the current flowing through the second connection point. A current control circuit for maintaining the voltage between the gates of the first MOS transistor and the third MOS transistor constant, and
And a voltage control circuit that keeps the voltage between the gates of the MOS transistor and the fourth MOS transistor constant and keeps the voltage between the first connection point and the second connection point constant. MOS transistor circuit.