JP3036121B2 - Pseudo-log IF amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo logarithmic IF amplifier which is approximated by a broken line, and more particularly to a pseudo logarithmic IF amplifier formed on a C-MOS integrated circuit.

[0002]

2. Description of the Related Art As a pseudo logarithmic IF amplifier of a broken line approximation type formed on a C-MOS integrated circuit, for example, the one shown in FIG. 6 is conventionally known. This is disclosed in
Japanese Patent Application Laid-Open No. 292010/292010, a dual-wave rectifier comprising two sets of mismatched differential pair transistors is provided in each of differential amplifiers cascaded in multiple stages, and the outputs of each double-wave rectifier are added. It was made. Hereinafter, an outline of the operation will be described.

A mismatched differential pair transistor (T
_{n + 1} and T _{(n + 1) k} ) have the same ratio of gate width W to gate length L (W / L) and 1: k (k> 1), respectively. The transistors having the ratio of 1 (T _{n + 1} , T
_{n + 1} ) and transistors having a ratio of k (T _{(n + 1) k} , T
_{Between (n + 1) k} ), the drains and the gates are commonly connected. Therefore, α is expressed by the following equation 1 using the ratio (W ₁₁ / L ₁₁ ) of the transistor T ₁₁ . In the equation, μ _n is the mobility of the transistor, and C _OX is the gate oxide film capacitance.

[0004]

(Equation 1)

The ratio k between one mismatched differential pair transistor is the ratio (W ₁₁ / L ₁₁ ) of the first mismatched differential pair transistor (T ₁₁ , T _1k ). W _1k /
L _1k ) is determined as in the following Expression 2.

[0006]

(Equation 2)

Further, a mismatched differential pair transistor (T ₁₁ ,
T _1k ), the gate-source voltages are V _gS1 , V _gS2 ,
Placing the threshold voltage V _t, I ₁ ~I ₄ is expressed as the following equation 3 to the 6.

[0008]

(Equation 3)

[0009]

(Equation 4)

[0010]

(Equation 5)

[0011]

(Equation 6)

Then, since I ₁₁ can be expressed by the following equations 7 and 8, and V _IN can be expressed by the following equation 9, ΔI ₁ can be obtained as in equation 10.

[0013]

(Equation 7)

[0014]

(Equation 8)

[0015]

(Equation 9)

[0016]

(Equation 10)

That is, Expression 10 indicates that the current ΔI ₁ has a square-wave dual-wave rectification characteristic with respect to the input voltage V _IN . Similarly, the current (ΔI ₂ ,..., ΔI _{n + 1} ) from the second-stage mismatched differential transistor to the n-th mismatched differential transistor is expressed by the following equations (11) and (12). I get it.

[0018]

[Equation 11]

[0019]

(Equation 12)

Here, the values of the currents (ΔI ₁ , ΔI ₂ ,..., ΔI _{n + 1} ) and the constant current sources (I ₁₁ ,
I ₂₂ ,..., I _{n (n + 1)} )
It is clear that 5 is satisfied.

[0021]

(Equation 13)

[0022]

[Equation 14]

[0023]

(Equation 15)

Here, no matter how large the values of V _IN , V ₁ ,..., V _OUT are, the currents (ΔI ₁ , ΔI ₂ ,.
_{n + 1} ) falls within the range of the values shown in Expressions 13 to 15.
Since V ₁ ,..., V _OUT are the outputs of the differential amplifier, when the input signal V _IN gradually increases, V _OUT changes to V _OUT.
The output up to ₁ saturates sequentially. Therefore, the output current I of the transistors (T ₁₀ ,..., T ₆₀ ) forming the adder is calculated.
_OUT While it is Equation 16, the output current I _OUT is
The maximum output voltage of the differential amplifier is used as a current source (I ₀₁ , I
₀₂ ,..., I _0n ) and resistors (R ₀₁ , R ₀₂ ,..., R _0n )
Can be set to a constant sign value by setting. That is, the characteristic of the output current I _OUT can be made approximately logarithmic with respect to the input voltage V _IN .

[0025]

(Equation 16)

[0026]

The above-described conventional pseudo-logarithmic IF amplifier has one mismatched differential pair transistor and one transistor.
Since two double-wave rectifiers are configured, the current source needs to be twice as many as the number of rectifiers, and current consumption increases. In addition, the circuit itself requires two mismatched differential pair transistors for one rectifier, and there is a problem that the circuit scale increases.

An object of the present invention is to provide a pseudo logarithmic IF amplifier capable of reducing current consumption and circuit scale.

[0028]

In order to achieve the above object, a pseudo-log IF amplifier according to the present invention has the following configuration. That is, the pseudo-logarithmic IF amplifier of the first invention is a differential amplifier cascade-connected in multiple stages, and a half-wave rectifier receiving a corresponding one of the input signal or the output signal of the differential amplifier, respectively. A set (n ≧ 1) of mismatched differential pair transistors (n sets of paired transistors having different ratios of gate width to gate length), and the n sets of mismatched differential pair transistors are connected to the DC of the differential output current. comprising a half-wave rectifier and to output component, and an adder for adding all the half-wave rectifier respective output DC component, the n
Sets of mismatched differential pair transistors where n ≧ 2
Are two sets of parallel-connected
Gate width and gate of each matched differential pair transistor
Transistors with smaller length ratios and larger ratios
Drains between the two transistors
And the gates are connected in common, and n is n ≧ 2
Width and gain of mismatched differential pair transistors in
The rectification characteristics by changing the ratio of the
To improve the linearity of the logarithmic characteristic by forming a rectifier
It is characterized by having .

Further, a pseudo-logarithmic IF amplifier according to a second aspect of the present invention comprises:
A differential amplifier cascaded in multiple stages, and a half-wave rectifier receiving a corresponding one of input signals or output signals of the differential amplifier, each comprising n sets (n ≧ 1) of mismatched differential pairs A half-wave rectifier comprising transistors (n sets of paired transistors having different ratios of gate width to gate length), wherein the n sets of mismatched differential pair transistors output the differential output current as it is ; An adder that receives all the outputs of the half-wave rectifiers, adds all of them, and outputs a DC component as a result of the addition, or receives the output of each of the half-wave rectifiers, forms the DC component thereof, and adds them.
And n sets of mismatch differences when n is n ≧ 2
Active transistors are driven in parallel by different constant current sources
Each of the two connected mismatched differential pair transistors
Transistors with smaller ratio of gate width to gate length
And between the transistors with the larger ratio.
And the drains and the gates are connected in common,
Mismatched differential pair transistors when n is n ≧ 2
The gate width and gate length ratio and the value of the constant current source
Of rectifiers with different rectification characteristics
Is characterized by having a configuration for improving

Further, a pseudo logarithmic IF amplifier according to a third aspect of the present invention includes:
A differential amplifier cascaded in multiple stages and a half-wave rectifier receiving a corresponding one of the input signal or the output signal of the differential amplifier, wherein each of the n sets (n ≧ 1) of M
An OS mismatched differential pair transistor (n sets of paired transistors having different gate width to gate length ratios) is provided so that the n sets of MOS mismatched differential pair transistors output the DC component of the differential output current. And a summer for adding all the output DC components of the half-wave rectifier. The half-wave rectifier includes a MOS mismatched differential pair transformer.
Of the output component of the transistor is almost proportional to the input voltage.
Removes flow components and is proportional to the square of the input voltage
Has a frequency that is twice the input voltage from the square characteristic component
By removing two AC components, the differential output current
It is characterized by outputting a flow component .

[0031]

Next, the operation of the pseudo-logarithmic IF amplifier of the present invention configured as described above will be described. According to the present invention, a half-wave rectifier including n sets (n ≧ 1) of mismatched differential pair transistors is provided as a rectifier, and a DC component of a differential output current is added (first invention, second invention). Alternatively, the differential output current is added, and the DC component is extracted therefrom (second invention). Therefore, it is possible to reduce current consumption and circuit size. When n satisfies n ≧ 2 (third invention), the linearity of the logarithmic characteristic is improved.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a pseudo-logarithmic IF amplifier according to one embodiment of the present invention. In FIG. 1, a pseudo-logarithmic IF amplifier according to the first embodiment includes a differential amplifier A cascaded in multiple stages.
_i (i = 1, 2,..., n), a half-wave rectifier receiving a corresponding input signal or output signal of the differential amplifier A _i , and all outputs of the respective half-wave rectifiers are added. And an adder.

Each half-wave rectifier has a pair of mismatched differential pair transistors (M _{(n + 1) 1} ,
M _{(n + 1) 2} ), current mirror circuits (M _{(n + 1) 3} , M _{(n + 1) 4} ) for forming a difference current, and a capacitor C _{0 (} for eliminating an AC component in the difference current). _{n + 1)} and a constant current source I _{0 (n + 1),} and configured to output a DC component of the differential output current. The mismatched differential pair transistors (M _{(n + 1) 1} , M
_{(n + 1) 2)} The mutual ratio of the transistors M _{(n + 1) 1} of the gate width to the gate length, the transistor M _{(n + 1)} smaller than the ratio of the _second gate width and a gate length. The adder includes a current mirror circuit (M ₁₀ , M ₂₀ ) and adds all the outputs (DC components of the differential output current) of each half-wave rectifier.

In the above configuration, the ratio (W / L) of the gate width W and the gate length L between the mismatched differential pair transistors of each half-wave rectifier does not need to be the same. For the sake of convenience. That, alpha _1, using the gate width to gate length ratio of the transistors _{M 11 (W 11 / L 11} ) represented by the following formula 17.

[0035]

[Equation 17]

The ratio k ₁ between one mismatched differential pair transistor is determined by the ratio (W ₁₁ / L ₁₁ ) of each of the first-stage mismatched differential pair transistors (M ₁₁ , M ₁₂ ), Same (W ₁₂
/ L ₁₂ ) and the following equation (18).

[0037]

(Equation 18)

Then, the drain currents I _d11 and I _d12 of the transistors M ₁₁ and M ₁₂ can be expressed by the following equations (19) and (20).

[0039]

[Equation 19]

[0040]

(Equation 20)

The constant current source I ₀₁ and the input voltage V _IN are represented by the following equations (21) and (22).

[0042]

(Equation 21)

[0043]

(Equation 22)

From the above equations, ΔI ₁ = I _d11 −I _d12
Is obtained by the following Expression 23.

[0045]

(Equation 23)

[0046] Therefore, placing the [Delta] I ₁ by Equation 24, the DC component [Delta] I _{1 DC} The formula 25,2 square characteristic component [Delta] I
_1SQ can be expressed by Expression 26, and the AC component ΔI _1DIFF can be expressed by Expression 27.

[0047]

(Equation 24)

[0048]

(Equation 25)

[0049]

(Equation 26)

[0050]

[Equation 27]

That is, ΔI _1DIFF can be considered to be a DC characteristic of a normal so-called matched differential pair which is substantially proportional to the input voltage V _IN , and is thus an AC component eliminated by the capacitor C ₀₁ . Accordingly, the DC component of [Delta] I ₁ (bar [Delta] I _1), as in equation 28, becomes the sum of the [Delta] I _{1 DC} and square characteristic component [Delta] I _1SQ DC component (bar [Delta] I _1SQ), the input voltage V
_{When IN} is considered to be a sine wave and expressed by Expression 29, Expression 30 is obtained.

[0052]

[Equation 28]

[0053]

(Equation 29)

[0054]

[Equation 30]

Similarly, the DC component of the output current ΔI ₂ of the second-stage mismatched differential pair transistor (M ₂₁ , M ₂₂ ) is given by the following equation (3).
1. Final stage mismatched differential pair transistors (M _{(n + 1) 1} , M
The DC component of the output current ΔI _{(n + 1)} of _{(n + 1) 2} ) is obtained as shown in Expression 32.

[0056]

(Equation 31)

[0057]

(Equation 32)

Thus, the output (DC component of the differential output current) of each half-wave rectifier is a current mirror circuit (M ₁₀ , M ₂₀ ).
_Is added by an adder consisting of
3).

[0059]

[Equation 33]

Accordingly, the output voltage V _RSSI of the adder is obtained by the following equation (34).

[0061]

(Equation 34)

That is, in the circuit of FIG.
_{When IN} gradually increases, the output from V _OUT to V ₁ sequentially saturates. This is shown in FIG. 2 in which the input voltage V _IN is expressed in dB.

As is clear from the above description, the capacitor may be provided on the adder side. Therefore, the half-wave rectifier and the adder can be configured as follows, for example. That is, as shown in FIG. 3, the half-wave rectifier includes mismatched differential pair transistors (M _{(n + 1) 1} , M _{(n + 1) 2} ) and a constant current source I
_{0 (n + 1)} and outputs the differential output current as it is.
Then, a current mirror circuit (M ₃₀ , M ₄₀ ) for forming a difference current and a capacitor C ₀ for eliminating an AC component in the difference current are provided in the adder, and a DC component is formed in the adder and added. To Alternatively, as shown in FIG. 4, a half-wave rectifier, the same as in FIG. 3, the adder provided a capacitor C ₀ on the output side, so that it is removed from the DC component after the addition of the total differential current. These have a great effect on reducing the circuit scale and the like.

Next, each half-wave rectifier can be composed of n sets of mismatched differential pair transistors where n ≧ 2, an example of which is shown in FIG. 5 (n = 2). This is the same as (M ₁₁ , M ₁₂ ) in FIG.
₁₅ , M ₁₆ ) in parallel. That is, mismatched differential pair transistors (M ₁₁ , M ₁₂ ) and (M ₁₅ , M ₁₆ )
Are driven by different constant current sources I ₀₁ and I ₀₁ ′, respectively, and the transistors (M ₁₁ and M ₁₅ ) having a smaller ratio of gate width to gate length and the transistors (M ₁₁ ) having a larger ratio are used. ₁₂ , M ₁₆ ), the drains and the gates are commonly connected.

An additional mismatched differential pair transistor (M ₁₅ ,
M ₁₆ ), the output current Δ
I ₁₂ is Motomari the following formula 35, the DC component formula 36
become that way.

[0066]

(Equation 35)

[0067]

[Equation 36]

Here, in Equations 30 and 32, α ₂
= And α _1. The cascaded differential amplifiers A _i
It need not be all the same gain, for convenience and the same gain g _V of explanation, the following equation 37 is established.

[0069]

(37)

Then, Equation 30 is represented by the following Equation 38.

[0071]

(38)

That is, G _V is defined as in the following Expression 39,
If the input voltage V _IN is expressed in dB, the DC component of the output current ΔI ₁ is shifted from the DC component of the output current ΔI ₁₂ by (１ ／) G _V toward the lower input level according to Expression 38. You can see that

[0073]

[Equation 39]

The same applies to the two sets of mismatched differential pair transistors in the second and subsequent stages, and the operating dynamic range covered by each two sets of mismatched differential pair transistors is (1/1). 2) next to each G _V, as a result, not
Matching differential pair transistor gate width to gate length ratio and constant
Rectifiers with different rectification characteristics by changing the value of the current source
In the case of ≧ 2, it is basically formed with almost the same circuit configuration.
As a result, the current consumption is reduced and the circuit scale is reduced, and the linearity of the logarithmic characteristic is improved.

On the other hand, it is assumed that the following equation 40 holds for the gain g _V of the differential amplifier A _i .

[0076]

(Equation 40)

Then, Expression 36 is expressed by Expression 41 below.

[0078]

[Equation 41]

[0079] That is, in turn, be in dB the input voltage V _IN, the DC component of the output current [Delta] I ₁ is (1/2) with respect to the DC component of the output current [Delta] I ₁₂ G _V only towards the input level is high The operation will be shifted. The same is true for the two sets of mismatched differential pair transistors in the second and subsequent stages, and the operating dynamic range covered by each two sets of mismatched differential pair transistors is (1/2) G next by _V, with the result that the linearity of the logarithmic characteristic can be improved.

Further, when the number of mismatched differential pair transistors per stage is n = m, and the following equation (42) or (43) is satisfied, the operating dynamic range covered by the mismatched differential pair transistors at each stage is as follows: it is (1 / m) next to each G _V, is the linearity of the logarithmic characteristic can be further improved.

[0081]

(Equation 42)

[0082]

[Equation 43]

[0083]

As described above, according to the pseudo-logarithmic IF amplifier of the present invention, a half-wave rectifier comprising n sets (n ≧ 1) of mismatched differential pair transistors is provided as a rectifier. Adding the DC component of the output current , or adding the differential output current and extracting the DC component from it ,
When n is n ≧ 2 ( first invention and second invention ), the linearity of the logarithmic characteristic is improved , and the MOS mismatch
A half-wave rectifier is configured by a differential pair transistor configuration (No.
3) In the case, the current consumption is reduced and the circuit scale is reduced.
Becomes possible .

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a pseudo-logarithmic IF amplifier (n = 1) according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram of the pseudo-logarithmic IF amplifier of the present invention.

FIG. 3 is a circuit diagram of a pseudo-logarithmic IF amplifier (n = 1) according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a pseudo logarithmic IF amplifier (n = 1) according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram of a half-wave rectifier (n = 2) used in a pseudo-logarithmic IF amplifier according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional pseudo-logarithmic IF amplifier.

[Explanation of symbols]

A ₁ to A _n differential amplifiers M _{(n + 1) 1} mismatch differential pair transistors M _{(n + 1) 2} mismatches differential pair transistors M ₁₅ mismatched differential pair transistors M ₁₆ mismatched differential pair transistors M _{(n + 1) 3} transistor M _{(n + 1) 4} transistor M ₁₀ ~M ₄₀ transistor I 0 _{(n + 1)} constant-current source

Claims (3)

(57) [Claims] 1. A differential amplifier cascaded in multiple stages and a half-wave rectifier receiving a corresponding one of an input signal or an output signal of the differential amplifier, respectively
A set (n ≧ 1) of mismatched differential pair transistors (n pairs of transistors having different ratios of gate width to gate length);
A half-wave rectifier configured such that the n sets of mismatched differential pair transistors output a DC component of the differential output current; and an adder that adds all output DC components of the half-wave rectifier. N sets of mismatched differential pair transistors when n is greater than or equal to 2, are connected in parallel by two different constant current sources.
The drains and the gates are commonly connected between the transistors having the smaller ratio of the gate width and the gate length of the pair of mismatched differential pair transistors and between the transistors having the larger ratio, and the n Is n ≧ 2
In order to improve the linearity of the logarithmic characteristic by forming a rectifier having a different rectification characteristic by changing the ratio of the gate width and the gate length of the mismatched differential pair transistor and the value of the constant current source in the case of Pseudo-log IF amplifier. 2. A differential amplifier cascaded in multiple stages, and a half-wave rectifier respectively receiving a corresponding one of an input signal or an output signal of the differential amplifier, wherein
A set (n ≧ 1) of mismatched differential pair transistors (n pairs of transistors having different ratios of gate width to gate length);
A half-wave rectifier configured such that the n sets of mismatched differential pair transistors output the differential output currents as they are; a DC component of the addition result obtained by receiving the outputs of the respective half-wave rectifiers and adding all the outputs; Or an adder that receives the output of each of the half-wave rectifiers, forms a DC component thereof, and adds the DC components. When n is n ≧ 2, n sets of mismatched differential pairs are provided. The transistors are connected in parallel by two driven by different constant current sources.
The drains and the gates are commonly connected between the transistors having the smaller ratio of the gate width and the gate length of the mismatched differential pair transistors of the set and between the transistors having the larger ratio, and the n Is n ≧ 2
In order to improve the linearity of the logarithmic characteristic by forming rectifiers having different rectification characteristics by changing the ratio of the gate width and gate length of the mismatched differential pair transistor and the value of the constant current source in the case of Pseudo-log IF amplifier. 3. A differential amplifier cascaded in multiple stages and a corresponding one of an input signal or an output signal of the differential amplifier.
Rectifiers each receiving
A set (n ≧ 1) of MOS mismatched differential pair transistors (gates)
N pairs of transistors with different ratios of gate width and gate length)
The n sets of MOS mismatched differential pair transistors are
Is configured to output the DC component of the differential output current of
A half-wave rectifier; and an adder for adding all output DC components of the half-wave rectifier.
Equipped, The half-wave rectifier is connected to the MOS mismatched differential pair transistor.
AC component that is almost proportional to the input voltage
, And 2 proportional to the square of the input voltage.
AC having twice the frequency of the input voltage from the squared characteristic component
DC component of the differential output current by removing the component
Output A pseudo-log IF amplifier.