JPH0656940B2 - Logarithmic amplifier circuit - Google Patents

Description

The present invention relates to a logarithmic amplifier circuit, and more particularly to a logarithmic amplifier circuit in a MOS integrated circuit.

[Prior Art] Conventionally, a logarithmic amplifier circuit of this type has been realized in a bipolar integrated circuit as shown in FIG.
It did not exist in integrated circuits.

[Problems to be solved by the invention]

Since the conventional logarithmic amplifier circuit described above is a bipolar integrated circuit, it has the drawback that it cannot be integrated on a MOS integrated circuit. For example, when a logarithmic IF amplifier is constructed, the baseband section is constructed by the bipolar integrated circuit. Then, there is a drawback that the current consumption increases.

[Means for solving problems]

A logarithmic amplifier circuit according to the present invention is a cascade-connected multistage MOS.
The ratio W / L of the gate width W and the gate length L of each transistor is input to the first stage input or each stage output of the differential amplifier, and is 1 / k (k>
The two differential pairs, which are equal to each other in 1), have mutually opposite inputs, and the drains of the transistors having the same W / L are connected in common. The in-phase outputs of the above are commonly connected.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In FIG. 1, the differential pairs driven by the current sources I ₀₁ , I ₀₂ , ..., I _0n are sequentially connected in cascade. It is shown by an equation that the two differential pairs driven by two current sources I ₁₁ , I ₂₂ , ..., I _n , _{n + 1} are square-wave double-wave rectifiers.

α = μ _n (C _0x / 2) (W ₁ / L ₁ ) (1) (where μ _n is the mobility, C _0x is the gate oxide film capacitance. W ₁ and L ₁ are the gate width W and the gate of the transistor T11. Long L.

k = (W ₂ / L ₂ ) / (W ₁ / L ₁ ) (2) (where W ₂ and L ₂ are the gate width W and the gate length L of the transistor T1k). In the pair of differential pairs composed of the transistors T11 and T1k, the gate-source voltage is V _gs1 , V _gs2 , and the threshold voltage is V _gs1 .
putting a _{t I 1 = α (V gs1} -V t) 2 (3) I 2 = kα (V gs2 -V t) 2 (4) I 3 = α (V gs3 -V t) 2 (5) I ₄ = kα (V _gs4 −V _t ) ² (6) Here, I ₁ + I ₂ = I ₁₁ (7) I ₃ + I ₄ = I ₁₁ (8) V _1N = V _gs1 −V _gs2 = V _gs4 −V _gs3 (9) Is asked. It can be seen from the equation (11) that the current ΔI ₁ has a square-wave double-wave rectification characteristic with respect to the input voltage V _IN . As well ΔI ₁ , ΔI ₂ , ..., Δ shown in equations (11) to (13)
The value of I _{n + 1} is −2I ₁₁ ≦ ΔI ₁ ≦ 2I ₁₁ (14) −2I ₂₂ ≦ ΔI ₂ ≦ 2I ₂₂ (15) −2I _{nn + 1} ≦ ΔI _{n + 1} ≦ 2I _{nn + 1} (16) Since it is clear that there is I _1N , V ₁ , ..., V _OUT
No matter how large the value of becomes, it enters the value shown by the equation (14) to the equation (16). If V ₁ , ..., V _OUT are outputs of the differential amplifier, the output from V _OUT to V _{1 is} sequentially saturated when the input signal V _1N is gradually increased.

Therefore, the transistors T ₁₀ , T ₂₀ ; T ₃₀ , T ₄₀ ; T ₅₀ , T
Assuming that I _OUT = ΔI ₁ + ΔI ₂ + ... + ΔI _{n + 1} (17) by ₆₀ , the output current I _OUT is the maximum output voltage of the differential amplifier as current sources I ₀₁ , I ₀₂ , ... I _0N and resistor R ₀₁ ,
By setting R ₀₂ , ... R _0n , a constant code value can be obtained.

Therefore, the output current I _OUT characteristic can be approximately logarithmic characteristic with respect to the input signal V _1N as shown in FIG.

〔The invention's effect〕

As described above, the present invention has the effect of realizing a logarithmic amplifier in a MOS integrated circuit. For example, if a logarithmic IF amplifier is configured, the parts after IF can be realized on a one-chip MOS integrated circuit, and low current consumption can be achieved. effective.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a characteristic diagram and FIG. 3 is a circuit diagram showing a conventional example. T ₀₁ , T _0n , T ₁₁ , T _{n + 1} , ₁ , T _{n + 1} , _k , T ₁₀ , ..., T
₆₀ …… Transistor, R ₀₁ ,…, R _0n …… Resistor, T ₀₁ ,
..., I _0n , I ₁₁ , ..., I _n , _{n + 1} ... Current source.

Claims (1)

[Claims] 1. A ratio W / L of a gate width W of a transistor to a gate length L of two transistors forming a differential pair in a first stage input or each stage output of a cascaded multistage MOS differential amplifier. In the transistors, two equal differential pairs of 1 / k (k> 1) have mutually opposite inputs, and the drains of the transistors having the same W / L are connected in common. A logarithmic amplifier circuit, in which in-phase outputs of all two pairs of differential pairs are commonly connected.