JP2914005B2 - Differential amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit,
In particular, the present invention relates to a differential amplifier circuit composed of MOS transistors.

[0002]

2. Description of the Related Art When a differential amplifier circuit is composed of MOS transistors, the linearity of transconductance poses a problem. As a differential amplifier circuit with improved linearity,
Conventionally, for example, those shown in FIGS. 11, 12, and 13 are known. These are referred to since they are described in detail in the following documents.

FIG. 11: A. Nedungadi and TRViswanathan
“Design of Linear CMOS Transco-nductance Element
s ”IEEE TRANSACTION ON CIRCUITS AND SYSTEMS, VOL, C
AS-31, NO.10, pp.891-894, OCTOBER 1984.

FIG. 12: Zhenhua Wang and Walter Guggenbu
hl “A Voltage-Controllable Line-ar MOS Transconduc
tor Using Bias Offset Technique ”IEEE JOURNAL OF
SOL-ID-STATE CIRCUITS, VOL.25, NO.1, PP.315-317, FEBRU
ARY 1990.

FIG. 13: Francois Krummenacher and Norber
t Joehl “A 4-MHz CMOS Continuo-us-Time Filter wit
h On-Chip Automatic Tuning ”IEEE JOURNAL OF SOLID-
STA-TE CIRCUITS, V0L.23, NO.3 pp.750-758, JUNE 1988.

[0006]

However, the conventional differential amplifier circuit having improved transconductance linearity has a problem that the circuit scale is increased.

An object of the present invention is to provide a differential amplifier circuit having a novel configuration which can improve the linearity of transconductance without increasing the circuit scale.

[0008]

To achieve the above object, a differential amplifier circuit according to the present invention has the following configuration. That is,
The differential amplifier circuit according to the first invention is a transconductor
The differential input pair is composed of two FETs (MOS transistors) of one differential pair and one FET of the other differential pair. The gates of the pair of other FETs and the gates of the other pair of FETs in one differential pair and the other pair of FETs in the other differential pair are connected in common; The output pair is formed by commonly connecting the drains of one FET and the drains of the other FET of the FET pair in each differential pair.

[0009] The differential amplifier circuit of the second invention, Trang
The conductance parameter and the drive current
To be a differential pair of different N sets (N ≧ 3); a differential input pair, the differential pair in the FET (MOS transistors) to the one FET of gates and other the gates of the FET, respectively A differential output pair, the drains of the other one of the at least one pair of FETs and one of the remaining pair of FETs, and one of the at least one pair of FETs and the remaining FE.
The drains of the T pair and the other FETs are connected to each other in common;

[0010]

Next, the operation of the differential amplifier circuit of the present invention configured as described above will be described. In the present invention, two differential pairs (first invention) or three or more differential pairs (second invention) are
The input and output between the ET pairs are connected in a predetermined relationship. Therefore, since the configuration can be made without the need for a special additional circuit, it is possible to provide a differential amplifier circuit that can improve the linearity of the transconductance without increasing the circuit scale.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a differential amplifier circuit according to a first embodiment of the present invention. This differential amplifier circuit has two differential pairs:
A (M1, M2) transistor pair and a differential pair including a constant current source 1 (value I ₀ ) for driving the same, and a (M3, M4) transistor pair and a constant current source 2 (value a ×
I ₀ ).

Here, the transconductance parameter β of the transistor is represented by mobility μ, gate oxide film capacitance C _OX per unit area, gate width W, and gate length L.
Can be expressed as Equation (1) using the transistor pair (M1, M1
Assuming that that of 2) is 1, the transistor pair (M3, M
In 4), it is b times. The constants a and b do not become 1 at the same time, but a ≦ 1 and b ≦ 1. still,
As is evident from Equation 1, the module is produced in the same manufacturing process,
And the gate oxide film capacitance C per unit area
_{If OX} is the same, transconductance
The difference of the parameter β is the ratio of the gate width W to the gate length L.
(W / L).

[0013]

## EQU1 ## β = μC _OX (W / L) (1/2)

[0014] The differential input pair voltage V _in is applied, between the two transistor pairs mutually gates of one transistor M1 and the gate and between the other transistor M2 and one transistor M3 of the other transistor M4 Are connected in common. The differential output pair is configured by mutually connecting the drains of the transistors M1 and M3 and the drains of the other transistors M2 and M4 in common between the two transistor pairs.

In the above configuration, assuming that the device operates in the saturation region, the drain current I _{d1 of} M1 becomes
Of the drain current I _d2 is the formula 3, M3 of the drain current I _d3
Is given by Equation 4, and the drain current I _{d4 of} M4 is given by Equation 5.

[0016]

## EQU2 ## I _d1 = β (V _GS1 −V _T ) ²

[0017]

## _EQU3 ## I _d2 = β (V _GS2 −V _T ) ²

[0018]

## EQU4 ## I _d3 = bβ (V _GS3 −V _T ) ²

[0019]

## EQU5 ## I _d4 = bβ (V _GS4 −V _T ) ²

Here, V _T is a threshold voltage, V
_GSi is a gate-source voltage.

Further, a value I ₀ of the constant current source 1 Equation 6, the value aI ₀ The formula 7 of the constant current source 2, the difference between the input voltage V _in the gate-source voltage between transistors mutual each differential pair Equation 8 is equal to

[0022]

I ₀ = I _d1 + I _d2

[0023]

AI ₀ = I _d3 + I _d4

[0024]

[Equation 8] _{V in = V GS1 -V GS2 =} V GS4 -V GS3

From equations (1) to (8), the difference current ΔI ₁ between the drain currents of the transistors M1 and M2 is given by equation (9).
The difference current ΔI between the drain currents of the transistors M3 and M4
₂ becomes Equation 10. In Equation 10, β ′ is represented by Equation 11, and I ₀ ′ is represented by Equation 12.

[0026]

(Equation 9)

[0027]

(Equation 10)

[0028]

Equation 11 β ′ = bβ

[0029]

## EQU12 ## I ₀ '= aI ₀

[0030] Thus, the differential current ΔI of the differential output current of the differential amplifier circuit is a mathematical expression 13, the conductance of the differential amplifier circuit is obtained by differentiating the equation 11 by the input voltage V _in ( Equation 14).

[0031]

[Expression 13] ΔI = ΔI ₁ + ΔI ₂

[0032]

[Equation 14]

[0033] Here, the input voltage range in which the differential coefficient of [Delta] I ₁ and [Delta] I ₂ does not become 0 although the equation 15 or the 16, the [Delta] I ₁ is an input voltage range shown in Equation 15 Equation 17
Similarly, in the input voltage range shown in Expression 16, Δ
Since I ₂ can be approximated by Expression 18, Expression 14 is expressed by Expression 19
Can be approximated by

[0034]

| V _in | ≦ I ₀ / β

[0035]

| V _in | ≦ I ₀ ′ / β ′

[0036]

[Equation 17]

[0037]

(Equation 18)

[0038]

[Equation 19]

[0039] For Equation 19 becomes a straight line, since the section V _in ² may if 0, a set as in Equation 11 and Equation 12, the relationship of b that may satisfy the formula 20 Become.

[0040]

[Mathematical formula-see original document] b√b = √a

Accordingly, I is calculated so that the expression 20 is satisfied.
If the ratio of ₀ 'and β' is selected, the transconductance can be linearized in the approximate expression. FIG. 2 shows the transconductance when the values of a and b are variously changed. From FIG. 2, if the allowable transconductance to 6% about ± for values of V _in = 0, it is understood that available up to about 0.9 relative to the operating input voltage range transconductance is not zero.

Next, FIG. 3 shows a differential amplifier circuit according to a second embodiment of the present invention. The circuit of the second embodiment includes three differential pairs, namely, a transistor pair of (M1, M2) and a differential pair having a constant current source 1 (value I ₀ ) for driving the transistor pair, and (M
3, M4) and a differential pair including a constant current source 2 (value a × I ₀ ) for driving the transistor pair, a (M5, M6) transistor pair and a constant current source 3 (value a ′
× I ₀ ). In addition,
The conductance parameter β between the three transistor pairs (M1, M2) (M3, M4) (M5, M6)
Is (M1, M2) :( M3, M4) :( M5, M
6) = 1: b: b '.

[0043] In FIG. 3, the differential input pair input voltage V _in is applied, among the three transistor pairs each other,
The gates of one transistor (M1, M3, and M5) and the gates of the other transistors (M2, M4, and M6) are commonly connected.

The differential output pair includes one transistor pair (M1, M1) between the three transistor pairs.
2) and the other transistor (M) of the remaining transistor pair (M3, M4) (M5, M6).
4 and M6) and between the other transistor M2 of one transistor pair (M1, M2) and one of the remaining transistor pairs (M3, M4) (M5, M6) and the drains of transistors (M3 and M5). Are connected in common.

In the above configuration, the difference current ΔI ₁ between the drain currents of the transistor pair (M1, M2) is calculated by the following equation (21) using the same procedure as described above.
The difference current ΔI ₂ between the drain currents of 4) is expressed by Equation 22, the difference current ΔI ₃ between the drain currents of the transistor pair (M5, M6).
Is given by Expression 23, so that the differential output current ΔI is given by Expression 24.

[0046]

(Equation 21)

[0047]

(Equation 22)

[0048]

(Equation 23)

[0049]

(Equation 24)

[0050] In Equation 24, so that the transconductance is linear, the coefficient of the cube of section V _in at a 0, a, b, a ' , b' when seeking a relationship equation 25 The transconductance characteristics of the circuit of the second embodiment are as shown in FIG.

[0051]

(Equation 25)

FIG. 5 shows a differential amplifier circuit according to a third embodiment of the present invention. The circuit of the third embodiment corresponds to the second embodiment.
In this embodiment, the method of forming the differential output pair is changed in the circuit of the embodiment. That is, the differential output pair is (M1, M2) (M
3, M4) (M5, M6), the other transistor M6 of one transistor pair (M5, M6) and the remaining transistor pair (M1, M6)
M2) One of the transistors (M1 and M4) of (M3, M4)
3) and one transistor pair (M
5, M6) and the drains of the other transistors (M2, M4) of the remaining transistor pairs (M1, M2) (M3, M4) are connected in common.

The circuit operation is the same as that of the circuit of the second embodiment, and the transconductance characteristics are as shown in FIG.

FIG. 7 shows a differential amplifier circuit according to a fourth embodiment of the present invention. The circuit of the fourth embodiment includes four differential pairs, namely, a transistor pair of (M1, M2) and a differential pair including a constant current source 1 (value I ₀ ) for driving the transistor pair, and (M
3, M4) and a differential pair including a constant current source 2 (value a × I ₀ ) for driving the transistor pair, a (M5, M6) transistor pair and a constant current source 3 (value a ′
× a differential pair comprising a I _0), composed mainly of a differential pair comprising a (M7, M8) transistor pair and a constant current source for driving the four (the value a "× I _0). Note , (M1, M
2) 4 of (M3, M4) (M5, M6) (M7, M8)
The ratio of β between two transistor pairs is (M1, M
2): (M3, M4): (M5, M6): (M7, M
8) = 1: b: b ′: b ″.

[0055] In FIG 7, the differential input pair input voltage V _in is applied, among four transistor pairs each other,
The gates of one transistor (M1, M3, M5, and M7) and the other transistor (M2, M4, M6, and M7)
8) The gates are commonly connected to each other.

Further, the differential output pair is provided between (M1, M2) and (M5, M6) between the four transistor pairs.
One of the two transistor pairs (M1 and M
5) and drains of the other transistor pair (M4 and M8) of the two transistor pairs (M3, M4) (M7, M8) and the other of the two transistor pairs of (M1, M2) (M5, M6) The transistors (M2 and M6) and (M
3, M4) (M7, M8), the drains of one of the two transistor pairs (M3 and M7) are commonly connected.

In the above configuration, the difference current ΔI ₄ between the drain currents of the transistors M7 and M8 in the added differential pair is given by Equation 26, and the differential output current of the differential amplifier circuit is given by Equation 27. Equations 21 and 22,
Substituting the approximations of 23 and 26 and transconductance becomes a straight line, a, b, a ', b', a ",
The relational expression to be satisfied by b ″ is obtained as Expression 28. The transconductance characteristic of the circuit of the fourth embodiment is shown in FIG.
become that way.

[0058]

(Equation 26)

[0059]

[Equation 27]

[0060]

[Equation 28]

FIG. 9 shows a differential amplifier circuit according to a fifth embodiment of the present invention. The circuit of the fifth embodiment is similar to that of the fourth embodiment.
In this embodiment, the method of forming the differential output pair is changed in the circuit of the embodiment. That is, the differential output pair is (M1, M2) (M
3, M4) (M5, M6) (M7, M8), (M1, M2) (M7, M
8), one of the two transistor pairs (M
1 and M7) and (M3, M4) (M5, M6), the drains of the other transistor (M4 and M6) and the two transistors of (M1, M2) (M7, M8). The other transistor (M2 and M8)
And (M3, M4) and (M5, M6), the drains of one transistor (M3 and M5) of two transistor pairs are connected in common.

The circuit operation is the same as that of the circuit of the fourth embodiment, and the transconductance characteristic is as shown in FIG.

[0063]

As described above, according to the differential amplifier circuit of the present invention, two differential pairs (first invention) or three or more differential pairs (second invention) are connected to the FET pair. Since the input and output can be connected in a predetermined relationship and can be configured without a special additional circuit, it is possible to provide a differential amplifier circuit that can improve the transconductance linearity without increasing the circuit scale. is there.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a differential amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a transconductance characteristic of the circuit of the first embodiment.

FIG. 3 is a circuit diagram of a differential amplifier circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram of transconductance characteristics of the circuit of the second embodiment.

FIG. 5 is a circuit diagram of a differential amplifier circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a transconductance characteristic of the circuit according to the third embodiment.

FIG. 7 is a circuit diagram of a differential amplifier circuit according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing a transconductance characteristic of the circuit of the fourth embodiment.

FIG. 9 is a circuit diagram of a differential amplifier circuit according to a fifth embodiment of the present invention.

FIG. 10 is a diagram showing a transconductance characteristic of the circuit according to the fifth embodiment.

FIG. 11 is a circuit diagram of a conventional differential amplifier circuit.

FIG. 12 is a circuit diagram of a conventional differential amplifier circuit.

FIG. 13 is a circuit diagram of a conventional differential amplifier circuit.

[Explanation of symbols]

1 to 4 constant current source M1~M8 MOS transistor V _in input voltage

Claims (2)

(57) [Claims] A transconductance parameter and a drive
The dynamic current is composed of two differential pairs different from each other for each pair; the differential input pair is composed of the FET (M
OS transistor) The gates of one of the pair of FETs and the other of the pair of FETs in the other differential pair and the other of the pair of FETs in one differential pair and one of the pair of FETs in the other differential pair. The differential output pair is configured by commonly connecting the drains of one FET and the drain of the other FET of the FET pair in each differential pair. A differential amplifier circuit; 2. A transconductance parameter and a drive
N pairs (N ≧ 3) of differential pairs whose dynamic currents are different from each other in each pair ;
(MOS transistor) The gate of one of the pair of FETs and the gate of the other of the pair of FETs are connected in common; the differential output pair is composed of at least one of the other pair of FETs and one of the remaining pair of FETs. And a drain of one of the at least one pair of FETs and a drain of the other one of the remaining pairs of FETs are commonly connected to each other;