JPH05291850A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To provide the differential amplifier circuit capable of improving the linearity of a trans-conductance with a small circuit scale. CONSTITUTION:A ratio of current gains (beta) among three differential pair transistors(TRs) is (M1, M2):(M3, M4):(M5, M6)=1:b:b'. The differential input pair receiving an input voltage Vin is formed by connecting gates of the M1, M3, M5 and gates of the M2, M4, M6 in common respectively. Furthermore, the differential output pair is formed by connecting drains of the M1, M4, M6 and gates of the M2, M3, M5 in common respectively. The linearity of the trans-conductance is improved by setting properly parameters a, b, b'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit,
In particular, it relates to a differential amplifier circuit composed of MOS transistors.

[0002]

2. Description of the Related Art When a differential amplifier circuit is composed of MOS transistors, the linearity of transconductance becomes a problem. As a differential amplifier circuit with improved linearity,
Conventionally, for example, those shown in FIGS. 11, 12, and 13 are known. These are referred to because they are described in detail in the following documents.

FIG. 11: A. Nedungadi and TR Viswanathan
“Design of Linear CMOS Transco-nductance Element
s ”IEEE TRANSACTION ON CIRCUITS AND SYSTEMS, VOL, C
AS-31, NO.10, pp.891-894, OCTOBER 1984.

Figure 12: Zhenhua Wang and Walter Guggenbu
hl “A Voltage-Controllable Line-ar MOS Transconduc
tor Using Bias Offset Technique ”IEEE JOURNAL OF
SOL-ID-STATE CIRCUITS, VOL.25, NO.1, PP.315-317, FEBRU
ARY 1990.

FIG. 13: Francois Krummenacher and Norber
t Joehl “A 4-MHz CMOS Continuo-us-Time Filter wit
h On-Chip Automatic Tuning ”IEEE JOURNAL OF SOLID-
STA-TE CIRCUITS, V0L.23, NO.3 pp.750-758, JUNE 1988.

[0006]

However, the conventional differential amplifier circuit in which the linearity of the transconductance is improved has a problem that the circuit scale increases.

An object of the present invention is to provide a differential amplifier circuit having a novel structure which can improve the transconductance linearity without increasing the circuit scale.

[0008]

In order to achieve the above object, the differential amplifier circuit of the present invention has the following configuration. That is,
The differential amplifier circuit of the first invention is composed of two differential pairs;
The differential input pair is the FET (MOS
Transistor) pair of FETs and the other differential pair of FETs and the other FET of the pair of gates, and the other differential pair of FETs of the other pair of FETs and the other differential pair of FETs of the other pair of FETs And the gates of and are commonly connected to each other; and the differential output pair is configured by commonly connecting the drains of one FET of the FET pair and the drains of the other FET of each differential pair; It is characterized by that.

The differential amplifier circuit of the second invention is composed of N (N ≧ 3) differential pairs; one differential input pair is one of FET (MOS transistor) pairs in each differential pair. The gates of the FETs and the gates of the other FETs are commonly connected to each other; and the differential output pair includes drains of the other FET of at least one FET pair and one FET of the remaining FET pair, and One FET of at least one FET pair and the other FE of the remaining FET pair
The drains of T and T are commonly connected to each other; respectively.

[0010]

Next, the operation of the differential amplifier circuit of the present invention constructed as above will be described. In the present invention, two sets of differential pairs (first invention) or three or more sets of differential pairs (second invention) are used.
Input and output between the ET pairs are connected in a predetermined relationship. Therefore, since it can be configured without requiring a special additional circuit, it is possible to provide a differential amplifier circuit capable of improving the linearity of transconductance without increasing the circuit scale.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a differential amplifier circuit according to the first embodiment of the present invention. This differential amplifier circuit has two differential pairs, namely
A differential pair including a transistor pair (M1, M2) and a constant current source 1 (value I ₀ ) for driving the transistor pair, and a transistor pair (M3, M4) and a constant current source 2 (value a × for driving the transistor pair).
And a differential pair including I ₀ ).

Here, the transconductance parameter β of the transistor can be expressed as Formula 1 using the mobility μ, the gate oxide film capacitance C _OX per unit area, the gate width W, and the gate length L, but the transistor pair (M1, M
If it is 1 in 2), the transistor pair (M3, M
In 4), it is b times. The constants a and b do not become 1 at the same time, but a ≦ 1 and b ≦ 1.

[0013]

[Equation 1] β = μC _OX (W / L) (1/2)

The differential input pair to which the voltage V _in is applied is such that, between two transistor pairs, the gates of one transistor M1 and the other transistor M4 and the gates of the other transistor M2 and one transistor M3 are connected. Are commonly connected. Further, the differential output pair is configured by commonly connecting the drains of the transistors M1 and M3 on one side and the drains of the transistors M2 and M4 on the other side between the two transistor pairs.

In the above configuration, assuming that the device operates in the saturation region, the drain current I _{d1 of} M1 is given by the following equation (2), M2
Drain current I _d2 of Equation 3 is the drain current I _{d3 of} M3
Is given by Equation 4, and the drain current I _{d4 of} M4 is given by Equation 5.

[0016]

## EQU2 ## I _d1 = β (V _GS1 −V _T ) ²

[0017]

## _EQU00003 ## I _d2 = β (V _GS2- V _T ) ²

[0018]

(4) I _d3 = bβ (V _GS3 −V _T ) ²

[0019]

## EQU5 ## I _d4 = bβ (V _GS4- V _T ) ²

Here, V _T is a threshold voltage, V _T
GSi is the gate-source voltage.

The value I ₀ of the constant current source 1 is the equation 6, the value aI ₀ of the constant current source 2 is the equation 7, and the input voltage V _in is the gate-source voltage difference between the transistors of each differential pair. Equation 8 is equal to

[0022]

[Equation 6] I ₀ = I _d1 + I _d2

[0023]

[Formula 7] aI ₀ = I _d3 + I _d4

[0024]

[ _Equation 8] V _in = V _GS1 −V _GS2 = V _GS4 −V _GS3

From Equations 1 to 8, the difference current ΔI ₁ between the drain currents of the transistors M1 and M2 is given by Equation 9,
Difference current ΔI between drain currents of the transistors M3 and M4
₂ becomes Equation 10. In Equation 10, β ′ is Equation 11, and I ₀ ′ is Equation 12.

[0026]

[Equation 9]

[0027]

[Equation 10]

[0028]

## EQU11 ## β '= bβ

[0029]

## EQU12 ## I ₀ ′ = aI ₀

Therefore, the differential current ΔI of the differential output current of the differential amplifier circuit is given by the equation 13, and the conductance of the differential amplifier circuit is obtained by differentiating the equation 11 by the input voltage V _in ( Equation 14).

[0031]

Equation 13 ΔI = ΔI ₁ + ΔI ₂

[0032]

[Equation 14]

Here, the input voltage range in which the differential coefficients of ΔI ₁ and ΔI ₂ do not become 0 is Equation 15 or Equation 16, and in the input voltage range shown in Equation 15, ΔI ₁ is Equation 17
In the input voltage range shown in Equation 16, Δ
Since I ₂ can be approximated by Formula 18, Formula 14 is Formula 19
Can be approximated by

[0034]

[Equation 15] | V _in | ≦ I ₀ / β

[0035]

[Equation 16] | V _in | ≦ I ₀ ′ / β ′

[0036]

[Equation 17]

[0037]

[Equation 18]

[0038]

[Formula 19]

In order for Equation 19 to be a straight line, the term V _in ² needs to be 0. Therefore, the relationship between a and b set in Equations 11 and 12 should satisfy Equation 20. Become.

[0040]

[Expression 20] b√b = √a

Therefore, the I
₀ ', beta' be selected ratios of, possible transconductance linearity in approximation. FIG. 2 shows transconductances when various values of a and b are changed. From FIG. 2, it is understood that if the transconductance is allowed up to about ± 6% with respect to the value of V _in = 0, about 0.9 can be used for the operating input voltage range where the transconductance is not zero.

Next, FIG. 3 shows a differential amplifier circuit according to the second embodiment of the present invention. The circuit of the second embodiment includes three differential pairs, that is, a differential pair including a transistor pair of (M1, M2) and a constant current source 1 (value I ₀ ) for driving the transistor pair, and
3, a pair of transistors M4) and a constant current source 2 (value a × I ₀ ) for driving the transistor pair, and a pair of transistors (M5, M6) and a constant current source 3 (value a) for driving the transistor pair. ′
X I ₀ ) and a differential pair. In addition,
Conductance parameter β between three transistor pairs of (M1, M2) (M3, M4) (M5, M6)
The ratio of (M1, M2): (M3, M4): (M5, M
6) = 1: b: b '.

In FIG. 3, the differential input pair to which the input voltage V _in is applied is defined as follows:
The gates of one transistor (M1, M3, and M5) and the gates of the other transistor (M2, M4, and M6) are commonly connected to each other.

Further, the differential output pair includes one transistor pair (M1, M1) between the three transistor pairs.
2) One transistor M1 and the other transistor (M3, M4) (M5, M6) of the remaining transistor pair (M3, M4)
4 and M6) and one transistor pair (M1, M2) and the other transistor M2 and the remaining transistor pair (M3, M4) (M5, M6) one transistor (M3 and M5) drains Are commonly connected.

In the above structure, the difference current ΔI ₁ of the drain currents of the transistor pair (M1, M2) is calculated by the equation 21 and the transistor pair (M3, M) by the same procedure as described above.
The difference current ΔI ₂ of the drain current of 4) is the formula 22 and the difference current ΔI ₃ of the drain current of the transistor pair (M5, M6).
Is expressed by Expression 23, the differential output current ΔI is calculated by Expression 24.

[0046]

[Equation 21]

[0047]

[Equation 22]

[0048]

[Equation 23]

[0049]

[Equation 24]

In order to make the transconductance a straight line in the equation 24, the coefficient of the term of the cube of V _in is set to 0, and the relationship of a, b, a ', b'is obtained. Thus, the transconductance characteristic of the second embodiment circuit is as shown in FIG.

[0051]

[Equation 25]

Next, FIG. 5 shows a differential amplifier circuit according to the third embodiment of the present invention. This third embodiment circuit is the same as the second embodiment.
This is a modification of the method of forming the differential output pair in the embodiment circuit. That is, the differential output pair is (M1, M2) (M
3, M4) (M5, M6) among the three transistor pairs, the other transistor M6 of the one transistor pair (M5, M6) and the remaining transistor pair (M1,
M2) (M3, M4) one of the transistors (M1 and M4)
3) drains and one transistor pair (M
5, M6) and the other transistor (M2, M4) of the remaining transistor pair (M1, M2) (M3, M4) are commonly connected to each other.

The circuit operation is similar to that of the second embodiment circuit, and its transconductance characteristic is as shown in FIG.

Next, FIG. 7 shows a differential amplifier circuit according to the fourth embodiment of the present invention. The circuit according to the fourth embodiment includes four differential pairs, that is, a differential pair including a transistor pair of (M1, M2) and a constant current source 1 (value I ₀ ) for driving the transistor pair, and (M
3, a pair of transistors M4) and a constant current source 2 (value a × I ₀ ) for driving the transistor pair, and a pair of transistors (M5, M6) and a constant current source 3 (value a) for driving the transistor pair. ′
X I ₀ ), and a differential pair including a (M7, M8) transistor pair and a constant current source 4 (value a ″ × I ₀ ) for driving the transistor pair. , (M1, M
2) 4 of (M3, M4) (M5, M6) (M7, M8)
The ratio of β between two transistor pairs is (M1, M
2): (M3, M4): (M5, M6): (M7, M
8) = 1: b: b ′: b ″.

In FIG. 7, the differential input pair to which the input voltage V _in is applied has four transistor pairs, and
The gates of one transistor (M1, M3, M5, and M7) and the other transistor (M2, M4, M6, and M)
8) The gates are commonly connected to each other.

In addition, the differential output pair has two (M1, M2) (M5, M6) between four transistor pairs.
One transistor of one transistor pair (M1 and M
5) and (M3, M4) (M7, M8), the drains of the other transistor (M4 and M8) of the two transistor pairs and the other of the two transistor pairs of (M1, M2) (M5, M6). Transistors (M2 and M6) and (M
3, M4) (M7, M8) and one of the transistors (M3 and M7) of the two transistor pairs are commonly connected to each other.

In the above configuration, the difference current ΔI ₄ of the drain currents of the transistors M7 and M8 in the added differential pair is given by the equation 26, and the differential output current of the differential amplifier circuit is given by the equation 27. Equations 21 and 22,
By substituting the approximate expressions of 23 and 26 and the transconductance becomes a straight line, a, b, a ′, b ′, a ″,
The relational expression that b ″ must satisfy is given by Expression 28. The transconductance characteristic of the circuit of the fourth embodiment is shown in FIG.
become that way.

[0058]

[Equation 26]

[0059]

[Equation 27]

[0060]

[Equation 28]

Next, FIG. 9 shows a differential amplifier circuit according to the fifth embodiment of the present invention. This fifth embodiment circuit is the same as the fourth embodiment.
This is a modification of the method of forming the differential output pair in the embodiment circuit. That is, the differential output pair is (M1, M2) (M
3, M4) (M5, M6) (M7, M8) between four transistor pairs (M1, M2) (M7, M
8) one of the two transistor pairs (M)
1 and M7) and (M3, M4) (M5, M6) of the two transistor pairs of the other transistor (M4 and M6) and (M1, M2) (M7, M8) of the two transistor pairs. The other transistor (M2 and M8)
And (M3, M4) (M5, M6), the drains of one of the transistors (M3 and M5) of the two transistor pairs are commonly connected.

The circuit operation is similar to that of the fourth embodiment circuit, and its transconductance characteristic is as shown in FIG.

[0063]

As described above, according to the differential amplifier circuit of the present invention, two pairs of differential pairs (first invention) or three or more pairs of differential pairs (second invention) are used as FET pairs. Since the input and output of each other are connected in a predetermined relationship and can be configured without any special additional circuit, it is possible to provide a differential amplifier circuit that can improve the linearity of transconductance without increasing the circuit scale. is there.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a differential amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a transconductance characteristic diagram of the first embodiment circuit.

FIG. 3 is a circuit diagram of a differential amplifier circuit according to a second embodiment of the present invention.

FIG. 4 is a transconductance characteristic diagram of the second embodiment circuit.

FIG. 5 is a circuit diagram of a differential amplifier circuit according to a third embodiment of the present invention.

FIG. 6 is a transconductance characteristic diagram of the circuit of the third embodiment.

FIG. 7 is a circuit diagram of a differential amplifier circuit according to a fourth embodiment of the present invention.

FIG. 8 is a transconductance characteristic diagram of the fourth embodiment circuit.

FIG. 9 is a circuit diagram of a differential amplifier circuit according to a fifth embodiment of the present invention.

FIG. 10 is a transconductance characteristic diagram of the fifth embodiment circuit.

FIG. 11 is a circuit diagram of a conventional differential amplifier circuit.

FIG. 12 is a circuit diagram of a conventional differential amplifier circuit.

FIG. 13 is a circuit diagram of a conventional differential amplifier circuit.

[Explanation of symbols]

1 to 4 constant current source M1~M8 MOS transistor V _in input voltage

Claims (2)

[Claims] 1. A differential input pair is constituted by two differential pairs; a differential input pair is one FET of a FET (MOS transistor) pair in one differential pair and the other FET of a FET pair in the other differential pair. And the FE in the other differential pair and the other FET of the FET pair in the one differential pair
The gates of one of the FETs of the T pair are commonly connected to each other; the differential output pair is an FE in each differential pair.
A differential amplifier circuit, which is configured by connecting drains of one FET of the T pair and drains of the other FET in common. 2. Comprised of N (N ≧ 3) differential pairs;
The differential input pair includes the gates of one FET of the FET (MOS transistor) pair in each differential pair and the FE of the other FET.
The gates of T are commonly connected to each other; the differential output pair is the other FET of at least one FET pair
And drains of one of the remaining FET pairs and one of the FETs of the at least one FET pair and the other drains of the remaining FET pair of the pair of FETs are commonly connected, respectively. Differential amplifier circuit.