JP2808855B2 - Constant voltage circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant voltage circuit, and more particularly to a constant voltage circuit including an insulated gate field effect transistor.

[Conventional technology]

Conventionally, a constant voltage circuit of this type includes an operational amplifier 16, an enhancement type NMOS transistor 17, a depletion type PMOS transistor 18, a resistor, as shown in FIG.
19, 20 and a constant current source 21.
_DD is supplied.

In FIG. 3, assuming that the current flowing through the enhancement type NMOS transistor 17 is i ₁ and the current flowing through the depletion type NMOS transistor 18 is i ₂ , i ₁ and i ₂ are represented by the following equations, respectively.

In _{i 1 = K e (V out} -V TE) 2 i 2 = K d (0-V TD) 2 above _{equation, K e = (1/2) ·} μ e C 0e W e / L e K d = (1/2) · μ _e C _0e W _d / L _d V _TE : Threshold voltage of enhancement type NMOS transistor 17 V _TD : Threshold voltage of depletion type NMOS transistor 18 μ _e : Threshold voltage of enhancement type NMOS transistor 17 Mobility μ _d : Mobility of depletion type NMOS transistor 18 C _0e : Oxide film capacity of enhancement type NMOS transistor 17 C _0d : Oxide film capacity of depletion type NMOS transistor 18 W _e : Channel width W _d of enhancement type NMOS transistor 17 : Channel width L _{e of the} depletion type NMOS transistor 18: Channel length L _d of the enhancement type NMOS transistor 17: Channel length of the depletion type NMOS transistor 18.

Therefore, according to the above equation, when the gain of the operational amplifier 16 is sufficiently large, the output voltage V _out from the terminal 54 is given by the following equation.

In the above equation, setting _{R 20 K d = R 19 K} e, V out = V
_TD + _VTE , and since the threshold voltages _VTD and _VTE are insensitive to temperature, the temperature fluctuation of the output voltage _Vout is theoretically zero.

 The above is the outline of the operation of the conventional constant voltage circuit.

[Problems to be solved by the invention]

In the above-described conventional constant voltage circuit, as described with reference to FIG. 3, a depletion type NMOS transistor is required. However, the current production technology has a disadvantage that the number of steps must be considerably increased in order to manufacture a depletion type NMOS transistor by a CMOS process.

[Means for solving the problem]

In the constant voltage circuit according to the present invention, a first enhancement-type NMOS transistor having a drain connected to a first high potential and a gate connected to a predetermined voltage output terminal; A second enhancement-type NMOS transistor having a source connected to a low-potential second potential, a drain connected to the first potential, and a gate connected to the first potential.
An enhancement-type PMOS transistor connected to a divided potential between the first and second potentials, and a drain and a gate both connected to the source of the enhancement-type PMOS transistor, and a source connected to the second potential. And a differential amplifier circuit having a source of the first enhancement-type NMOS transistor and a source of the enhancement-type PMOS transistor as an output terminal, and a negative-phase input terminal connected to the first input terminal. Connected to the source of the enhancement-type NMOS transistor, the positive-phase input side terminal is connected to the source of the enhancement-type PMOS transistor,
And an operational amplifier having an output terminal connected to the voltage output terminal.

Further, in the constant voltage circuit according to the present invention, the drain is connected to a first high potential, and the gate is connected to a predetermined voltage output terminal. A second enhancement type NMOS transistor having a source connected to the source of the first NMOS transistor and a source connected to the drain of the fourth enhancement type NMOS transistor; a drain connected to the first potential; Enhancement type PM connected to a divided potential between the first potential and the drain of the fourth enhancement type NMOS transistor
An OS transistor, and both a drain and a gate are connected to a source of the enhancement type PMOS transistor;
A third enhancement type NM having a source connected to the drain of the fourth enhancement type NMOS transistor
An OS transistor; a differential amplifier circuit having a source of the first enhancement type NMOS transistor and a source of the enhancement type PMOS transistor as an output terminal; The positive-phase input terminal connected to the source of the NMOS transistor is connected to the first enhancement type.
An operational amplifier connected to the source of the PMOS transistor and having an output terminal connected to the voltage output terminal; and a gate connected to a predetermined constant voltage source and a source connected to a low-potential second power supply. And a fourth enhancement type NMOS transistor.

〔Example〕

Next, the present invention will be described with reference to the drawings. First
FIG. 2 is a circuit diagram of the first embodiment of the present invention. As shown in FIG. 1, the present embodiment includes an operational amplifier 1, enhancement-type NMOS transistors 2, 4, and 5, an enhancement-type PMOS transistor 3, and resistors 6 and 7.

In FIG. 1, the enhancement type NMOS transistors 4 and 5 together form a MOS resistor. If these resistance values are R ₄ and R ₅ respectively, the enhancement type NMOS transistor 2 and the enhancement type PMOS transistor The currents i ₁ and i ₂ flowing through 3 are represented by the following equations, respectively.

i ₁ = K _N (v _G1 −V _TN ) ² i ₂ = K _P (v _G2 −V _DD −V _TD ) ^{2 In the} above equation, K _N = (1/2) · μ ₁ C ₀₁ W ₁ / L ₁ K _P = (1/2) · μ ₂ C ₀₂ W ₂ / L ₂ v _G1 : The gate potential of the enhancement type NMOS transistor 2 v _G2 : The gate potential of the depletion type PMOS transistor 3 V _TN : The gate potential of the enhancement type NMOS transistor 2 Threshold voltage V _TP : threshold voltage of enhancement type PMOS transistor 3 μ ₁ : mobility of enhancement type NMOS transistor 2 μ ₂ : mobility of enhancement type PMOS transistor 3 C ₀₁ : oxide film of enhancement type NMOS transistor 2 capacity C _02: oxide film capacitance W ₁ of the enhancement type PMOS transistor 3: enhancement mode NMOS transistor 2 of the channel width W _2: the channel width of the enhancement-mode PMOS transistor 3 L _1: enhancement type NMOS transistor 2 of the channel length L _2: a channel length of the depletion type PMOS transistor 3.

Therefore, according to the above equation, when the gain of the operational amplifier 1 is sufficiently large, the output voltage V _out from the terminal 51 is given by the following equation.

Now, as in the conventional example described above, setting the _{R 5 K P = R 4 K} N, the output voltage V _out is expressed by the following equation.

In the above equation, the voltage value V _DD, the temperature coefficient of V _TP and V _TN is compared to the temperature coefficient of the resistance value is omitted it for a sufficiently small value, only for the resistance value R ₆ and R _7, its temperature If the coefficient is α, the output voltage V when the temperature is T
_out is given by the following equation.

That is, it is understood that the output voltage _Vout is kept constant regardless of the ambient temperature.

On the other hand, FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The configuration including the operational amplifier 8, the enhancement type NMOS transistors 9, 11, 12 and the enhancement type PMOS transistor 10 is shown in FIG. Is the same as that of the first embodiment described above, except that in this embodiment, an enhancement type NMOS transistor 13 is newly added to the first embodiment. It has a different configuration.

In FIG. 2, a newly added enhancement type NMOS transistor 13 has a voltage V _b input from a terminal 52.
Corresponding to the operation in the saturation region.
In this case, the drain current _ID of the enhancement type NMOS transistor 13 is expressed as _ID = K _N · (V _b −V _TN ), where V _TN is the threshold voltage of the enhancement type NMOS transistor 13. _Assuming that the voltage _Vb is kept constant, the current value of _ID is kept constant irrespective of the voltage between the drain and the source. Therefore, even if power supply noise or the like is mixed in, the current flowing through the enhancement type NMOS transistor 13 is kept constant at a fixed time, and output current fluctuation due to power supply noise or the like can be completely prevented.

〔The invention's effect〕

As described in detail above, the present invention can be configured with only an enhancement type MOS transistor without using a depletion type MOS transistor in a circuit configuration.
It is possible to eliminate the problem related to the manufacturing process in the CMOS process peculiar to the S transistor, and it is possible to reduce the total number of processes.

[Brief description of the drawings]

1 and 2 are circuit diagrams of first and second embodiments of the present invention, respectively, and FIG. 3 is a circuit diagram of a conventional example. In the figure, 1,8,16 ... operational amplifier, 2,4,5,9,11,12,1
3,17 …… Enhancement type NMOS transistor, 3,10 ……
Enhancement type PMOS transistors, 6, 7, 14, 15, 19, 2
0: resistor, 18: depletion type NMOS transistor, 21: constant current source.

Claims (2)

(57) [Claims] A first enhancement type NMOS transistor having a drain connected to a first high potential and a gate connected to a predetermined voltage output terminal; and both a drain and a gate being the first NMOS transistor. A second enhancement-type NMOS transistor having a source connected to a low potential second potential, a drain connected to the first potential, and a gate connected to the first and second potentials.
Enhancement type PM connected to the divided potential between two potentials
An OS transistor, and both a drain and a gate are connected to a source of the enhancement type PMOS transistor;
A third enhancement-mode NMOS transistor having a source connected to the second potential, and a differential amplifier having a source of the first enhancement-mode NMOS transistor and a source of the enhancement-mode PMOS transistor as output terminals The circuit and the negative-phase input terminal are the first enhancement type NMOS.
Connected to the source of the transistor, the positive-phase input terminal
An operational amplifier connected to the source of the enhancement type PMOS transistor and having an output terminal connected to the voltage output terminal. 2. A first enhancement type NMOS transistor having a drain connected to a first high potential and a gate connected to a predetermined voltage output terminal, and having both a drain and a gate connected to the first NMOS transistor. Of the second enhancement type, the source of which is connected to the drain of the fourth enhancement type NMOS transistor.
An NMOS transistor and an enhancement-type PMOS transistor having a drain connected to the first potential and a gate connected to a divided potential between the first potential and the drain of the fourth enhancement-type NMOS transistor;
Both the drain and the gate are the enhancement type PMOS.
A third enhancement NMOS transistor connected to the source of the transistor, the source of which is connected to the drain of the fourth enhancement NMOS transistor;
And the source of the first enhancement type NMOS transistor and the enhancement type PM transistor.
A differential amplifier circuit having a source of an OS transistor as an output terminal; and a negative-phase input terminal connected to the first enhancement type NMOS.
Connected to the source of the transistor, the positive-phase input terminal
An operational amplifier connected to the source of the first enhancement-type PMOS transistor and having an output terminal connected to the voltage output terminal; a second gate having a gate connected to a predetermined constant voltage source and a source having a low potential; The fourth enhancement type connected to a power supply
A constant voltage circuit, comprising: an NMOS transistor.