JP3080226B2 - Logarithmic amplification circuit with amplification and rectification circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logarithmic amplifier circuit, and more particularly, to a logarithmic amplifier circuit which can be suitably implemented on a semiconductor integrated circuit, has excellent temperature characteristics, and can easily change logarithmic characteristics.

[0002]

2. Description of the Related Art As an example of a conventional logarithmic amplifier circuit, there is a circuit disclosed in Japanese Patent Application Laid-Open No. 9-36686. In general, logarithmic amplification is realized by inputting input signals or output signals of a plurality of cascaded differential amplifier circuits to corresponding rectifier circuits, and adding each of the output signals of the rectifier circuits. In this conventional logarithmic amplifier circuit,
By using a triple tail cell instead of the differential amplifier circuit and rectifier circuit of each stage, the functions of the differential amplifier circuit and rectifier circuit are performed by one circuit cell.

FIG. 13 shows a triple tail cell constituting the above-mentioned conventional logarithmic amplifier circuit.

In FIG. 13, three n-channel field-effect transistors (Metal-Oxide-Se
miconductor Field-Effect Transistor, MOSFE
T) (hereinafter referred to as MOS transistors) M101, M
102 and M103 are constant current sources 101 (current value: I ₀ )
And form a triple tail cell.
The gates of the MOS transistors M101 and M102 form the input terminals of the triple tail cell, respectively. One terminal of the constant current source 101 is coupled to the sources of the MOS transistors M101, M102, M103, and the other terminal is grounded.

[0005] The drain of the MOS transistor M101 is connected to one terminal of a resistor 104 (resistance value: R).
The drain of the MOS transistor M102 is connected to the resistor 105
(Resistance value: R). The other terminals of the resistors 104 and 105 are connected to each other, and are further grounded via a constant voltage source 102 (voltage value: V _R ).

The drains of the MOS transistors M101 and M102 are connected to the power supply voltage line to which the power supply voltage V _DD is applied via load resistors 106 and 107 (resistance value: R _L ), respectively. MOS transistors M101 and M
The drains of 102 respectively constitute the amplification output terminals of the triple tail cell. MOS transistor M1
The drain of 03 constitutes the rectified output terminal of the triple tail cell.

The control voltage _Vb is applied to the gate of the MOS transistor M103 by the constant voltage source 103, and the current _ISQ flowing through the drain is taken out as a rectified output current. The amplified output voltage is taken out between the drains of the MOS transistors M101 and M102.

In the triple tail cell, M
When the current flowing through the drain of the OS transistors M101 and M102, respectively I _D101, I _D102, the differential output current ΔI (= I _D101 -I _D102) is substantially proportional to the input voltage V _i. When the differential output current ΔI is converted by the load resistors 106 and 107 connected to the drains of the MOS transistors M101 and M102, output voltages V _O1 and V _O2 are obtained at the drains. Differential output voltage ΔV (= V _O1
Since -V _O2) also approximately proportional to the input voltage V _i, the function of the differential amplifier circuit is obtained.

On the other hand, the current I _SQ flowing to the drain of the MOS transistor M103 has a double-wave rectification characteristic, and thus a function of a rectification circuit is obtained.

In the above-mentioned conventional logarithmic amplifier circuit, a plurality of triple tail cells shown in FIG. 12 are cascaded via a capacitor (capacitance value: C), and a current I output from each triple tail cell is connected. _SQ is added by an adder. The output of the adder has a logarithmic characteristic with respect to the input voltage V _i.

[0011]

In the conventional logarithmic amplifier circuit described above, in the triple tail cell of FIG. 12, output voltages V _O1 and V _{O2 serving as} amplified output signals are applied to load resistors 109 and 1 respectively.
10 has the following problems.

Generally, the output current of a circuit using a MOS transistor has a transconductance parameter β
Is proportional to Here, the transconductance parameter β is approximately proportional to the absolute temperature raised to the power of (−3/2), but it can be considered that it is linearly approximated at room temperature and inversely proportional to the absolute temperature. Therefore, even in an amplifier circuit using a MOS transistor, the output current depends on the temperature, and has a so-called temperature characteristic. The output current also depends on the temperature characteristics of the drive current and the temperature characteristics of the load resistance.

Therefore, in the conventional logarithmic amplifier circuit using the triple tail cell shown in FIG. 12, the voltage gain of the amplified output of the triple tail cell has a temperature dependency. The temperature dependence appears as the temperature dependence of the logarithmic characteristic. As a result, there is a problem that the temperature dependence of the logarithmic characteristic of the output signal cannot be reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logarithmic amplifier which can reduce the temperature dependence of the logarithmic characteristic of an output signal.

Another object of the present invention is to provide a logarithmic amplifier circuit capable of easily changing the logarithmic characteristic of an output signal.

[0016]

(1) A first logarithmic amplifier circuit according to the present invention includes first to n-th (n is an integer of 2 or more) cascade-connected amplifier / rectifier circuits. An initial input signal is input to an input terminal of the first stage amplifying / rectifying circuit, and an input terminal of the second to (n-1) th amplifying / rectifying circuit is connected to the first to the (n-1) th stage. The amplified output signals of the (n-2) -stage amplification / rectification circuits are input, respectively, and
From the amplification output terminals of the (n-1) th stage amplification / rectification circuit, the amplification output signals of the second stage to the (n-1) th stage amplification / rectification circuit are output, respectively, and the second stage -From the rectification output terminal of the (n-1) th stage amplification / rectification circuit,
The rectified output signals of the second to (n-1) th amplifying / rectifying circuits are output, respectively, and the input terminal of the n-th amplifying / rectifying circuit is connected to the (n-1) th amplifying / rectifying circuit. The amplified output signal of the rectifier circuit is input, and the n-th stage amplification is performed;
A rectification output terminal of the rectification circuit outputs a rectification output signal of the n-th stage amplification / rectification circuit, and the first to n-th rectification outputs of the first to n-th stage amplification / rectification circuits are added. In the logarithmic amplifier circuit configured to obtain an output signal obtained by logarithmically amplifying the initial input signal, each of the first to n-th amplifying / rectifying circuits includes first and second source-coupled amplifying / rectifying circuits. A MOS differential pair formed by two MOS transistors, and third and fourth Ms operating as loads of the first and second MOS transistors, respectively.
An OS transistor, a triple tail cell formed by source-coupled fifth, sixth and seventh MOS transistors and driven by a single tail current; and as a load for the fifth and sixth MOS transistors In addition to the eighth and ninth MOS transistors operating respectively, a first constant voltage is commonly applied to the gates of the third and fourth MOS transistors, and the fifth and sixth MOS transistors A differential voltage generated between the drains of the first and second MOS transistors is applied between the gates, and the eighth and ninth MO transistors are applied.
A second constant voltage is commonly applied to the gates of the S transistors, and the gates of the first and second MOS transistors forming the MOS differential pair form the input terminals of the corresponding amplifying / rectifying circuits. The drains of the fifth and sixth MOS transistors forming the triple tail cell form an amplification output terminal of a corresponding amplification and rectification circuit, and the seventh tail forming the triple tail cell.
The drains of the MOS transistors form a rectification output terminal of a corresponding amplifying / rectifying circuit.

(2) In the first logarithmic amplifier circuit of the present invention, each of the first to n-th amplifying / rectifying circuits includes a MOS transistor formed by source-coupled first and second MOS transistors. Differential pair and first and second MOs
A third and fourth MOS transistor respectively operating as a load of an S transistor, and a triple tail transistor formed by source-coupled fifth, sixth and seventh MOS transistors and driven by a single tail current.
It comprises a cell and eighth and ninth MOS transistors which operate as loads for the fifth and sixth MOS transistors, respectively. And the third and fourth
A first constant voltage is commonly applied to the gates of the MOS transistors, and a differential voltage generated between the drains of the first and second MOSFETs is applied between the gates of the fifth and sixth MOSFETs. , Eighth and Ninth MOs
The second constant voltage is commonly applied to the gates of the S transistors.

Furthermore, the gates of the first and second MOS transistors forming the MOS differential pair form the input terminals of the corresponding amplifying / rectifying circuits, and the fifth and sixth MOS transistors form the triple tail cell. The drain of the MOS transistor forms the amplification output terminal of the corresponding amplification and rectification circuit, and the drain of the seventh MOS transistor forming the triple tail cell forms the rectification output terminal of the corresponding amplification and rectification circuit. I have.

Therefore, in each of the first to n-th amplifying / rectifying circuits, when an input signal is applied to the input terminal of the amplifying / rectifying circuit, the first and n-th stages have first and second square characteristics with respect to the input signal. The drain currents of the second MOS transistors are equal to the third and fourth M
The square root (root) is compressed by the OS transistor and converted into a voltage. As a result, the differential output voltage between the drains of the first and second MOS transistors (that is, M
The differential output voltage of the OS differential pair is generated. The differential output voltage is linear with respect to the input signal, and its proportionality constant (ie, gain) is
It does not depend on the transconductance parameter of the OS transistor or the tail current value for driving the MOS differential pair.

Further, when the differential output voltage of the MOS differential pair is applied between the gates of the fifth and sixth MOS transistors, the drain currents of the fifth and sixth MOS transistors are reduced to the differential output voltage. On the other hand, it has a square characteristic. The drain currents are converted to voltages by the square root compression by the eighth and ninth MOS transistors operating as loads of the fifth and sixth MOS transistors.
As a result, a differential output voltage (ie, a differential output voltage of the triple tail cell) is generated between the drains of the fifth and sixth MOS transistors, and is output from the amplified output terminal as an amplified output signal. The amplified output signal is linear with respect to the input voltage of the triple tail cell, and at the same time, linear with respect to the input voltage of the MOS differential pair (that is, the input voltage of the amplifying / rectifying circuit). And the proportionality constant (ie, voltage gain) is
It does not depend on the transconductance parameter of the MOS transistor constituting the cell or the value of the tail current driving the triple tail cell.

On the other hand, the drain current of the seventh MOS transistor has a square characteristic with respect to the input voltage of the triple tail cell, and the drain current is output as a rectified output signal from the rectified output terminal.

As described above, the first to n-th cascade-connected
In the amplifying and rectifying circuits of the stages, the voltage gain of the amplified output signal does not depend on the value of the transconductance parameter or the tail current. Also, JP-A-9-36686
No load resistor is used as in the conventional circuit disclosed in Japanese Patent Application Laid-Open Publication No. H11-157,086. Therefore, the rectified output signals of the first to n-th amplifying / rectifying circuits are not affected by the temperature.
That is, in the first logarithmic amplifier circuit of the present invention, the temperature dependence of the logarithmic characteristic of the output signal is reduced.

(3) In a preferred example of the first logarithmic amplifier circuit of the present invention, a third constant voltage is applied to the gate of the seventh MOSFET in each of the first to n-th amplification / rectification circuits. You. In this case, the rectified output current of each amplifying / rectifying circuit has an ideal square characteristic.

(4) In another preferred example of the logarithmic amplifier circuit according to the present invention, in each of the first to n-th amplifying / rectifying circuits, a third gate is connected to the gate of the seventh MOSFET.
A constant voltage is applied, and the first to n-th amplification /
The voltage value of the third constant voltage can be changed in at least one of the rectifier circuits, and the logarithmic characteristic of the output signal can be adjusted by changing the voltage value of the third constant voltage. In this case, the logarithmic characteristic of the output signal of the logarithmic amplifier circuit can be easily changed.

(5) The second logarithmic amplifier circuit of the present invention comprises:
A first stage to an n-th stage (n is an integer of 2 or more) cascaded amplifier / rectifier circuits; an input terminal of the first stage amplifier / rectifier circuit is supplied with an initial input signal; Input terminals of the first to (n-2) th amplifying / rectifying circuits are input to input terminals of the second to (n-1) th amplifying / rectifying circuits, respectively. From the amplification output terminals of the amplification / rectification circuits of the (n-1) th stage, the amplification output signals of the amplification / rectification circuits of the second to (n-1) th stages are respectively output. 2nd stage to (n-1) th stage amplification
From the rectification output terminals of the rectifier circuit, the second stage to the (n
-1) A rectified output signal of the amplifying / rectifying circuit of the stage is output, and an input terminal of the amplifying / rectifying circuit of the n-th stage is
An amplified output signal of the (n-1) stage amplifying / rectifying circuit is input, and a rectified output signal of the n-th stage amplifying / rectifying circuit is supplied from a rectified output terminal of the n-th stage amplifying / rectifying circuit. Is output, and the first to n-th rectified outputs of the first to n-th amplification / rectification circuits are added to obtain an output signal obtained by log-amplifying the initial input signal. In the circuit, each of the first to n-th amplifying / rectifying circuits includes first and second source-coupled MOS transistors.
A MOS differential pair formed by transistors, third and fourth MOS transistors respectively operating as loads of the first and second MOS transistors, and fifth, sixth, seventh and seventh sources coupled to each other. A fourth tail cell formed by eight MOS transistors and driven by a single tail current; and a ninth cell operating as a load of the fifth and sixth MOS transistors, respectively.
And a tenth MOS transistor, and a first constant voltage is commonly applied to the gates of the third and fourth MOS transistors.
Between the gates of the first and second MOS transistors.
A differential voltage generated between the drains of the MOS transistors is applied, and a second constant voltage is commonly applied to the gates of the ninth and tenth MOS transistors.
The gates of the first and second MOS transistors forming an OS differential pair form the input terminals of a corresponding amplifying / rectifying circuit, and the fifth and sixth MOS transistors form the quadritail cell. Form the amplification output terminal of the corresponding amplification and rectification circuit,
The drains of the seventh and eighth MOS transistors forming the quadri-tail cell are commonly connected to form a rectification output terminal of a corresponding amplifying / rectifying circuit.

(6) The second logarithmic amplifier circuit of the present invention comprises:
In the first logarithmic amplifier circuit according to the present invention, this corresponds to a circuit in which a triple tail cell is replaced with a quadrature cell.

The one in which the drains of the seventh and eighth MOS transistors forming the quadri-tail cell are connected in common performs an operation equivalent to that of the triple-tail cell, and is described in the first logarithmic amplifier circuit of the present invention. For the same reason, the temperature of the rectified output signal is not affected by the temperature, so that the temperature dependence of the logarithmic characteristic is reduced.

(7) In a preferred example of the second logarithmic amplifier circuit according to the present invention, a third constant voltage is applied to the gate of the seventh MOSFET in each of the first to nth amplification / rectification circuits. You. In this case, the rectified output current of each amplifying / rectifying circuit has an ideal square characteristic.

(8) In another preferable example of the second logarithmic amplifier circuit of the present invention, in each of the first to n-th amplification / rectification circuits, a third constant voltage is applied to the gate of the seventh MOSFET. And the voltage value of the third constant voltage can be changed in at least one of the first to n-th amplifying / rectifying circuits, and by changing the voltage value of the third constant voltage. The logarithmic characteristic of the output signal can be adjusted. In this case, the logarithmic characteristic of the output signal of the logarithmic amplifier circuit can be easily changed.

(9) The third logarithmic amplifier circuit of the present invention comprises:
A first stage to an n-th stage (n is an integer of 2 or more) cascaded amplifier / rectifier circuits; an input terminal of the first stage amplifier / rectifier circuit is supplied with an initial input signal; Input terminals of the first to (n-2) th amplifying / rectifying circuits are input to input terminals of the second to (n-1) th amplifying / rectifying circuits, respectively. From the amplification output terminals of the amplification / rectification circuits of the (n-1) th stage, the amplification output signals of the amplification / rectification circuits of the second to (n-1) th stages are respectively output. 2nd stage to (n-1) th stage amplification
From the rectification output terminals of the rectifier circuit, the second stage to the (n
-1) A rectified output signal of the amplifying / rectifying circuit of the stage is output, and an input terminal of the amplifying / rectifying circuit of the n-th stage is
An amplified output signal of the (n-1) stage amplifying / rectifying circuit is input, and a rectified output signal of the n-th stage amplifying / rectifying circuit is supplied from a rectified output terminal of the n-th stage amplifying / rectifying circuit. Is output, and the first to n-th rectified outputs of the first to n-th amplification / rectification circuits are added to obtain an output signal obtained by log-amplifying the initial input signal. In the circuit, the first stage amplifying / rectifying circuit includes a MOS differential pair formed by source-coupled first and second MOS transistors, and a first and second MO.
A third and fourth MOS transistor respectively operating as a load of an S transistor, and a first triple tail formed by source-coupled fifth, sixth and seventh MOS transistors and driven by a single tail current A cell and eighth and ninth MOS transistors respectively operating as loads of the fifth and sixth MOS transistors
A third transistor and a third transistor.
A first constant voltage is commonly applied to the gates of the MOS transistors, and a differential voltage generated between the drains of the first and second MOS transistors is applied between the gates of the fifth and sixth MOS transistors. Applied to the eighth
A second constant voltage is commonly applied to the gates of the first and second MOS transistors, and the gates of the first and second MOS transistors forming the MOS differential pair are connected to the first-stage amplification and rectification circuit. And the drains of the fifth and sixth MOS transistors forming the first triple tail cell form an amplified output terminal of the first stage amplifying / rectifying circuit; The drain of the seventh MOS transistor forming one triple tail cell forms a rectification output terminal of the first stage amplifying / rectifying circuit, and the second to n-th stage amplifying / rectifying circuits are provided. Are source-coupled tenth and eleventh
And a third triple-tail cell formed by the twelfth and twelfth MOS transistors and driven by a single tail current, and thirteenth and fourteenth MOs acting as loads on the tenth and eleventh MOS transistors, respectively.
A gate of the thirteenth and fourteenth MOS transistors, wherein a constant voltage is commonly applied to the gates of the thirteenth and fourteenth MOS transistors to form the second triple tail cell; Form the input terminals of the corresponding amplifying / rectifying circuits of the second to n-th stages, and the drains of the tenth and eleventh MOS transistors forming the second triple tail cell are connected to the The amplification output terminals of the corresponding amplification and rectification circuits of the second to n-th stages are formed, and the triple tail
The drain of the twelfth MOS transistor forming a cell forms a rectification output terminal of the corresponding amplification / rectification circuit of the second to n-th stages.

(10) The third logarithmic amplifier circuit of the present invention comprises a MOS differential pair of the second to n-th stage amplifying / rectifying circuits of the first logarithmic amplifier circuit of the present invention and M which operates as a load thereof.
This is equivalent to omitting the OS transistor.

The differential output voltage (ie, the amplified output signal of the amplifying / rectifying circuit) of the second triple tail cell constituting the second to n-th amplifying / rectifying circuits is input to the input signal (ie, the relevant amplified signal). The gain is substantially independent of the transconductance parameter of the MOS transistor forming the triple tail cell and the value of the tail current driving the triple tail cell.

On the other hand, the drain current of the twelfth MOS transistor forming the second triple tail cell has a square characteristic with respect to the input signal of the second triple tail cell (ie, the input signal of the corresponding amplifying / rectifying circuit). And the drain current is output from the rectification output terminal as a rectification output signal. The rectified output signal is proportional to the square of the input voltage of the amplifying / rectifying circuit.

For this reason, the gain of the output signal obtained by logarithmically amplifying the initial input signal does not depend on the value of the transconductance parameter or the tail current. Further, Japanese Patent Laid-Open No. 9-3
No load resistor is used unlike the conventional circuit disclosed in US Pat. No. 6,686. Therefore, since the rectified output signal is not affected by the temperature, the temperature dependency of the logarithmic characteristic of the output signal obtained by logarithmically amplifying the initial input signal is reduced.

(11) In a preferred example of the third logarithmic amplifier circuit of the present invention, a DC voltage is applied to the gates of the seventh and twelfth MOS transistors.

In this case, the rectified output current of each amplifying / rectifying circuit has a highly accurate square characteristic.

(12) In a further preferred example of the third logarithmic amplifier circuit of the present invention, a first DC voltage is applied to a gate of the seventh MOS transistor, and a second DC voltage is applied to a gate of the twelfth MOS transistor. , Each of the first and second DC voltages is varied to vary each of the rectified output signals.

In this case, since the drain currents of the seventh and twelfth MOS transistors change according to their gate voltages, each of the rectified output signals can be varied, and the logarithmic characteristic of the output signal of the logarithmic amplifier circuit can be obtained. Can be controlled.

(13) The fourth logarithmic amplifier according to the present invention comprises:
A first stage to an n-th stage (n is an integer of 2 or more) cascaded amplifier / rectifier circuits; an input terminal of the first stage amplifier / rectifier circuit is supplied with an initial input signal; Input terminals of the first to (n-2) th amplifying / rectifying circuits are input to input terminals of the second to (n-1) th amplifying / rectifying circuits, respectively. From the amplification output terminals of the amplification / rectification circuits of the (n-1) th stage, the amplification output signals of the amplification / rectification circuits of the second to (n-1) th stages are respectively output. 2nd stage to (n-1) th stage amplification
From the rectification output terminals of the rectifier circuit, the second stage to the (n
-1) A rectified output signal of the amplifying / rectifying circuit of the stage is output, and an input terminal of the amplifying / rectifying circuit of the n-th stage is
An amplified output signal of the (n-1) stage amplifying / rectifying circuit is input, and a rectified output signal of the n-th stage amplifying / rectifying circuit is supplied from a rectified output terminal of the n-th stage amplifying / rectifying circuit. Is output, and the first to n-th rectified outputs of the first to n-th amplification / rectification circuits are added to obtain an output signal obtained by log-amplifying the initial input signal. In the circuit, the first stage amplifying / rectifying circuit includes a MOS differential pair formed by source-coupled first and second MOS transistors, and a first and second MO.
A third and fourth MOS transistors each acting as a load of an S transistor, and a fifth, sixth, seventh and eighth MOS transistors source coupled and driven by a single tail current. One quadritail cell and ninth and tenth cells operating as loads of the fifth and sixth MOS transistors, respectively.
And a first constant voltage is commonly applied to the gates of the third and fourth MOS transistors, and the first and second MOS transistors are connected between the gates of the fifth and sixth MOS transistors. A differential voltage generated between the drains of the two MOS transistors is applied,
A second constant voltage is commonly applied to the gates of the ninth and tenth MOS transistors, and the gates of the first and second MOS transistors forming the MOS differential pair are connected to the gate of the first stage. The drains of the fifth and sixth MOS transistors forming the input terminal of the rectifier circuit and forming the first quadritail cell form the amplified output terminal of the first stage amplifier and rectifier circuit; The drains of the seventh and eighth MOS transistors forming the first quadrilateral cell are commonly connected to form a rectified output terminal of the first stage amplifying / rectifying circuit. Each of the n-th stage amplifying / rectifying circuits is formed by source-coupled eleventh, twelfth, thirteenth and fourteenth MOS transistors and is driven by a single tail current. A second quadritail cell, and fifteenth and sixteenth MOS transistors operating as loads of the eleventh and twelfth MOS transistors, respectively, and the gates of the fifteenth and sixteenth MOS transistors are A constant voltage is commonly applied to said first and second cells to form said second quadrilateral cell.
The gates of the first and twelfth MOS transistors form the input terminals of the corresponding amplifying / rectifying circuits of the second to n-th stages, and the eleventh and twelfth MOS transistors form the second quadritail cell. The drains of the MOS transistors form the amplification output terminals of the corresponding amplification / rectification circuits of the second to nth stages, and the drains of the thirteenth and fourteenth MOS transistors forming the first quadritail cell are Are connected in common to form rectification output terminals of the corresponding amplification and rectification circuits of the second to n-th stages.

(14) The fourth logarithmic amplifier circuit of the present invention corresponds to the third logarithmic amplifier circuit of the present invention in which the triple tail cell is replaced by a quadrature cell.

The common connection of the drains of the seventh and eighth MOS transistors or the common connection of the drains of the eleventh and twelfth MOS transistors forming the quadritail cell is equivalent to the operation of the triple tail cell. Therefore, the rectified output signal is not affected by the temperature for the same reason as described in the first logarithmic amplifier circuit of the present invention, so that the temperature dependence of the logarithmic characteristic is reduced.

(15) In a preferred example of the fourth logarithmic amplifier circuit of the present invention, in the first-stage amplification / rectification circuit, a fourth constant voltage is applied to the gate of the seventh MOSFET, and In each of the n-th stage amplifying / rectifying circuits, a fourth constant voltage is applied to the gate of the twelfth MOSFET. In this case, the rectified output current of each amplifying / rectifying circuit has a highly accurate square characteristic.

(16) In a further preferable example of the fourth logarithmic amplifier circuit of the present invention, in the first stage amplifying / rectifying circuit, a fourth constant voltage is applied to a gate of the seventh MOSFET, and In each of the second to n-th amplification / rectification circuits, a fifth constant voltage is applied to the gate of the twelfth MOSFET, and in the first-stage amplification / rectification circuit, the fourth constant voltage and the second At least one voltage value of the fifth constant voltage in the amplifying / rectifying circuit of the n-th stage can be changed, and by changing the voltage value of the fourth constant voltage or the fifth constant voltage, the logarithm of the output signal is obtained. Characteristics can be adjusted. In this case, the logarithmic characteristic of the output signal of the logarithmic amplifier circuit can be adjusted.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
1 shows a logarithmic amplifier circuit according to an embodiment.

This logarithmic amplifier circuit includes n cascade-connected amplifier / rectifier circuits, that is, first amplifier / rectifier circuits S1,
A second amplifying / rectifying circuit S2,..., An n-th amplifying / rectifying circuit Sn, and an adder for adding rectified outputs of the amplifying / rectifying circuits S1 to Sn to generate a logarithmic output. I have. Here, the addition is performed by connecting the rectification output wirings of the amplification and rectification circuits S1 to Sn. In other words, the rectification output wiring forms an adder.

Since the first to n-th amplifying / rectifying circuits S1 to Sn have the same configuration, the first amplifying / rectifying circuit S1 will be described in detail here.
Description of the rectifier circuits S2 to Sn will be omitted.

(Configuration of Amplifying / Rectifying Circuit S1) As shown in FIG. 1, the first amplifying / rectifying circuit S1 includes a MOS differential pair 4 formed by two source-coupled n-channel MOS transistors M1 and M2. And a triple-tail cell 5 formed by three n-channel MOS transistors M5, M6 and M7 source-coupled to each other.
l) and

The sources of the MOS transistors M1 and M2 forming the MOS differential pair 4 are a constant current source 1 (current value: I
_SS1 ) is grounded. This MOS differential pair is
It is driven by the constant current _ISS1 generated by the constant current source 1.

The ratio (W / L) of the gate width (W) to the gate length (L) of each of the MOS transistors M1 and M2 is K ₁ times that of the unit MOS transistor (K ₁ is a constant, but K ₁ is a constant). ₁ ≧ 1).

The gates of the MOS transistors M1, M2, the first and second input terminal pair of the first amplifier and rectifier circuits S1 to form the input voltage V _i of the logarithmic amplification circuit is applied between their gate You. That is, the first and second input terminal pairs operate as input terminal pairs of the logarithmic amplifier circuit.

The n-channel MOS transistor M3 is
It operates as a load of the OS transistor M1. The source of the MOS transistor M3 is connected to the drain of the MOS transistor M1, the drain is connected to a power supply voltage line to which the power supply voltage V _DD is applied, and the bias voltage (DC constant voltage) V _B is applied to the gate.

The n-channel MOS transistor M4 is
It operates as a load of the OS transistor M2. The source of the MOS transistor M4 is connected to the drain of the MOS transistor M2, the drain is connected to a power supply voltage line to which the power supply voltage V _DD is applied, and the gate is the same bias voltage V _B as applied to the MOS transistor M3. Is applied.

[0054] The ratio of the MOS transistor M3, the gate width of M4 (W) and gate length (L) (W / L) are both _twice that of K of unit MOS transistor (K ₂ is a constant, where K ₂ ≧ 1).

The sources of the n-channel MOS transistors M5, M6 and M7 forming the triple tail cell 5 are:
It is grounded via a constant current source 2 (current value: I ₀₁ ).
The triple tail cell 5 is driven by a constant current I ₀₁ generated by the constant current source 2, and the constant current I ₀₁ is a tail current.

The gates of the MOS transistors M5 and M6 are connected to the drains of the MOS transistors M1 and M2, respectively. The drains of the MOS transistors M5 and M6 are connected to the first amplifying / rectifying circuit S1 respectively.
And a second output terminal (amplified output terminal).

The gate of the MOS transistor M5 has a MOS differential pair 4 generated at the drain of the transistor M1.
The first output voltage V _O1 of is applied. The second output voltage V _O2 of the MOS differential pair generated at the drain of the transistor M2 is applied to the gate of the MOS transistor M6. The difference between these two output voltages V _O1 and V _O2 (ie,
MOS differential pair 4 differential output voltage)
The input voltage of the cell.

A control voltage (DC constant voltage) V _C1 is applied to the gate of the MOS transistor M7. The drain of the MOS transistor M7 is connected to the first amplifying / rectifying circuit S1.
Is formed as a third output terminal (rectified output terminal).

The ratio (W / L) of the gate width (W) to the gate length (L) of the MOS transistors M5 and M6 is equal to the unit MOS.
₁ times that of the K of the transistor. The ratio of the gate width (W) to the gate length (L) of the MOS transistor M7 (W /
L) is K ₃ times that of the unit MOS transistor (K ₃ is a constant, but K ₃ ≧ 1).

The n-channel MOS transistor M1 and the constant current source 3 (current value: I _SS1 / 2) form a control voltage generation circuit that generates a control voltage V _C1 applied to the gate of the triple tail cell 5. It is commonly applied DC constant voltage V _B to the gate of the MOS transistor M10. M
The drain of the OS transistor M10 is connected to the power supply voltage line, and the source is connected to one end of the constant current source 3.

The control voltage V _C1 is controlled by the MOS transistor M1
Equal to zero source voltage. In other words, the control voltage V
_C1 is generated at the source of the MOS transistor M10. The gate of the MOS transistor M7 of the first triple tail cell 5 is connected to the source of the MOS transistor M10.

(Configuration of Amplifying / Rectifying Circuits S2 to Sn) First
In the second amplifying / rectifying circuit S2 having substantially the same configuration as the amplifying / rectifying circuit S1, the gates of the MOS transistors M1 and M2 forming the MOS differential pair are connected to the input terminal pair of the second amplifying / rectifying circuit S2. To form The gate of the MOS transistor M11 is connected to the MOS of the first amplifying / rectifying circuit S1.
The generated third output voltage V _O3 is applied to the drain of the transistor M5. The fourth output voltage V _O4 generated at the drain of the MOS transistor M6 of the first amplifying / rectifying circuit S1 is applied to the gate of the MOS transistor M12. In other words, the differential output voltage (V _O3 −V _O3 ), which is the amplification output of the first amplification / rectification circuit S1, is input between the input terminals of the second amplification / rectification circuit S2.

The drains of the MOS transistors M5 and M6 of the second amplifying / rectifying circuit S2 are respectively connected to the second amplifying / rectifying circuit S2.
The first and second output terminals (amplification output terminals) of the rectifier circuit S2 are formed. Also, the MO of the second amplifying / rectifying circuit S2
The drain of the S transistor M17 forms a rectified output terminal of the second amplifying / rectifying circuit S2. This point is the third
The same applies to the nth amplifying / rectifying circuits S3 to Sn. However, only the n-th stage amplification / rectification circuit Sn does not output a signal from its amplification output terminal.

(Operating Principle of Amplifying / Rectifying Circuit S1)
The operation principle of the first amplifying / rectifying circuit S1 constituting the logarithmic amplifier circuit of the first embodiment shown in FIG. 1 will be described with reference to FIG.

Assuming that the relationship between the drain current I _D and the gate-source voltage V _GS of the MOS transistor operating in the saturation region obeys the square law, ignoring the body effect and channel length modulation, the drain current I _D Is the following equation (1
a) and (1b).

[0066]

(Equation 1)

In equations (1a) and (1b), K is
Gate width (W) and gate length (L) of MOS transistor
, The ratio (W / L) of the unit MOS transistor to that of the unit MOS transistor, β is a transconductance parameter, and V _TH is a threshold voltage.

Assuming that the effective mobility of carriers is μ and the capacitance of the gate oxide film per unit area is C _OX , the transconductance parameter β is defined as β = μ (C _OX / 2) (W / L).

The effective mobility μ of the carrier changes according to the following equation (2) according to the absolute temperature T.

[0070]

(Equation 2)

The transconductance parameter β is also
It changes according to the following equation (3) according to the absolute temperature T.

[0072]

(Equation 3)

Is obtained.

However, in the equations (3) and (4), the suffix 300 represents μ, β, T at 300 K (= 27 ° C.).
Shows the value of

FIG. 3 shows a temperature characteristic of the transconductance parameter β. From FIG. 3, the temperature characteristic of the transconductance β shown in Expression (3) can be understood.

(A) MOS differential pair FIG. 2 shows a first amplifier / rectifier circuit S1 of the logarithmic amplifier circuit. Note that, in FIG. 2, I _SS1 and I _SS1 shown in FIG.
₀₁ and V _C are respectively I _SS1 = I _SS , I ₀₁ = I ₀ and V _C1 = V _C.

Assuming that the matching between the elements is good, the MO
The two output currents of the S differential pair 4, that is, the drain currents I _D1 and I _D2 of the MOS transistors M1 and M2 are respectively expressed by the following equations (4a) and (4b).

[0078]

(Equation 4)

The drain currents I _D1 and I _D2 of the MOS transistors M1 and M2 represented by the equations (4a) and (4b) are the MOS transistors M3 and M4 serving as loads, respectively.
Are converted to voltages by the square root (root), and output voltages V _O1 and V _O2 are generated.

The output voltages V _O1 and V _O2 of the MOS differential pair 4 are
It is expressed as in the following equations (13a) and (13b).

[0081]

(Equation 5)

Therefore, the differential output voltage ΔV ₁ of the MOS differential pair 4 is expressed by the following equation (6).

[0083]

(Equation 6)

From the equation (6), it is understood that the differential output voltage ΔV of the MOS differential pair 4 is proportional to (I _D11 / 2−I _D21 / 2).

Here, a and b are constants, x is a variable,
Consider the following identity (6).

[0086]

(Equation 7)

Then, in the equation (6), a, b, x
Is set as follows.

[0088]

(Equation 8)

Then, the left side of the equation (7) is (I _D11
/ 2−I _D21 / 2) to which the above equations (4a) and (4b) are substituted. In this case, the right-hand side of the identity (5) is ^{_{(K 1 β) 1/2 · V}} i. Therefore, the following equation (8) holds.

[0090]

(Equation 9)

Therefore, the following expression (10) is established from the expressions (6) and (9).

[0092]

(Equation 10)

In the equation (10), the ratio K ₂ between the gate width (W) and the gate length (L) of the load MOS transistors M 3 and M 4 is determined by the gates of the MOS transistors M 1 and M 2 forming the MOS differential pair 4. if the ratio K ₁ is greater than the width (W) and gate length (L), this MOS differential pair becomes a reverse-phase attenuator, if K ₂ is equal or K ₁ is smaller than the K _1, the MOS differential The moving pair becomes an out-of-phase amplifier.

As is clear from equation (10), the MOS
Differential output voltage [Delta] V ₁ of the MOS differential pair to the load transistors M3, M4 is proportional to the input voltage V _i. In other words, a MOS having the MOS transistors M3 and M4 as loads
The differential pair operates as a linear attenuator or amplifier for the input voltage V _i . If (K ₂ / K ₁ ) is set to a small value, a high gain can be realized.

[0095] Further, in the proportional relationship between the input voltage V _i and the differential output voltage [Delta] V _1, the proportionality constant, i.e., the voltage gain becomes ^{_{(K 1 / K 2) 1/2}} . Therefore, the voltage gain does not include the tail current value I ₀ , the transconductance parameter β, or the load resistance value _RL . This means that the voltage gain has no temperature characteristics.

[0096] Here, when the differential output current of the MOS differential pair 4 and [Delta] I _D, [Delta] I _D by using the drain current I _D1, I _D2 is expressed by the following equation (11).

[0097]

[Equation 11]

Therefore, the differential output current Δ of MOS differential pair 4
_ID is a linear term

[0099]

(Equation 12)

And the nonlinear term

[0101]

(Equation 13)

It can be seen that the following is included.

[0103] When the MOS transistor M1, the voltage of the combined source of M2 forming the MOS differential pair 4 and the common source voltage V _S1, the common source voltage V _S1 is the following formula (1
It is expressed as 4).

[0104]

[Equation 14]

[0105] In Equation (14), V _CM1 is the common mode voltage of the input voltage V _i is the input differential.

As can be seen from equation (14), since the common source voltage V _S1 is a function of the input voltage V _i , the common source voltage V _S1 varies with the input voltage V _i . Further, the third term (square root term) of the equation (14) is equal to (1/2) ^1/2 of the second square root of the nonlinear term (13).
Therefore, the nonlinear term (13) of the differential output current [Delta] I _D of the MOS differential pair 4, it can be seen that due to variations of the common source voltage V _S1.

This corresponds to the common source voltage V of the MOS differential pair.
_{If S1} can be fixed to a constant voltage, it means that the MOS differential pair 4 can be operated linearly.

_Assuming that the common mode voltage of the output voltages V _O1 and V _O2 is V _CM2 , V _CM2 is represented by the following equation (15).

[0109]

(Equation 15)

From equation (15), it can be seen that the MOS transistor M
3, the output voltages V _O1 and V of the MOS differential pair with M4 as a load.
_O2 common mode voltage V _CM2 is equal to common source voltage V
It can be seen that _S1 (see the above equation (14)) is used.

FIG. 4 shows the MOS of the first amplifying / rectifying circuit S1.
The calculated value of the output voltage characteristic of the differential pair 4 is shown.

In FIG. 4, curves a1 and a2 indicate the output voltages V _O1 and V _O2 of the MOS differential pair 1, respectively, and a curve a3
Shows the common mode voltage V _CM2 of the input voltage V _i. Curve a
4 indicates a voltage [−V _O1 +2 (V _B −V _TH )], and a straight line a
5 shows the voltage _{[V O2 -V O1 + V B} -V TH]. Straight line a5
As is clear from FIG. 5, the differential output voltage Δ
V is proportional to the input voltage V _i .

FIG. 5 shows measured output voltage characteristics and differential output voltage characteristics of the MOS differential pair 1 when K ₂ = K ₁ = 1. The transistor array used here is an n-channel power MOS transistor array (model name: μPA
572T). The threshold voltage V _TH of this MOS transistor is about 1.5 V, and the value of the transconductance parameter β is also approximately two digits larger than the value of the transconductance parameter β of the MOS transistor of a CMOS process that is currently generally used. About big. Therefore, the power supply voltage and tail current must be increased to widen the input voltage range. In this measurement, the power supply voltage was set to 5.0 V (V _DD =
5.0 V), and tail current of 10.5 mA (I _SS = 10.
5 mA).

In FIG. 5, curves b1 and b2 show the two output voltages V _O1 and V _O2 of the MOS differential pair 1, respectively, and curves b3 and b4 show the differential output voltage ΔV ₁ ( = V _O1 -V _O2 ) and -ΔV ₁ (= V _O2 -V _O1 ). FIG. 5 shows that the differential output voltage ΔV ₁ of the MOS differential pair 1 having the MOS transistors M3 and M4 as loads is linear over a wide input voltage range.

(B) MOS Triple Tail Cell Next, MOS transistor M5, M6, M7
The operation of the OS triple tail cell 5 will be described.

The output current of the MOS triple tail cell 5 is disclosed in Japanese Patent Application Laid-Open Nos. 8-83314, 8-84037 and 8-315506 by the same inventor.

In the first amplifying / rectifying circuit S1 shown in FIG.
MOS forming input terminal pair of triple tail cell 5
The output voltages V _O1 ,
V _O2 is input. In other words, the differential output voltage ΔV of the MOS differential pair 4 is input between the gates of the MOS transistors M5 and M6. Therefore, the differential output current [Delta] I ₁ of the triple-tail cell 5, the MOS transistors M5, M6 of the drain current and I _D5, I _D6 respectively, are expressed as ΔI ₁ = I _D5 -I _D6.

Therefore, according to the method disclosed in Japanese Patent Application Laid-Open No. 8-83314, this triple tail
The differential output current ΔI ₁ of the cell 5 is represented by the following equation (16).

[0119]

(Equation 16)

Here, the differential output voltage Δ of the MOS differential pair 4 inputted between the gates of the MOS transistors M5 and M6
V ₁ is linear with respect to the input voltage V _i to the MOS differential pair 4 (that is, the first amplifying / rectifying circuit S 1), and V ₁ of the MOS transistors M 5 and M 6 forming the triple tail cell 5. Considering that the drain currents I _D5 and I _D6 each have a square characteristic with respect to the input voltage ΔV ₁ to the triple tail cell 5, the first amplifying / rectifying circuit S1 in FIG. 2 has a square characteristic. to output current, the differential output current [Delta] I ₁ of the triple-tail cell represented by formula (16) is linear to the input voltage [Delta] V _1, in other words, proportional to the input voltage [Delta] V ₁ It is necessary to.

That is, if c is a constant, it is necessary that ΔI ₁ = cΔV ₁ holds.

Therefore, ΔV ₁ of the numerator of the above formula (16)
Must be equal to the constant c. That is, the following equation (17) must be satisfied.

[0123]

[Equation 17]

At this time, the differential output current ΔI ₁ of the triple tail cell 5 is as follows.

[0125]

(Equation 18)

When the control voltage V _C at this time is obtained from Expression (17), the following Expression (19) is obtained.

[0127]

[Equation 19]

Therefore, the differential output current ΔI ₁ of the triple tail cell 5 represented by the above equation (16) becomes linear with respect to the input voltage ΔV ₁ , that is, the first amplifying / rectifying circuit of FIG. In order for S1 to output a current having a square characteristic, the control voltage V _C must be set so that Expression (19) holds. Then, the differential output current ΔI ₁ of the triple tail cell at that time is expressed by the above equation (18).

For example,

[0130]

(Equation 20)

At this time, the control voltage V _C needs to be set as follows.

[0132]

(Equation 21)

As described above, if the control voltage V _C to the MOS transistor M7 of the triple tail cell 5 is set so that the above equation (19) holds, the above equation (1)
6), the differential output current I ⁻ of this triple tail cell becomes linear with respect to the input voltage ΔV ₁ . Then, the differential output current ΔI ₁ is represented by the above equation (18).

In the first amplifying / rectifying circuit S1 shown in FIG. 2, since the MOS differential pair having the MOS transistors M3 and M4 as loads and the MOS triple tail cells are cascaded, the triple tail cells are not connected. M that forms
The gate voltages of the OS transistors M5, M6, and M7 are V _O1 , V _O2 , and (V _CM2 + V _C ), respectively. If M
Gate voltage of the OS transistor M7 (V _CM2 + V _C ) = V
If _G7 is a constant value, it can be very simplified gate bias circuit for generating a control voltage V _C. Therefore, next, the conditions necessary for that are obtained.

The common mode voltage V of the output voltages V _O1 and V _O2
CM2 is represented by the above equation (15), and since the control voltage V _C satisfies the above equation (19), the MOS transistor M7
Gate voltage V _G7 = (V _CM2 + V _C ) is _calculated by the following equation (2)
It is expressed as 2). Here, d is a constant.

[0136]

(Equation 22)

As described above, in order for the first amplifying / rectifying circuit S1 of FIG. 2 to output a current having a square characteristic, the differential output current ΔI ₁ of the triple tail cell 5 is reduced to its input voltage ΔV ₁ Since it is necessary to be proportional, the equation (2)
In 2), all coefficients of the term including the input voltage ΔV ₁ must be zero. That is, equation (22) must be simplified as in equation (23).

[0138]

(Equation 23)

The condition required to satisfy the equation (23) is the following relational equation (24a) in the equation (22):
(24b) is satisfied.

[0140]

(Equation 24)

Therefore, these relational expressions (24a) and (2
As 4b) is satisfied, when setting values such as the current value I _0, I _SS is established equation (23) is, the gate voltage V _G7 of a MOS transistor _{M7 = (V CM2 + V C} ) is constant Value. As a result, the bias circuit for generating the control voltage V _C for the MOS transistor M7 is greatly simplified as shown in FIG. And in that case,
Control voltage V _C is the formula in the circuit configuration of FIG. 2 (1
9), the differential output current ΔI ₁ of the triple tail cell 5 is expressed by the equation (18).
Becomes linear with respect to the input voltage ΔV ₁ .

[0142] Further, as already described in the above "(a) the MOS differential pair", the input voltage [Delta] V ₁ to MOS triple tape cell 5, MOS differential pair of MOS transistors M3, M4 and the load Differential output voltage ΔV ₁ ,
Proportional to the input voltage V _i of the to the first amplifier and rectifier circuit S1.

Thus, the first amplifying / rectifying circuit S1 shown in FIG.
Is to output an output current ΔI ₁ having a square characteristic with respect to the input voltage V _i as a differential output current of the MOS triple tail cell.

In this case, the triple tail cell formed by MOS transistors M5, M6 and M7 operates as an adaptive bias differential pair as disclosed in Japanese Patent Application Laid-Open No. 6-152275 by the same inventor. I do.

On the other hand, the triple tail cell 5 shown in FIG.
In, the drain currents I _D5 and I _D6 of the MOS transistors M5 and M6 are respectively compressed by square roots (roots) by the MOS transistors M8 and M9 serving as loads and converted into voltages, and output voltages V _O3 and V _O4 are generated. Is done. The differential output voltage of the input differential pair of the triple tail cell 5 is Δ
When V _2, as in the case of the MOS differential pair 4, [Delta] V ₂ is expressed by Equation (25).

[0146]

(Equation 25)

In the equation (25), the ratio K ₄ between the gate width (W) and the gate length (L) of the load MOS transistors M 8 and M 9 is equal to the gates of the MOS transistors M 5 and M 6 forming the triple tail cell 5. if the ratio K ₁ is greater than the width (W) and gate length (L), the triple-tail cell 5 becomes the attenuator opposite phase, if K ₄ equals K ₁ or K ₁ smaller, this triple Tail cell 5 is an amplifier of opposite phase.

Further, in the MOS differential pair 4, the expression (1)
0) is satisfied, the differential output voltage ΔV ₂ of the triple tail cell 5 is expressed by Expression (26).

[0149]

(Equation 26)

From the above equation (26), the triple tail
Input voltage V _i of the differential output voltage [Delta] V ₂ of the cell 5 MOS differential pair, i.e., the input voltage V _i of the first amplifier and rectifier circuits S1
It turns out that it is proportional to. A proportional relationship between the input voltage V _i and the differential output voltage [Delta] V _2, the proportionality constant (K ₁₂
/ K ₂ K ₄ ) ^1/2 corresponds to the voltage gain of the first amplifying / rectifying circuit S1. The voltage gain does not include the tail current value I ₀ , the transconductance parameter β, or the load resistance value _RL . This means that the voltage gain has no temperature characteristics.

(C) Operation Input Voltage Range Next, the operation input voltage range of the first amplifying / rectifying circuit S1 in FIG. 2 will be described.

MOS forming triple tail cell 5
The drain currents I _D5 and I _D6 of the transistors M5 and M6 are
The input voltage ΔV to this triple tail cell 5 respectively
Since it has a square characteristic with respect to ₁ , the drain currents I _D5 , I _D6 , I _{D7 of the} MOS transistors M5, M6, M7
Are given by the following equations (27a), (27b), (27
It is shown as c).

[0153]

[Equation 27]

Two MOS transistors M5 and M6 forming a differential pair of this MOS triple tail cell 5
Is expressed by the sum of the drain currents _ID5 and _ID6 . Therefore, the above equations (27a) and (27b)
The following equation (28) is obtained using

[0155]

[Equation 28]

As is apparent from equations (27c) and (28), the two output currents I _D7 and (I _D5 + I _D6 ) of the triple tail cell 5 are both proportional to the square of the input voltage ΔV ₁ , Therefore, the output currents I _D7 and (I _D5 + I
_D6) both have an ideal square characteristics for the input voltage [Delta] V _1.

Next, a condition is determined in which the linear input voltage range of the MOS triple tail cell 5 and the operating input voltage range of the MOS differential pair 4 are equal.

First, if none of the MOS transistors M5, M6, M7 forming the MOS triple tail cell 5 pinch off, the two output voltages V _O1 , V _O2 and the control voltage V _C of the MOS differential pair 4 become They are respectively represented by the following mathematical expressions (29a), (29b), and (29c).

[0159]

(Equation 29)

The expressions (29a) and (29b) are the same as the expressions (13a) and (13b).

When I _D1 = I _SS and I _D2 = 0, the above equation (2)
9a), (29b) and (29c) are as follows.

[0162]

[Equation 30]

[0163] When the formula (30a) is substituted into the equation (27a), the following equation (31) is obtained for I _D5.

[0164]

(Equation 31)

When the equation (31) is arranged, the following equation (3) is obtained.
It looks like 2).

[0166]

(Equation 32)

Similarly, equation (30b) is replaced by equation (27)
Substituting in b), the following equation (33) is obtained for I _D6.

[0168]

[Equation 33]

When the equation (33) is arranged, the following equation (3) is obtained.
It becomes like 4).

[0170]

(Equation 34)

By subtracting equation (32) from equation (34),
The following equation (35) is obtained.

[0172]

(Equation 35)

Equation (35) shows that the MOS triple tail
The maximum value of the differential input voltage ΔV ₁ to the cell 5 is shown.

On the other hand, the minimum value of the differential input voltage ΔV ₁ is I _D2
= I _SS , I _D1 = 0, and ΔV ₁ at that time is as follows.

[0175]

[Equation 36]

Therefore, it can be seen that the range of the differential input voltage ΔV ₁ is expressed as follows.

[0177]

(37)

Further, the equation (30c) is replaced by the equation (27).
Substituting in c), the following equation (38) is obtained for I _D7.

[0179]

(38)

This equation (38) is added to the above equation (34).
By substituting (35) and solving this, the following equation (39) is obtained.

[0181]

[Equation 39]

Therefore, the current values I, 2 and 3 of the constant current sources
_0, I _SS and, by setting the value of the ratio K ₂ thereto of unit MOS transistor of the ratio of the gate width to the gate length of the MOS transistor so as to satisfy the formula (39), the linear input of the MOS triple-tail cell 5 The voltage range becomes equal to the operation input voltage range of the MOS differential pair 4. As a result, FIG.
In the first amplifying / rectifying circuit S1, the ideal square characteristic (rectifying characteristic) is obtained over the entire operating input voltage range of the first amplifying / rectifying circuit S1.

Then, in this case, the MOS triple tail cell 5 of FIG. 2 operates as an adaptive bias differential pair having the maximum linear input voltage range.

The circuit configuration of the first amplifying / rectifying circuit S1 shown in FIG. 2 can be most simplified, for example, by K ₁ = K ₂ = 1, K ₃
= 2, I _SS = I _0/2 . At this time, the value of the constant c is

[0185]

(Equation 40)

Is obtained.

[0187] Equation (40) satisfies the above equation (19), respectively the control voltage V _C constant d at this time, the following equation (41a), so that the (41b).

[0188]

[Equation 41]

Therefore, the transistor having a load M
When OS differential pairs are cascaded, a linear amplifier is obtained, and K ₂ /
If K ₁ is set to be smaller than ₁ , high gain can be realized.

(Operation of Logarithmic Amplifier) As described above, FIG.
Of the first amplifying / rectifying circuit is linear and has a voltage gain of (K₁₂
/ K _TwoK_Four)^1/2Function and squaring characteristics as differential amplification circuit
It has a function as a rectifier circuit that outputs a current having I
Therefore, as shown in FIG.
By connecting the circuits S1 to Sn in cascade, the first to n-th
Rectification current I of the amplification and rectification circuits S1 to Sn₁~ I_nThe figure
It has the characteristics shown in FIG. These rectified currents I₁~ I
_nAre added via the connection line 9 and added to the output terminal 10.
Output current I_RSSI(= I₁+ I_Two+ ... + I_n)But
Is output.

FIG. 6 shows the rectified currents I ₁ , I ₂ ,.
_n and I _RSSI to indicate the relationship between the input voltage V _i. From Figure 6, it can be seen to have a pseudo logarithmic characteristic with respect to the output current I _RSSI input voltage V _i.

[0192] Each rectified output currents I _1, I _2, ···, have to have temperature dependency I _n, the output current I _RSSI be no temperature dependence.

[0193] Furthermore, the rectified output current I ₁ ~I _n corresponds to a change of the control voltage V _C1 ~V _Cn applied to the triple-tail cell of the amplifier and rectifier circuit S1~Sn first to n Change. That is, the control voltage V _C1 ~V _Cn the high rectified output current I ₁ ~I _n and set increases, the control voltage V _C1 ~V _Cn
Setting low as rectified output current I ₁ ~I _n decreases. In the logarithmic characteristic of the output current I _RSSI , the dynamic range of the logarithmic characteristic of each stage is determined by the voltage gain of each stage of the MOS triple tail cell connected in cascade, and the rectified currents of the preceding stage and the succeeding stage are superimposed. Part changes.

Therefore, by appropriately setting the control voltages V _{C1 to} V _Cn , the logarithmic characteristics such as the logarithmic accuracy and the slope of the logarithmic amplifier can be adjusted.

[0195] Incidentally, the rectified output current I ₁ of the triple-tail cell 5, as shown in equation (27c), since a square current, operation Thailand Na dynamic range in the case of dB displays the input voltage V _i is Since only about 6 to 8 dB can be secured, the product of the voltage gains of the MOS differential pair having the transistor as the load and the MOS triple tail cell having the transistor as the load is the total voltage gain per stage.

The specific value of (K ₂ K ₄ / K ₁₂ ) is, for example, about 4 to 6.

(Second Embodiment) FIG. 7 and FIG.
7 shows a logarithmic amplifier circuit according to a second embodiment of the present invention.

In the logarithmic amplifier circuit of the second embodiment, in each of the amplifying / rectifying circuits S1 to Sn, a quadritail cell is used instead of a triple tail cell.
1 has the same configuration as the logarithmic amplifier circuit of the first embodiment shown in FIGS. Therefore, the same components are denoted by the same reference numerals, and the description of the same components will be omitted.

As described above, the MOS transistor M7 forming the triple tail cell 5 of the first amplifying / rectifying circuit S1 shown in FIG. 2 has a ratio (W / L) of the gate width to the gate length.
Has twice the size of the unit MOS transistor (K ₃
= 2). Therefore, the MOS transistor M7 can be divided into two unit MOS transistors M7A and M7B in which all of the source, drain and gate are commonly connected. That is, it can be deformed like the quadretail cell 5A shown in FIG.

Since the quadretail cell 5A is equivalent to the triple tail cell 5, the operation of the logarithmic amplifier of the second embodiment is exactly the same as that of the first embodiment.

[0202] Thus, each of the rectified output current I ₁ ~I _n of the amplifier and rectifier circuit of the first to n are added via the connection line 9, the output current I _RSSI is output to the output terminal 10. This output current I _RSSI is equal to the input voltage V of the logarithmic amplifier circuit.
_It has a logarithmic characteristic for _i .

Each of the control currents V _C1 , V _{C2 ,.}
Can be changed to change the logarithmic characteristic of the output current I _RSSI .

FIG. 9 shows the characteristics of the drain currents I _D5 , I _D6 , I _D7A and I _D7B of the MOS transistors M5, M6, M7A, M7B constituting the quadritail cell 5A.

In FIG. 9, it can be seen from the curves A1, A2, and A3 that the drain currents I _D5 , I _D6 , I _D7A , and I _D7B all have square characteristics. It can also be seen from the curve A4 that the sum of the drain currents I _D7A and I _D7B also has a square characteristic. Furthermore, the drain current I
_It can also be seen from the curve A6 that the sum of _D5 and I _D7A has a linear characteristic, and that the sum of the drain currents I _D6 and I _D7B has a linear characteristic.

(Third Embodiment) FIG. 10 shows a logarithmic amplifier circuit according to a third embodiment of the present invention.

The logarithmic amplifier of the third embodiment has n amplifying / rectifying circuits S, like the logarithmic amplifier of the first embodiment.
1 to Sn are cascaded. The first amplifying / rectifying circuit S1 has exactly the same configuration as that of the first embodiment. Therefore, the same reference numerals are given to the same elements, and the description thereof will be omitted.

On the other hand, the second to n-th amplifying / rectifying circuits S2 to S2
Sn corresponds to the logarithmic amplifier circuit of the first embodiment in which the MOS differential pairs in the second to n-th amplifying / rectifying circuits S2 to Sn are omitted.

That is, the second amplifying / rectifying circuit S2 comprises:
It comprises a triple-tail cell 5 formed by three source-coupled n-channel MOS transistors M5, M6, M7.

The sources of the n-channel MOS transistors M15, M16 and M17 forming the triple tail cell 5 are grounded via a constant current source 12 (current value: I ₀₁ ). This triple tail cell 15 is a constant current source 1
2 driven by the constant current I ₀₁ generated by the
₀₁ is the tail current.

The gates of the MOS transistors M15 and M16 are connected to the drains of the drains of M5 and M6, respectively, and form the input terminal pair of the triple tail cell 15, that is, the input terminal pair of the second amplifying / rectifying circuit. I do. The drains of the MOS transistors M15 and M16 form the amplification output terminals of the second amplification and rectification circuit S2, respectively.

The output voltage of the first amplifying / rectifying circuit S1 is applied as an input voltage between the gates of the MOS transistors M15 and M16.

The control voltage (DC constant voltage) V _C2 is applied to the MOS transistor M17. The drain of the MOS transistor M17 forms a rectified output terminal of the first amplifying / rectifying circuit S2.

The ratio (W / L) of the gate width (W) to the gate length (L) of the MOS transistors M15 and M16 is expressed in units of M
It is K ₁ times that of the OS transistor (K ₁ is a constant, but K ₁ ≧ 1). The ratio (W / L) of the gate width (W) to the gate length (L) of the MOS transistor M17 is equal to the unit MOS.
It is K ₃ times that of the transistor (K ₃ is a constant, where K ₃ ≧ 1).

The n-channel MOS transistor M20 and the constant current source 13 (current value: I _SS1 / 2) form a control voltage generation circuit that generates a control voltage V _C2 applied to the triple tail cell 15. DC constant voltage V _B is applied to the gate of the MOS transistor M20. The drain of the MOS transistor M20 is connected to a power supply voltage line (power supply voltage V
_DD ), the source of which is connected to one end of the constant current source 13.

The control voltage V _C2 is controlled by the MOS transistor M2
Equal to zero source voltage. In other words, the control voltage V
_C2 is generated at the source of the MOS transistor M20. MOS transistor M of triple tail cell 15
The gate of 17 is connected to the source of the MOS transistor M20.

In the second amplifying / rectifying circuit S2, the triple tail cell 15 operates as a differential amplifying circuit that is substantially linear with respect to its input voltage, and the difference between the drains of the MOS transistors M15 and M16 is substantially proportional to the input voltage. A dynamic output voltage is generated.

Although the linearity of the differential amplifier circuit deteriorates with respect to the first amplifier / rectifier circuit S1 composed of the MOS differential pair 4 and the triple tail cell 5, the voltage gain is
(K ₁ / K ₄ ) ^1/2 . Also in this case, the voltage gain does not include the tail current value I ₀ , the transconductance parameter β, or the load resistance value _RL . This means that the voltage gain has no temperature characteristics.

On the other hand, a current proportional to the square of the input voltage of the triple tail cell 15 flows through the drain of the MOS transistor M17 constituting the triple tail cell 15. Then, the drain current of the MOS transistor M17 is output as the rectified output current I ₂ of the second amplifier-rectifier circuit.

Third to nth amplifying / rectifying circuits S3 to Sn
Has the same configuration as the second amplifying / rectifying circuit. Then, the rectified output currents I _{3 to In} are output from the _{third to n-} th amplifying / rectifying circuits S3 to Sn, similarly to the second amplifying / rectifying circuit.

[0220] These respective rectified output current I ₁ ~I _n of the amplifier and rectifier circuit of the first to n are added via the connection line 9, the output current I _RSSI is output to the output terminal 10. The output current I _RSSI has a logarithmic characteristic with respect to the input voltage V _i of the logarithmic amplification circuit.

The rectified currents I ₁ , I ₂ ,.
_{If n} does not have temperature dependency, the output current I _RSSI also has no temperature dependency.

[0222] In addition, each rectified current _{I 1, I 2, ···,} I n
Change in response to changes in the control voltages V _C1 , V _C2 ,... V _Cn applied to the triple tail cells of the first to n-th amplifying / rectifying circuits. Therefore, each control current V _C1 , V _C2 ,
... By setting V _Cn appropriately, the output current I _RSSI
Can be changed.

(Fourth Embodiment) FIG. 11 shows a logarithmic amplifier circuit according to a fourth embodiment of the present invention.

The logarithmic amplifier circuit of FIG. 11 is different from the logarithmic amplifier circuit of FIG. 12 in that quadruple cells are used in place of the triple tail cells of the amplifier / rectifier circuits S1 to Sn of the logarithmic amplifier circuit of the third embodiment. It has the same configuration as the logarithmic amplifier circuit of the third embodiment. Therefore, the same components are denoted by the same reference numerals, and the description of the same components will be omitted.

MOS transistor M7 forming triple tail cell 5 of first amplifying / rectifying circuit S1 in FIG.
Means that the ratio (W / L) of gate width to gate length is unit MOS
Since it has twice the size of a transistor (K ₃ = 2),
The MOS transistor M7 can be divided into two unit MOS transistors M7A and M7B in which all of the source, drain and gate are connected in common. That is, it can be deformed like the quadretail cell 5B.

The MOS transistor M1 forming the triple tail cell 15 of the second amplifying / rectifying circuit S2
7, the ratio (W / L) of the gate width to the gate length is expressed in units of MO.
Since it has twice the size of the S transistor (K ₃ = 2), the MOS transistor M7 is connected to the source, the drain,
It can be divided into two unit MOS transistors M17A and M17B all of whose gates are connected in common.
That is, it can be deformed like the quadretail cell 15A. The third to n-th amplifier / rectifier circuits have the same configuration as the second amplifier / rectifier circuit.

The quadretail cell 5A is equivalent to the triple tail cell 5 and the quadretail cell 15
Since A is equivalent to the triple tail cell 15, the operation of the logarithmic amplifier of the fourth embodiment is exactly the same as that of the third embodiment.

In the logarithmic amplification of the fourth embodiment, the first
Each of the rectified output current I ₁ ~I _n of the amplifier-rectifier circuit to n-th are added via the connection line 9, the output current I _RSSI is output to the output terminal 10. The output current I _RSSI has a logarithmic characteristic with respect to the input voltage V _i of the logarithmic amplification circuit.

The rectified currents I ₁ , I ₂ ,.
_{If n} does not have temperature dependency, the output current I _RSSI also has no temperature dependency.

[0230] In addition, each rectified current _{I 1, I 2, ···,} I n
Change in response to changes in the control voltages V _C1 , V _C2 ,... V _Cn applied to the triple tail cells of the first to n-th amplifying / rectifying circuits. Therefore, each control current V _C1 , V _C2 ,
... By setting V _Cn appropriately, the output current I _RSSI
Can be changed.

(Fifth Embodiment) FIG. 12 shows a logarithmic amplifier circuit according to a fifth embodiment of the present invention.

The logarithmic amplifier circuit of FIG. 12 is different from the second to n-th amplifier / rectifier circuits of the third embodiment in that the control voltages V _{C2 to} V _Cn are supplied by one control voltage generation circuit. In this case, there is an advantage that the configuration of the logarithmic amplifier circuit can be simplified.

[0233]

As described above, the logarithmic amplifier according to the present invention can reduce the temperature dependence of the logarithmic characteristic. Further, the logarithmic characteristic can be easily changed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a logarithmic amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a first amplifying / rectifying circuit included in the logarithmic amplifier circuit according to the first embodiment of the present invention.

FIG. 3 is a temperature characteristic of a transconductance parameter β.

FIG. 4 is a characteristic diagram showing calculated values of output voltage characteristics of a MOS differential pair included in the logarithmic amplifier circuit according to the first embodiment of the present invention.

FIG. 5 is a characteristic diagram showing actual measured values of output voltage characteristics and differential output voltage characteristics of a MOS differential pair included in the logarithmic amplifier circuit according to the first embodiment of the present invention (K ₂ = K ₁ = 1) ).

FIG. 6 is a diagram illustrating output current characteristics and rectified output current characteristics of the logarithmic amplifier circuit according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram of a logarithmic amplifier circuit according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram of a second amplifying / rectifying circuit constituting a logarithmic amplifier circuit according to a second embodiment of the present invention.

FIG. 9 is a characteristic diagram showing a drain current characteristic of a MOS transistor forming a quadritail cell in the logarithmic amplifier circuit according to the second embodiment of the present invention.

FIG. 10 is a circuit diagram of a logarithmic amplifier circuit according to a third embodiment of the present invention.

FIG. 11 is a circuit diagram of a logarithmic amplifier circuit according to a fourth embodiment of the present invention.

FIG. 12 is a circuit diagram of a logarithmic amplifier circuit according to a fifth embodiment of the present invention.

FIG. 13 shows a MOS triple tail cell in which a resistor constituting a conventional logarithmic amplifier circuit is loaded.

[Explanation of symbols]

M1, M2, M3, M4, M5, M6, M7 MOS transistors M8, M9, M10 MOS transistors M15, M16 MOS transistors M17, M18, M19, M20 MOS transistors M7A, M7B, M17A, M17B MOS transistors 1, 2, 3 , 12,13, constant current source 4 MOS differential pair 5,15 triple tail cell 5A, 15A quad tail cell

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03G 11/08 H03F 1/30 H03F 3/45

Claims (12)

(57) [Claims] 1. A cascade-connected first to n-th stages (where n is 2
The first stage amplification / rectification circuit, an input terminal of the first stage amplification / rectification circuit is supplied with an initial input signal, and the second to (n-1) th stage amplification / rectification circuits are provided. , Input terminals of the amplification / rectification circuits of the first to (n-2) th stages are respectively input to the input terminals of the second stage to (n-1) th stage. From the amplification output terminal,
The amplified output signals of the second to (n-1) th amplifying / rectifying circuits are output, respectively, and the second to (n-1) th amplifying / rectifying circuits are output.
From the rectification output terminals of the amplifying / rectifying circuits of the -1) stage, rectified output signals of the second to (n-1) th amplifying / rectifying circuits are respectively outputted, and the amplifying / rectifying of the n-th stage is performed. (N)
-1) The amplified output signal of the stage amplifying / rectifying circuit is input,
A rectified output terminal of the n-th stage amplifying / rectifying circuit outputs a rectified output signal of the n-th stage amplifying / rectifying circuit. In a logarithmic amplifier configured to obtain an output signal obtained by log-amplifying the initial input signal, the first to n-th amplifying and rectifying circuits each include: A MOS differential pair formed by source-coupled first and second MOSFETs, and the first and second MOSs;
A third and fourth MOSFET respectively operating as a load of a FET; a triple tail cell formed by source coupled fifth, sixth and seventh MOSFETs and driven by a single tail current; The eighth and the eighth operate as loads of the fifth and sixth MOSFETs, respectively.
And a ninth MOSFET, a first constant voltage is commonly applied to the gates of the third and fourth MOSFETs, and the first and second MOSFETs are interposed between the gates of the fifth and sixth MOSFETs. A differential voltage generated between the drains of the two MOSFETs is applied, and a second constant voltage is commonly applied to the gates of the eighth and ninth MOSFETs. And the second MO
The gates of the SFETs form the input terminals of the corresponding amplifying / rectifying circuits, and the drains of the fifth and sixth MOSFETs forming the triple tail cells form the amplifying output terminals of the corresponding amplifying / rectifying circuits. A logarithmic amplifier circuit, wherein the drain of the seventh MOSFET forming the triple tail cell forms a rectified output terminal of a corresponding amplifier / rectifier circuit. 2. The logarithmic amplifier circuit according to claim 1, wherein a third constant voltage is applied to a gate of said seventh MOSFET in each of said first to n-th amplifying / rectifying circuits. 3. In each of the first to n-th amplification / rectification circuits, a third constant voltage is applied to a gate of the seventh MOSFET, and the first to n-th amplification / rectification circuits are provided. 2. The logarithmic characteristic of the output signal according to claim 1, wherein the voltage value of the third constant voltage is changeable in at least one of the circuits, and the logarithmic characteristic of the output signal is adjustable by changing the voltage value of the third constant voltage. Logarithmic amplifier circuit. 4. The cascade-connected first to n-th stages (n is 2
The first stage amplification / rectification circuit, an input terminal of the first stage amplification / rectification circuit is supplied with an initial input signal, and the second to (n-1) th stage amplification / rectification circuits are provided. , Input terminals of the amplification / rectification circuits of the first to (n-2) th stages are respectively input to the input terminals of the second stage to (n-1) th stage. From the amplification output terminal,
The amplified output signals of the second to (n-1) th amplifying / rectifying circuits are output, respectively, and the second to (n-1) th amplifying / rectifying circuits are output.
From the rectification output terminals of the amplifying / rectifying circuits of the -1) stage, rectified output signals of the second to (n-1) th amplifying / rectifying circuits are respectively outputted, and the amplifying / rectifying of the n-th stage is performed. (N)
-1) The amplified output signal of the stage amplifying / rectifying circuit is input,
A rectified output terminal of the n-th stage amplifying / rectifying circuit outputs a rectified output signal of the n-th stage amplifying / rectifying circuit. In a logarithmic amplifier configured to obtain an output signal obtained by log-amplifying the initial input signal, the first to n-th amplifying and rectifying circuits each include: A MOS differential pair formed by source-coupled first and second MOSFETs, and the first and second MOSs;
A third and fourth MOSFET respectively operating as a FET load; a quad tail cell formed by source coupled fifth, sixth, seventh and eighth MOSFETs and driven by a single tail current; The fifth
And a ninth and a tenth MOSFET respectively operating as a load of the sixth MOSFET, and a first constant voltage is commonly applied to the gates of the third and fourth MOSFETs. 6th MO
The first and second MOSFETs between the gates of the SFETs;
A differential voltage generated between the drains of T is applied, a second constant voltage is commonly applied to the gates of the ninth and tenth MOSFETs, and the first and second MOSFETs forming the MOS differential pair are applied. MO of 2
The gates of the SFETs form the input terminals of the corresponding amplification and rectification circuits, and the drains of the fifth and sixth MOSFETs forming the quadritail cells form the amplification output terminals of the corresponding amplification and rectification circuits. And the seventh and eighth MOs forming the quadritail cell
The drains of the SFETs are connected in common and
A logarithmic amplifier circuit comprising a rectifier output terminal of the rectifier circuit. 5. The logarithmic amplifier circuit according to claim 4, wherein a third constant voltage is applied to a gate of said seventh MOSFET in each of said first to n-th amplifier / rectifier circuits. 6. In each of the first to n-th amplifying / rectifying circuits, a third constant voltage is applied to the gate of the seventh MOSFET, and the first to n-th amplifying / rectifying circuits are provided. 5. The logarithmic characteristic of the output signal according to claim 4, wherein the voltage value of the third constant voltage is changeable in at least one of the circuits, and the logarithmic characteristic of the output signal is adjustable by changing the voltage value of the third constant voltage. Logarithmic amplifier circuit. 7. The cascade-connected first to n-th stages (where n is 2
The first stage amplification / rectification circuit, an input terminal of the first stage amplification / rectification circuit is supplied with an initial input signal, and the second to (n-1) th stage amplification / rectification circuits are provided. , Input terminals of the amplification / rectification circuits of the first to (n-2) th stages are respectively input to the input terminals of the second stage to (n-1) th stage. From the amplification output terminal,
The amplified output signals of the second to (n-1) th amplifying / rectifying circuits are output, respectively, and the second to (n-1) th amplifying / rectifying circuits are output.
From the rectification output terminals of the amplifying / rectifying circuits of the -1) stage, rectified output signals of the second to (n-1) th amplifying / rectifying circuits are respectively outputted, and the amplifying / rectifying of the n-th stage is performed. (N)
-1) The amplified output signal of the stage amplifying / rectifying circuit is input,
A rectified output terminal of the n-th stage amplifying / rectifying circuit outputs a rectified output signal of the n-th stage amplifying / rectifying circuit. To the n-th rectified output are added to obtain an output signal obtained by logarithmically amplifying the initial input signal.
Differential pair formed by the first and second MOSFETs, third and fourth MOSFETs respectively operating as loads on the first and second MOSFETs, and fifth, sixth and seventh sources coupled to each other. A first triple tail cell formed by a single MOSFET and driven by a single tail current;
Eighth and ninth Ms acting as ET loads, respectively
An OSFET is included, a first constant voltage is commonly applied to the gates of the third and fourth MOSFETs, and the first and second MOSFETs are connected between the gates of the fifth and sixth MOSFETs. A differential voltage generated between the drains is applied, and the eighth and ninth MOSs are applied.
A second constant voltage is commonly applied to the gates of the FETs, and the first and second MOs forming the MOS differential pair are formed.
The gate of the SFET forms the input terminal of the first stage amplifying and rectifying circuit, and the drains of the fifth and sixth MOSFETs forming the first triple tail cell are the first stage amplifying and rectifying circuit. Forming the rectifier circuit amplification output terminal and forming the first triple tail cell;
The drain of the MOSFET forms the rectification output terminal of the first stage amplifying / rectifying circuit, and the second to n-th stages of the amplifying / rectifying circuits are respectively source-coupled tenth and Eleventh and twelfth MOSF
A second triple tail cell formed by ET and driven by a single tail current;
And a third constant voltage is commonly applied to the gates of the thirteenth and fourteenth MOSFETs, and the second triple tail cell And the gates of the tenth and eleventh MOSFETs form the input terminals of the corresponding amplifying and rectifying circuits of the second to nth stages, and form the second triple tail cells. 1
0 and the drains of the eleventh MOSFET are connected to the second
The first to nth stages forming corresponding amplification output terminals of corresponding amplification / rectification circuits and forming the triple tail cell;
A logarithmic amplifier circuit, wherein drains of two MOSFETs form rectification output terminals of the corresponding amplification / rectification circuits of the second to n-th stages. 8. In the first stage amplifying / rectifying circuit,
The fourth constant voltage is applied to a gate of the seventh MOSFET, and a fourth constant voltage is applied to a gate of the twelfth MOSFET in each of the second to n-th amplifying / rectifying circuits. Logarithmic amplifier circuit. 9. The first stage amplifying / rectifying circuit,
A fourth constant voltage is applied to the gate of the seventh MOSFET, and a fifth constant is applied to the gate of the twelfth MOSFET in each of the second to n-th amplification / rectification circuits.
When a constant voltage is applied to the first stage amplifying / rectifying circuit, the fourth constant voltage and the second to n-th stage amplifying / rectifying circuits are applied.
At least one of the fifth constant voltages in the rectifier circuit can be changed, and the fourth constant voltage or the fifth constant voltage can be changed.
8. The logarithmic amplifier according to claim 7, wherein a logarithmic characteristic of the output signal can be adjusted by changing a voltage value of the constant voltage. 10. A cascade-connected first to n-th (n is an integer of 2 or more) amplification / rectification circuits, and an input terminal of the first-stage amplification / rectification circuit receives an initial input signal. The amplified output signals of the first to (n-2) th stage amplifying / rectifying circuits are input to the input terminals of the second to (n-1) th stage amplifying / rectifying circuits, respectively. From the amplification output terminals of the second to (n-1) th amplification / rectification circuits,
The amplified output signals of the second to (n-1) th amplifying / rectifying circuits are output, respectively, and the second to (n-1) th amplifying / rectifying circuits are output.
From the rectification output terminals of the amplifying / rectifying circuits of the -1) stage, rectified output signals of the second to (n-1) th amplifying / rectifying circuits are respectively outputted, and the amplifying / rectifying of the n-th stage is performed. (N)
-1) The amplified output signal of the stage amplifying / rectifying circuit is input,
A rectified output terminal of the n-th stage amplifying / rectifying circuit outputs a rectified output signal of the n-th stage amplifying / rectifying circuit. To the n-th rectified output are added to obtain an output signal obtained by logarithmically amplifying the initial input signal.
Differential pair formed by the first and second MOSFETs, third and fourth MOSFETs respectively operating as loads of the first and second MOSFETs, and fifth, sixth, and seventh sources coupled to each other. And the eighth MOSF
A first quadritail cell formed by ET and driven by a single tail current;
A ninth and a tenth MOSFET respectively operating as a load of the OSFET, and a first constant voltage is commonly applied to gates of the third and fourth MOSFETs, and the fifth and sixth MOSFETs are A differential voltage generated between the drains of the first and second MOSFETs is applied between the gates of the ninth and tenth MOSFETs.
A second constant voltage is commonly applied to the gates of the MOSFETs, and the first and second MOs forming the MOS differential pair are formed.
The gate of the SFET forms the input terminal of the first stage amplifying / rectifying circuit, and the drains of the fifth and sixth MOSFETs forming the first quadritail cell are the drains of the first stage amplifying / rectifying circuit. A seventh rectifier circuit forming an amplification output terminal and the first quadritail cell;
And a drain of the eighth MOSFET is connected in common to form a rectified output terminal of the first stage amplifying / rectifying circuit. Each of the second to n-th stage amplifying / rectifying circuits has a source. A second quadritail cell formed by coupled eleventh, twelfth, thirteenth, and fourteenth MOSFETs and driven by a single tail current, and operates as a load on the eleventh and twelfth MOSFETs, respectively. The eleventh and twelfth MOSFETs including a fifteenth and a sixteenth MOSFET, wherein a constant voltage is commonly applied to the gates of the fifteenth and sixteenth MOSFETs, and the second and fourth quadritail cells are formed. Form the input terminals of the corresponding amplifying and rectifying circuits of the second to n-th stages, and form the second quadritail cells. Wherein for forming the first
The drains of the first and twelfth MOSFETs are connected to the second
The drains of the thirteenth and fourteenth MOSFETs forming the amplification output terminals of the corresponding amplification and rectification circuits of the first to n-th stages and forming the first quadritail cell are commonly connected to each other. A logarithmic amplifier circuit, wherein a rectification output terminal of a corresponding amplifying / rectifying circuit at the n-th stage is formed. 11. In the first stage amplifying / rectifying circuit, a fourth constant voltage is applied to a gate of the seventh MOSFET, and in each of the second to n-th stage amplifying / rectifying circuits, the twelfth MOSFET is applied. 11. The logarithmic amplifier according to claim 10, wherein a fourth constant voltage is applied to the gate of the logarithmic amplifier. 12. In the first stage amplifying / rectifying circuit, a fourth constant voltage is applied to a gate of the seventh MOSFET, and in each of the second to n-th stage amplifying / rectifying circuits, A fifth constant voltage is applied to the gate of the twelfth MOSFET, and the fifth constant voltage in the first stage amplifying / rectifying circuit and the fifth constant voltage in the second to n-th stage amplifying / rectifying circuits. 11. The logarithmic amplifier circuit according to claim 10, wherein at least one voltage value is changeable, and the logarithmic characteristic of the output signal can be adjusted by changing the voltage value of the fourth constant voltage or the fifth constant voltage.