GB2335061A

GB2335061A - Logarithmic amplifier

Info

Publication number: GB2335061A
Application number: GB9905153A
Authority: GB
Inventors: Katsuiji Kimura
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1998-03-05
Filing date: 1999-03-05
Publication date: 1999-09-08
Also published as: JP3080226B2; JPH11251853A; GB9905153D0

Abstract

A logarithmic amplifier that decreases the temperature dependence of an output signal. The amplifier has cascade-connected amplifier-rectifier circuits S1...Sn. Each having a MOS differential pair M1, M2, third and fourth MOSFETs M3, M4 serving respectively as loads of the first and second MOSFETs M1, M2, a triple-tail cell M5, M6, M7, and eighth and ninth MOSFETs M8, M9 serving respectively as loads of the fifth and sixth MOSFETs M5, M6. A constant voltage VB is commonly applied to gates of the MOSFETs M3, M4, M8, M9. A differential voltage generated between drains of the first and second MOSFETs M1, M2 is applied across gates of the fifth and sixth MOSFETs M5, M6. Drains of the fifth and sixth MOSFETs M5, M6 constitute the amplified output terminal pair of a corresponding one of the amplifier-rectifier circuits. A drain of the seventh MOSFET M7 constitutes the rectified output terminal of a corresponding one of the amplifier-rectifier circuits.

Description

2335061 LOGARITENIC AMPLIFIER

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a logarithmic amplifier suitable to semiconductor Large-Scale Integrated circuits (LSIs) and more particularly, to a logarithmic amplifier comprising cascade-connected amplifier-rectifier circuits each having amplifier and rectifier functions, which has a superior temperature characteristic and which is able to change or adjust readily the logarithmic characteristic.

2. Description of the Prior Art

A conventional logarithmic amplifier is disclosed in the Japanese Non-Examined Patent Publication No. 9-36686 published in February 1997, which corresponds to the United States Patent No. 5,631, 594 issued to the inventor of the present invention, K. Kimura, on May 20, 1997.

In general, a logarithmic amplifier is realized by cascade-connected differential amplifiers located at a plurality of stages, rectifiers provided for the respective differential amplifiers, and an adder. An initial input signal to be amplified is applied to a first one of the cascade-connected differential amplifiers. An amplified output signal of each of the cascade-connected differential amplifiers at the plurality of stages is applied to a corresponding one of the rectifiers. Rectified output signals of the rectifiers are applied to the adder and added to one another, resulting in a logarithmically-amplified output signal as an output of the adder.

In the conventional logarithmic amplifier disclosed in the Japanese NonExamined Patent Publication No. 9-36686, the differential amplifier and the rectifier at each stage are replaced with a triple-tail cell, thereby realizing the amplifier and rectifier functions by a single circuit cell.

Fig. 1 shows the circuit configuration of the triple tail cell used in the conventional - logarithmic amplifier disclosed in the Japanese Non-Examined Patent Publication No.

9-36686.

In Fig. 1, the triple-tail cell is comprised of three Metal-Oxide-Semiconductor (MOS) FieldEffect Transistors (MOSFETs) M101, M102, and M103 whose sources are coupled together, which are driven by a single constant current sink 101 (current value: 10). Gates of the MOSFETs M101 and M102 constitute an input terminal pair of the triple-tail cell, across which an input voltage Vi is applied. One terminal of the constant current sink 101 is connected to the coupled sources of the MOSFETs M101, M102, and M103, and the other terminal thereof is connected to the ground.

The gate of the MOSFET M101 is connected to one terminal of a resistor 104 (resistance value: R) and the gate of the MOSFET M102 is connected to one terminal of another resistor 105 (resistance value: R). The other terminals of the resistors 104 and 105 are coupled together to be connected to the ground through a constant voltage source 102 (voltage value: VR).

Drains of the MOSFETs M101 and M102 are connected to a supply voltage line applied with a power supply voltage VDD through load resistors 106 and 107 (resistance value: RL), respectively.

The drains of the MOSFETs M101 and M102 constitute an amplified-signal output terminal pair of the triple-tail cell.

A drain of the MOSFET M103 constitutes a rectified-signal output terminal of the triple-tail cell.

A gate of the MOSFET M103 is applied with a control voltage V,b generated by a constant voltage source 103. A drain current IsQ of the MOSFET M103 is derived as a rectified output current from the drain of the MOSFET M103 serving as the rectified-signal outputterminal. An amplified output voltage is derived from the drains of the MOSFETs M101 and M102 serving as the amplified signal output terminal pair.

In the above-described triple-tail cell in Fig. 1, when drain currents flowing through the drains of the MOSFETs M101 and M102 are defined as ID1o, and ID102, respectively, a differential output current AI defined as AI = ID101 - ID102 is approximately proportional to the applied input voltage Vi. The differential output current AI is converted by the load resistors 106 and 107 to produce two output voltages V01 and V02 at the drains of the MOSFETs M1 0 1 and M1 0 2, respect ively. Then, a dif f erential output voltage AV defined as AV = V01 - V02 is approximately proportional to the applied input voltage Vi. This means that the triple tail cell has a differential amplifier function.

On the other hand, the drain current IsQ flowing through the drain of the MOSFET M103 has a square-law characteristic. This means that the triple-tail cell has a full-wave rectifier function also.

With the conventional logarithmic amplifier disclosed in the Japanese NonExamined Patent Publication No. 9-36686, a plurality of the triple-tail cells shown in Fig. 1 are cascade-connected through coupling capacitors (capacitance value: C), and the rectified output currents IsQ of the triple-tail cells are added to one another by an adder. In this case, an output of the adder has a logarithmic characteristic with respect to the applied input voltage Vi.

However, the conventional triple-tail cell shown in Fig. 1 has the following problem because the output voltages V01 and V02 as the amplified output signals are produced by the load resistors 106 and 107.

Specifically, in general, an output current of a circuit using MOSFETs is proportional to the t rans conductance parameter P. Although the transconductance parameter P is approximatel proportional to the (-2/3)th power of the absolute temperature T, i.e.,, (T -2/3) ' it may be thought as inversely proportional to the absolute temperature T at temperatures in the vicinity of room temperature due to the first-order approximation. Therefore, the output current of the amplifier circuit using MOSFETs varies dependent on the absolute temperature T, which means that this output current of the amplifier has a so-called "temperature characteristic". This output current varies further dependent on the temperature characteristics of a driving current of the circuit and load resistors thereof.

Accordingly, with the conventional logarithmic amplifier using the conventional triple-tail cell of Fig. 1, the voltage gain of the amplified output signal of the triple-tail cell has a temperature characteristic, which causes a temperature dependence of the logarithmic characteristic. As a result, the logarithmic characteristic of the amplified output signal of the conventional logarithmic amplifier has an unsatisfactorily large temperature dependence.

5- SUMMARY OF THE INVENTION

Accordingly, an object of the present invention to provide a logarithmic amplif ier that makes it possible to decrease the temperature dependence of the logarithmic characteristic of 5 an output signal.

Another object of the present invention to provide a logarithmic amplifier in which a logarithmic characteristic of an output signal can be readily changed or adjusted.

The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.

A logarithmic amplifier according to a first aspect of the present invention is comprised of cascade-connected amplifier-rectifier circuits located at first to n-th stages, where n is an integer equal to or greater than two.

amplifier-rectifier circuits receives an input Each of the sianal and produces an amplified output signal anda rectified output signal. An initial input signal to be amplified is used as the input signal to the amplifier-rectifier circuit at the first 20 stage.

The amplified output signals from the amplifierrectifier circuits located at the first to (n - 1)-th stages are used as the input signals to the amplifier-rectifier circuits at the second to n-th stages, respectively.

The rectified output signals from the amplifierrectifier circuits located at the first to n-th stages are added to one another to produce an output signal of the logarithmic amplifier. The output signal of the logarithmic amplifier is a logarithmically amplified signal of the initial input signal.

Each of the amplifier-rectifier circuits located at the first ton-th stages iscomprisedof aMOS differential pair formed by first and second MOSFETs; third and fourth MOSFETs serving respectively as loads of the first and second MOSFETs; a triple-tail cell formed by source-coupled fifth, sixth, and seventh MOSFETs driven by a single tail current; and eighth and ninth MOSFETs serving respectively as loads of the f if th and sixth MOSFETs.

A f irst constant voltage is commonly applied to gates of the third and fourth MOSFETs. A differential voltage generated between drains of the first and second MOSFETs of the MOS differential pair is applied across drains of the fifth and sixth MOSFETs of the triple-tail cell. A second constant voltage is commonly applied to gates of the eighth and ninth MOSFETs.

Gates of the first and second MOSFETs of the MOS differential pair constitute an input terminal pair of a corresponding one of the amplif ier-rectif ier circuits located at the first to n-th stages. Drains of the fifth and sixth MOSFETs of the triple-tail cell constitute an amplified-signal output terminal pair of the corresponding one of the amplif ier-rectif ier circuits located at the first to n-th stages. A drain of the seventh MOSFET of the triple-tail cell constitutes a rectif ied-signal output terminal of the corresponding one of the amplif ier-rectif ier circuits located at the first to n-th stages.

With the logarithmic amplifier according to the first aspect of the present invention, each of the amplifier-rectifier circuits at the first to n-th stages is comprised of the MOS differential pair formed by the source-coupled first and second MOSFETs, the third and fourth MOSFETs serving respectively as the loads of the first and second MOSFETs, the triple-tail cell f ormed by the source-coupled fifth, sixth, and seventh MOSFETs driven by the single tail current, and the eighth and ninth MOSFETs serving respectively as loads of the fifth and sixth MOSFETs.

Also, the first constant voltage is commonly applied to the gates of the third and fourth MOSFETs. The differential voltage generated between the drains of the first and second MOSFETs of the MOS dif f erential pair is applied across the drains of the f if th and sixth MOSFETs of the tripletail cell. The second constant voltage is commonly applied to the gates of the eighth and ninth MOSFETs.

Moreover, the gates of the first and second MOSFETs of the MOS differential pair constitute the input terminal pair of a corresponding one of the amplifier-rectifier circuits located at the first to n-th stages. The drains of the f if th and sixth MOSFETs of the triple-tail cell constitute the amplif ied-signal output terminal pair of the corresponding one of the amplif ier-rectif ier circuits located at the first to n-th stages.

The drain of the seventh MOSFET of the triple-tail cell constitutes the rectified-signal output terminal of the corresponding one of the amplif ier-rectif ier circuits located at the first to n-th stages.

Therefore, in each of the amplifier-rectifier circuits at the first to n-th stages, the drain currents of the first and second MOSFETs of the MOS differential pair, each of which has a square-law characteristic with respect to the input signal, are and fourth MOSFETs, As a result, the differential voltage (i.e., the differential output voltage of the MOS differential pair) is generated between the drains of the first and second MOSFETs of the MOS differential pair. This differential voltage has a linear characteristic with respect to the input signal and at the same time, the constant of proportionality (i.e., the gain) of the MOS differential pair is independent of the transconductance parameter of the first and second MOSFETs and the tail current of the MOS differential pair.

Further, each of the drain currents of the f if th and sixth MOSFETs of the triple-tail cell has a square-law characteristic square-root-compressed by the third resnectivelv.

with respect to the differential voltage of the MOS differential pair applied to the gates of the fifth and sixth MOSFETs. The drain currents of the fifth and sixth MOSFETs are squareroot -compres s ed by the eighth and ninth MOSFETs serving as the fifth and sixth MOSFETs, respectively. As a result, the differential voltage (i.e., the differential output voltage of the MOS dif f erential pair) is generated between the drains of the f irst and second MOSFETs. This dif f erential voltage has a linear characteristic with respect to the input signal and at the same time, the constant of proportionality (i.e., the gain) of the MOS differential pair is independent of the transconductance parameter of the first and second MOSFETs and the tail current of the MOS differential pair.

On the other hand, the drain current of the seventh MOSFET, which has a square-law characteristic with respect to the differential voltage of the MOS differential pair applied across the gates of the fifth and sixth MOSFETs, is outputted from the rectified-signal output terminal.

Thus, in the amplifier-rectifier circuits at the first to n-th stages, the voltage gains of the amplified output signals does not dependent on the transconductance parameters and the tail currents. Also, unlike the conventional logarithmic amplifier disclosed in the Japanese Non-Examined Patent Publication No. 9-36686, load resistors are unnecessary in each of the triple-tail cells.

As a result, the rectified output signals of the amplifier-rectifier circuits at the first to n-th stages are not affected by the ambient temperature. This means that the temperature dependence of the output signal of the logarithmic amplifier according to the first aspect is decreased.

In a preferred embodiment of the logarithmic amplifier according to the first aspect of the present invention, the gate of the seventh MOSFET is applied with a third constant voltage in each of the amplifier-rectifier circuits at the first to n-th stages.

In this embodiment, there is an additional advantage that the rectified output signal has an ideal square-law characteristic in each of the amplif ier-rectif ier circuits at the first to n-th stages.

In another preferred embodiment of the logarithmic amplifier according to the first aspect of the present invention, the gate of the seventh MOSFET is applied with a third constant voltage in each of the amplifierrectifier circuits at the first to n-th stages, and at least one of the third constant voltages in the amplifier-rectifier circuits at the first to n-th stages is changeable, thereby making the logarithmic characteristic of the output signal of the logarithmic amplifier adjustable.

In this embodiment, there is an additional advantage that the logarithmic characteristic of the logarithmic amplifier can be adjustable.

A logarithmic amplifier according to a second aspect of the present invention is comprised of cascade-connected amplifier-rectifier circuits located at first to n-th stages, where n is an integer equal to or greater than two. Each of the amplifier-rectifier circuits receives an input signal and produces an amplified output signal and a rectified output signal.

An initial input signal to be amplified is used as the input signal to the amplifier-rectifier circuit at the first stage.

The amplified output signals from the amplifierrectifier circuits located at the first to (n - 1)-th stages are used as the input signals to the amplif ier-rectif ier circuits at the second to n-th stages, respectively.

Each of the amplifier-rectifier circuits located at the first to n-th stages is comprised of aMOS differential pair formed by first and second MOSFETs; third and fourth MOSFETs serving -12 respectively as loads of the first and second MOSFETs; a quadritail cell formed by source-coupled fifth, sixth, seventh, and eighth MOSFETs driven by a single tail current; and ninth and tenth MOSFETs serving respectively as loads of the f if th and sixth 5 MOSFETs.

A first constant voltage is commonly applied to gates of the third and fourth MOSFETs. A differential voltage generated between drains of the first and second MOSFETs of the MOS dif f erential pair is applied across drains of the f if th and sixth MOSFETs of the quadritail cell. A second constant voltage is commonly applied to gates of the ninth and tenth MOSFETs.

Gates of the f irst and second MOSFETs of the MOS differential pair constitute an input terminal pair of a corresponding one of the amplif ier-rectif ier circuits located at the first to n-th stages. Drains of the f if th and sixth MOSFETs of the quadritail cell constitute an amplified-signal output terminal pair of the corresponding one of the amplif ier-rectif ier circuits located at the f irst to n-th stages. Coupled drains of the seventh and eighth MOSFETs of the quadritail cell constitutes a rectified-signal output terminal of the corresponding one of the amplifier-rectifier circuits located at the first to n-th stages.

With the logarithmic amplifier according to the second aspect of the present invention, each of the triple-tail cells formed by the f if th, sixth, and seventh MOSFETs is replaced with a quadritail cell formed by the f if th, sixth, seventh, and eighth MOSFETs. When the drains of the seventh and eighth MOSFETs are coupled together in the quadritail cell, the quadritail cell may provide the same operation as that of the triple-tail cell; in other words, the quadritail cell may be equivalent in operation to the triple-tail cell. Therefore, because of the same reason as that shown in the amplifier according to the first aspect, the same advantages as those in the first aspect are obtained.

In a preferred embodiment of the logarithmic amplifier according to the second aspect of the present invention, the gates of the seventh and eighth MOSFETs are commonly applied with a third constant voltage in each of the amplifier-rectifier circuits at the first to n-th stages.

In another preferred embodiment of the logarithmic 20 amplifier according to the second aspect of the present invention, the gates of the seventh and eighth MOSFETs are commonly applied with a third constant voltage in each of the amplifier-rectifier circuits at the first to n-th stages, and at least one of the third constant voltages in the amplifierrectifier circuits at the f irst to n-th stages is changeable, thereby making the logarithmic characteristic of the output signal of the logarithmic amplifier adjustable.

A logarithmic amplifier according to a third aspect of the present invention is comprised of cascade-connected amplifier-rectifier circuits located at first to n-th stages, where n is an integer equal to or greater than two. Each of the amplifier- rectifier circuits receives an input signal and produces an amplified output signal and a rectified output signal.

The amplified output signals from the amplifier rectifier circuits located at the first to (n - 1)-th stages are used as the input signals to the amplifier-rectifier circuits at the second to n-th stages, respectively.

The rectified output signals from the amplifier rectifier circuits located at the first to n-th stages are added to one another to produce an output signal of the logarithmic amplifier. The output signal of the logarithmic amplifier is a logarithmically amplified signal of the initial input signal.

The amplifier-rectifier circuit located at the first stage is comprised of a first MOS differential pair formed by first and second MOSFETs; third and f ourth MOSFETs serving respectively as loads of the first and second MOSFETs; a first triple-tail cell f ormed by source-coupled f if th, s ixth, and seventh MOSFETs driven by a single tail current; and eighth and ninth MOSFETs serving respectively as loads of the fifth and sixth MOSFETs.

A first constant voltage is commonly applied to gates of the third and fourth MOSFETs. A differential voltage generated between drains of the first and second MOSFETs of the first MOS differential pair is applied across drains of the fifth and sixth MOSFETs of the first triple-tail cell. A second constant voltage is commonly applied to gates of the eighth and ninth MOSFETs.

Gates of the first and second MOSFETs of the first MOS differential pair constitute an input terminal pair of the amplifier-rectifier circuits located at the first stage. Drains of the fifth and sixth MOSFETs of the first triple-tail cell constitute an amplified-signal output terminal pair of the amplifier-rectifier circuit located at the first stage. A drain of the seventh MOSFET of the first triple-tail cell constitutes a rectified-signal output terminal of the amplifier-rectifier circuit located at the first stage.

Each of the amplifier-rectifier circuits located at the second to n-th stages is comprised of a second triple-tail cell -16 formed by source-coupled tenth, eleventh, and twelfth MOSFETs driven by a single tail current; and thirteenth and fourteenth MOSFETs serving respectively as loads of the tenth and eleventh MOSFETs. A third constant voltage is commonly applied to gates of the thirteenth and fourteenth MOSFETs.

Gates of the tenth and eleventh MOSFETs of the second triple-tail cell constitute an input terminal pair of a corresponding one of the amplif ier-rectif ier circuits located at the second to n-th stages.

MOSFETs of the second triple-tail cell constitute Drains of the tenth and eleventh an amplified-signal output terminal pair of the corresponding one of the amplif ier-rectif ier circuits located at the second to n-th stages. A drain of the twelfth MOSFET of the second triple-tail cell constitutes a recti f ied- signal output terminal of the corresponding one of the amplif ierrectif ier circuits located at the second to n-th stages.

As described above, the logarithmic amplifier according to the third aspect of the present invention corresponds to one obtained by removing the MOS differential pair in each of the amplifier-rectifier circuits at the second to n-th stages in the amplifier according to the first aspect of the present invention.

In each of the amplif ier-rectif ier circuits at the second to n-th stages, the differential voltage of the second triple-tail cell (i.e., the amplified signal of the corresponding amplifier-rectifier circuit) is approximately proportional to the input signal of the second triple-tail cell (i.e., the input signal of the corresponding amplifier-rectifier circuit) and at the same time, the gain of the second triple-tail cell is independent of the transconductance parameter of the tenth to twelfth MOSFETs and the tail current of the second triple-tail cell.

On the other hand, the drain current of the twelfth MOSFET of the second triple-tail cell, which has a square-law characteristic with respect to the input signal of the second triple-tail cell, is outputted from the rectified-signal output terminal. The rectified-signal output terminal is proportional to the square of the input signal of the second triple-tail cell.

Thus, the gain of the output signal of the logarithmic amplifier is not dependent on the t ran s conductance parameters and the tail currents. Also, unlike the conventional logarithmic amplifier disclosed in the Japanese Non-Examined Patent Publication No. 9-36686, load resistors are unnecessary in each of the triple-tail cells. As a result, the temperature dependence of the output signal of the logarithmic amplifier according to the third aspect is decreased.

In a preferred embodiment of the logarithmic amplifier according to the third aspect of the present invention, the gate of the seventh MOSFET in the amplifier-rectifier circuit at the first stage is applied with a fourth constant voltage, and the twelfth MOSFET in each of the amplifier-rectifier circuits at the second to n-th stages is applied with a f if th constant voltage.

In another preferred embodiment of the logarithmic amplifier according to the third aspect of the present invention, the gate of the seventh MOSFET in the amplif ier-rectif ier circuit at the first stage is applied with a fourth constant voltage, and the twelfth MOSFET in each of the amplifier-rectifier circuits at the second to n-th stages is applied with a fifth constant voltage. Also, at least one of the fourth and fifth constant voltages is changeable, thereby making the logarithmic characteristic of the output signal of the logarithmic amplifier adjustable.

A logarithmic amplifier according to a fourth aspect of the present invention is comprised of cascade-connected amplifier-rectifier circuits located at first to n-th stages, where n is an integer equal to or greater than two. Each of the amplifier-rectifier circuits receives an input signal and produces an amplified output signal and a rectified output signal.

The rectified output signals from the amplifier- rectifier circuits located at the first to n-th stages are added to one another to produce an output signal of the logarithmic amplifier. The output signal of the logarithmic amplifier is a logarithmically amplified signal of the initial input signal.

The amplifier-rectifier circuit located at the first stage is comprised of a first MOS differential pair formedby first and second MOSFETs; third and fourth MOSFETs serving respectively as loads of the first and second MOSFETs; a first quadritail cell formed by source-coupled fifth, sixth, seventh, and eighth MOSFETs driven by a single tail current; and ninth and tenth MOSFETs serving respectively as loads of the fifth and sixth MOSFETs.

A first constant voltage is commonly applied to gates of the third and fourth MOSFETs. A differential voltage generated 20- between drains of the first and second MOSFETs of the first MOS dif f erential pair is applied across drains of the f if th and sixth MOSFETs of the first quadritail cell. A second constant voltage is commonly applied to gates of the ninth and tenth MOSFETs.

Gates of the first and second MOSFETs of the first MOS differential pair constitute an input terminal pair of the amplifier-rectifier circuits located at the first stage. Drains of the fifth and sixth MOSFETs of the first quadritail cell constitute an amplified-signal output terminal pair of the amplifier-rectifier circuit located at the first stage. Coupled drains of the seventh and eighth MOSFETs of the first quadritail cell constitutes a rectified-signal output terminal of the amplifier-rectifier circuit located at the first stage.

Each of the amplifier-rectifier circuits located at the second to n-th stages is comprised of a second quadritail cell formed by source-coupledeleventh, twelfth, thirteenth, and fourteenth MOSFETs driven by a single tail current; and fifteenth and sixteenth MOSFETs serving respectively as loads of the eleventh and twelfth MOSFETs. A third constant voltage is commonly applied to gates of the thirteenth and fourteenth MOSFETs.

Gates of the eleventh and twelfth MOSFETs of the second quadritail cell constitute an input terminal pair of a corresponding one of the amplif ier-rectif ier circuits located at the second to n-th stages. Drains of the eleventh and twelfth and MOSFETs of the second triple-tail cell constitute an amplif ied-signal output terminal pair of the corresponding one of the ampli f ier-rectif ier circuits located at the second to n-th stages. Coupled drains of the thirteenth and fourteenth MOSFETs of the second quadritail cell constitutes a rectified-signal output terminal of the corresponding one of the amplifier rectifier circuits located at the second to n-th stages.

As described above, the logarithmic amplifier according to the fourth aspect of the present invention corresponds to one obtained by removing the MOS differential pair in each of the amplifier-rectifier circuits at the second to n-th stages in the amplifier according to the third aspect of the present invention. In other words, the logarithmic amplifier according to the fourth aspect corresponds to one obtained by replacing the triple-tail cell in each of the amplifier-rectifier circuits at the first to n-th stages in the amplifier according to the second aspect with a quadritail cell.

Accordingly, because of the same reason as that of the second aspect, the same advantages as those in the first aspect are obtained.

In a preferred embodiment of the logarithmic amplifier according to the fourth aspect of the present invention, the gates of the seventh and eighth MOSFETs are commonly applied with a fourth constant voltage in the amplif ier-rectif ier circuit at the first stage, and the gates of the thirteenth and fourteenth MOSFETs are commonly applied with a f if th constant voltage in each of the amplifier- rectifier circuits at the second to n-th stages.

In another preferred embodiment of the logarithmic amplifier according to the second aspect of the present invention, the gates of the seventh and eighth MOSFETs are commonly applied with a fourth constant voltage in the amplifier-rectifier circuit at the first stage, and the gates of the thirteenth and fourteenth MOSFETs are commonly applied with a f if th constant voltage in each of the amplif ier-rectif ier circuits at the second to n-th stages.

Further, at least one of the third and fourth constant voltages in the amplifier-rectifier circuits at the first to n-th stages is changeable, thereby making the logarithmic characteristic of the output signal of the logarithmic amplifier adjustable.

BRIEF DESCRIPTION OF THE DRAWINGS is Preferred features of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

Fig. 1 is a circuit diagram showing a conventional MOS triple-tail cell used in a conventional logarithmic amplifier.

Fig. 2 is a circuit diagram showing a logarithmic amplifier according to a first embodiment of the present invention.

Fig. 3 is a circuit diagram showing an amplifier rectifier circuit located at the first stage of the logarithmic amplifier according to the first embodiment of Fig. 2.

Fig. 4 is a graph showing the temperature characteristic of the transconductance parameter P.

Fig. 5 is a graph showing the calculated output voltage characteristics of the MOS differential pair used in the logarithmic amplifier according to the first embodiment of Fig.

2.

Fig. 6 is a graph showing the calculated output voltage characteristics and the differential output voltage characteristics of the MOS differential pair used in the logarithmic amplifier according to the first embodiment of Fig. 2.

Fig. 7 is a graph showing the calculated output current characteristics and rectified output current characteristics of the logarithmic amplifier according to the first embodiment of Fig. 2.

Fig. 8 is. a circuit diagram showing a logarithmic amplifier according to a second embodiment of the present invention.

Fig. 9 is a circuit diagram showing an amplifierrectifier circuit located at the first stage of the logarithmic 10 amplifier according to the second embodiment of Fig. 8.

Fig. 10 is a graph showing the calculated drain current characteristics of the MOSFETs forming the quadritail cell used in the logarithmic amplifier according to the second embodiment of Fig. 8.

Fig. 11 is a circuit diagram showing a logarithmic amplifier according to a third embodiment of the present invention.

Fig. 12 is a circuit diagram showing a logarithmic amplifier according to a fourth embodiment of the present 20 invention.

Fig. 13 is a circuit diagram showing a logarithmi amplifier according to a fifth embodiment of the presen invention.

c t 1 1 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described in detail below while referring to the drawings 5 attached.

FIRST EMBODIMENT A logarithmic amplifier according to a first embodiment of the present invention has the circuit configuration shown in Fig. 2.

As shown in Fig. 2, this logarithmic amplifier is equipped with first to n-th amplifier-rectifier circuits SI, S2....... Sn ca s cade- connected located respectively at f irst to n-th stages, and an adder circuit for adding rectified output signals of the amplifier-rectifier circuits S1, S2. Sn to produce a logarithmically amplified output signal. Here, the rectified output signals of the amplif ier-rectif ier circuits SI, S2. ' Sn are commonly applied to an output terminal 10 of the logarithmic amplifier through a connection or wiring line 9. Therefore, it may be said that the connection line 9 serves as the adder circuit.

Since the first to n-th amplifier-rectifier circuits SI, S201. Sn have the same conf iguration, only the f irst amplifier-rectifier circuit S1 is explained in detail below and the detailed explanation about the second to n-th amplifier- rectifier circuits S2. Sn is omitted for the sake of -2 6 simplification. (configuration of the circuit S1) As clearly shown in Fig. 3, the first amplif ier-rectif ier circuit S1 is comprised of a MOS differential pair 4 formed by two n-channel MOSFETs M1 and M2 whose sources are coupled together, and a triple-tail cell 5 formed by three n-channel MOSFETs M5, M6, and M7 whose sources are coupled together.

The coupled sources of the MOSFETs M1 and M2 forming the MOS differential pair 4 are connected to the ground through a constant current sink 1 (current value: Issi). The MOS differential pair 4 is driven by the constant current Iss, generated by the constant current sink 1. The MOSFETs M1 and M2 have the same ratio (W/L) of the gate width W to the gate length L, which is K, times as large as that of a unit MOSFET, where K, is a constant equal to or greater than unity (i.e., K, k 1). Gates of the MOSFETs M1 and M2 constitute an input terminal pair of the logarithmic amplifier according to the first embodiment, across which an input voltage Vi is applied.

An n-channel MOSFET M3 serves as a load of the MOSFET M1.

The MOSFET M3 has a source connected to a drain of the MOSFET M1, a drain connected to a supply voltage line applied with a power supply voltage VDD, and a gate applied with a constant dc voltage, i. e., a bias voltage VB. Similarly, An n-channel MOSFET M4 serves as a load of the MOSFET M2. The MOSFET M4 has a source connected to a drain of the MOSFET M2, a drain connected to the supply voltage line Of VDD, and a gate applied with the same dc voltage, i.e., the same bias voltage VB. The MOSFETs M3 and M4 have the same ratio (W/L), which is K2 times as large as that of a unit MOSFET, where K2 is a constant equal to or greater than unity (i.e., K2 The coupled sources of the MOSFETs MS, M6, and M7 constituting the tripletail cell 5 are connected to the ground through a constant current sink 3 (current value: I0j). The triple-tail cell 5 is driven by the constant current I01 generated by the constant current sink 3. The constant current I01 may be termed a tail current. Gates of the MOSFETs MS and M6 are respectively connected to the drains of the M05FETs MI and M2. The drains of the MOSFETs MS and M6 form first and second output terminals (i.e., amplified-signal output terminals) of the amplifier- rectifier circuit S1.

The Gate of the MOSFET M5 is applied with a first output voltage V01 of the MOS differential pair 4 generated at the drain of the MOSFET M1. The Gate of the MOSFET M6 is applied with a second output voltage V02 of the MOS dif f erential pair 4 generated at the drain of the MOSFET M2. The difference between the first and second output voltages V01 and V02 (i.e., a dif f erential output voltage of the MOS differential pair 4) is an input voltage for the triple-tail cell 5.

A gate of the MOSFET M7 is applied with a dc constant voltage, i.e., a control voltage Vcl. A drain of the MOSFET M7 forms a third output terminal (i.e., an amplified-signal output terminal) of the amplifierrectifier circuit S1, from which a rectified output current I, of the circuit S1 is derived.

The MOSFETs M5 and M6 have the same ratio (W/L), which is K, times as large as that of a unit MOSFET. The MOSFET M7 has a ratio (W/L) which is K3 times as large as that of a unit MOSFET, where K3 is a constant equal to or greater than unity (i.e., K3 a 1).

An n-channel MOSFET M10 and a constant current sink 2 (current value: Issl/2) constitute a control voltage generator for generating the control voltage Vcj to be applied to the gate of the MOSFET M7. A gate of the MOSFET M10 is applied with the same bias voltage VB as that commonly applied to the gates of the MOSFETs M3 and M4. A drain of the MOSFET M10 is connected to the supply voltage line Of VDD. A source of the MOSFET M10 is connected to one terminal of the constant current sink 2.

The control voltage Vcj is equal to the source voltage of the MOSFET M10. In other words, the control voltage Vcj is generated at the source of the MOSFET M10. The gate of the MOSFET M7 of the triple- tail cell 5 is connected to the source of the MOSFET M10.

(configuration of the circuits S2 to Sn) In the second amplifierrectifier circuit S2 having substantially the same configuration as that of the first amplifier-rectifier circuit S1, the gates of the MOSFETs M1 and M2 of the MOS differential pair 4 constitute an input terminal pair of the second amplif ier-rectif ier circuit S2. A third output voltage V03 in the first amplifier-rectifier circuit S1, which is generated at the drain of the MOSFET MS, is applied to the gate of the MOSFET M1. A fourth output voltage V04 in the first amplifier-rectifier circuit SI, which is generated at the drain of the MOSFET M6, is applied to the gate of the MOSFET M2. In other words, the differential output voltage (V03 - V04) in the first amplifier-rectifier circuit S1 is applied across the input terminal pair of the second amplif ier-rectif ier circuit S2 as the amplified output signal of the circuit S1.

The drains of MOSFETs MS and M6 of the MOS triple-tail cell 5 constitute first and second output terminals (i.e., amplified output terminals) of the second amplifier-rectifier circuit S2. The drain of the MOSFET M7 constitutes a third output terminal (i.e., a rectified output terminal) of the second amplifier- rectifier circuit S2, from which a rectified output current 12 Of the circuit S2 is derived.

A control voltage VC2, which is equal to the source voltage of the MOSFET M10, is applied to the gate of the MOSFET M7. The -30 constant current sink 1 for driving the MOS differential pair 4 has a current value ISS2. The constant current sink 2 connected to the MOSFET 4 has a current value (ISS2/2). The constant current sink 3 for driving the MOS triple-tail cell 5 has a current value 5 102.

The above description is applied to each of the third to n-th amplifierrectifier circuits S3 to Sn.

In the n-th amplifier-rectifier circuit Sn, a control voltage Vcn is applied to the gate of the MOSFET M7. The constant current sink 1 f or driving the MOS dif f erential pair 4 has a current value Issn. The constant current sink 2 connected to the MOSFET 4 has a current value (Issn/2). The constant current sink 3 for driving the MOS triple-tail cell 5 has a current value Ion. Unlike the f irst to (n - 1) - th amplif ier-rectif ier circuits S1 to Sn-1, a rectified output current In is derived from the drain of the MOSFET M7 while no amplified output signal is derived in the n-th amplifier-rectifier circuit Sn.

(operation principle of the circuit S1) Next, the operation principle of the first amplifier- rectifier circuits S1 used in the logarithmic amplifier according to the f irst embodiment of Fig. 2 is explained below with ref erence to Fig. 3.

Supposing that the channel-length modulation and the body ef f ect can be ignored, and that a drain current ID and a gate-to-source voltage VGs of a MOSFET operating in the saturation region has a square-law characteristic, the drain current IDis given by the following well-known expressions or equations (1a) and (1b).

(V > GS _ V TH)2 (V D= Kfl GS = T'U (1a) ID' 0 (VGS:5 VTH) (1b) In the equations (1a) and (1b), K is a ratio of the 10 gate-width to gate- length ratio (W/L) with respect to the ratio (W/L) of a unit MOSFET, and VTH and P are the threshold voltage and the transconductance parameter thereof, respectively. The transconductance parameter is defined as (c W OX t) OX) L 2 where g is the effective mobility of a carrier and Cox is the gate-oxide capacitance per unit area.

The ef f ective mobility [t varies dependent on the absolute temperature T according to the following equation (2). 3 2 P = 1A300 -F- ( 300) i 20 (2) The t rans conductance parameter P varies dependent on the absolute temperature T according to the following equation (3), 3 T 2 fl = J6300 (7300) (3) In the equations (2) and (3), the suffix "300" denotes the values of R, P, and T at 300 K (= 27 OC) Fig. 4 shows the temperature dependence of the transconductance parameter It is seen from Fig. 4 that the temperature characteristic of the t rans conductance parameter monotonously decreases with the increasing temperature T. (a. MOS Differential Pair) Fig. 3 shows the first amplifier-rectifier circuit S1, in which the currents Iss, and I01 and the voltage Vc are set as Iss, = Iss, Iol = Io, and Vcj = Vc for generalization.

Supposing that all the MOSFETs M1 to M4 are matched in characteristic, drain currents ID, and ID2 of the MOSFETs M1 and M2, which are two output currents of the MOS differential pair 4, are expressed in the following equations (4a) and (4b), respectively.

{I. + K.fl V, 7, 21 1 V, j 2 -5 D1 'W (4a) 2 2 Iss 2 FTSS ID2 Iss - K, PV,::--- - Vi vi 1:- -) (4 b) 2 { 'J:K,;p K, P As seen from the equations (4a) and (4b), the operating input voltage range of the MOS differential pair 4 is given as 1 Vi Is V FI-1 5,6 The drain currents ID, and ID2 Of the MOSFETs M1 and M2, which are expressed by the equations (4a) and (4b), are respectively square-root- compressed by the load MOSFETs M3 and M4 and at the same time, they are respectively converted to the first and second output voltages Vol and V02 expressed by the following equations (5a) and (5b).

VO 1 - VB - VTH - D vi rIj (5a) J2 K, FID T W V02 = VB - VTH - vi S rl (5b) 2 K, P) Thus, a differential output voltage &V, of the MOS differential pair 4 is given by the following equation (6) A V1 V01 V02 IDI -rK-2P -,D2) ( 1 vi 1 :! IS (6) EK, Sfi) It is seen from the equation (6) that the differential output voltage AV, is proportional to (IDI -,D2) - Here, the following identity (7) is utilized b ( Fa- - 7J-2- x Ja 2 b -vF2 x 2 (7) where a and b are constants, and x is a variable.

Then, the constant a and b and the variable x in the identity (7) are set as follows.

a=l, b X Vi F2 Is J1 6 (8) Then, the left-hand side of the identity (7) is equal to one obtained by substituting the above equations (4a) and (4b) into (IDI - JD2) - At this time, the right-hand side of the identity (7) is equal to Vi X, j-6 Therefore, the following equation (9) is established.

JDI -,D2 - JK, #6 Vi vi V K, Accordingly, the following equation (10) is established from the above equations (6) and (9).

F rK AV, - VOI - V02 V 7 V 2 (10) The following fact is seen from the equation (10). Specifically, if the ratio K2 of the gate-width to the gate-length ratios (W/L) of the MOSFETs M3 and M4 serving as the loads is greater than the ratio K, of the gate-width to the gate-length ratios (W/L) of the MOSFETs M1 and M2 of the MOS differential pair 4 (i.e., K2 > K,), the MOS differential pair 4 serves as an opposite- phase linear attenuator. If the ratio K2 of the MOSFETs M3 and M4 serving as the loads is equal to or less than the ratio K, of the MOSFETs M1 and M2 of the MOS differential pair 4 (i.e., K2 s K,), the MOS dif f erential pair 4 serves as an opposite-phase linear amplifier.

As seen from the equation (10), the dif f erential output voltage AV, of the MOS differential pair 4 having the MOSFETs M3 and M4 as the loads is proportional to the input voltage Vi. In other words, the MOS differential pair 4 having the MOSFETs M3 and M4 as the loads serves as a linear attenuator or linear amplifier with respect to the input voltage Vi. Also, if the value of (K2/K1) is set as a small value, a high gain will be realized.

Moreover, the constant or coefficient of the proportional relationship between the differential output voltage AV, and the input voltage V:1 in the equation (10) (i.e., the voltage gain of the MOS dif f erential pair 4) is (K,/K2) 1/2. Therefore, thevoltage gain of the MOS differential pair 4 does not contain the tail current Iss, the trans conductance parameter P, and the load resistance RL. This means that the voltage gain of the pair-4 has no temperature dependence or no temperature characteristic.

When the differential output current of the MOS dif f erential pair 4 is defined as AID, the current AID is expressed as A ID = ID1 - ID2 = (JIDI JD2)(\rID1 + JD2 (11) V 2 ISS K, P i K, fl - Vi 2 1 vi 1:!S IS - F1fl) Accordingly, it is seen that the differential output current AID of the MOS differential pair 4 comprises a linear term given by the following expression (12) and a nonlinear term given by the following expression (13).

VTD JD2 = -\fK, P Vi (12) I's V 2 flD 1 + JD2 -V 'K, FK, K, Here, a common source voltage at the coupled sources of the MOSFETs M1 and M2 of the MOS differential pair 4 is defined as Vs,. Then, the common source voltage Vs, is given by the following equation (14), 41 ( 2 IS _ V2) VS1 W VCM1 VTH (14) where Vcm, is the common-mode voltage of the input voltage Vi which is applied differentially across the gates of the MOSFETs M1 and M2.

As seen from the equation (14), the common source voltage Vs, is a function of the input voltage Vi. Therefore, the common source voltage Vs, varies dependent on the input voltage Vi. Also, the third term in the equation (14) is equal to (l/2) 112 of the term RI _ V2 K, in the expression (11).

As a result, it is seen that the nonlinear-term (13) of the differential output current AID Of the MOS differential pair 4 is generated due to the change or fluctuation of the common source voltage Vs,. This means that if the common source voltage Vs, of the MOS dif f erential pair 4 is fixed at a constant value, the MOS differential pair 4 can be operated linearly.

Additionally, when the common-mode voltage of the output voltages Vc)l and V02 is defined as VCM2, the voltage VCM2 is expressed in the following equation (15).

V01 + V02 1 D ID2 2 8 2 1 'Fx VCM2 2 P2 2 VB - I'm - K 1 ss 2 - 2' FK2 Kfl V8 - VW - PK KM1 V7W - vs,) 2 vi SS K, fl) (15) It is seen from the equation (15) that the conmon-mode voltage VCM2 of the output voltages V01 and V02 Of the dif f erential pair 4 is given by using the common-source voltage Vs, which is expressed by the above equation (14).

7.

1 t 1 1 1 20 1 Fig. 5 shows the calculated output voltage characteristic (i.e., the input-output characteristic) of the MOS differential pair 4 of the first amplifier-rectifier circuit S1. In Fig. 5, the curves al and a2 denote the first and second output voltages V01 and V02, respectively, the curve a3 denotes the common-mode voltage VCM2 of the first and second output voltages Vol and V02, the curve a4 denotes the voltage [-V01 + 2 WB - VTH)], and the curve a5 denotes the voltage [V02 - V01 + VB - VTIA. As seen from the curve a5, the differential output voltage AV, of the MOS differential pair 4 is proportional to the input voltage Vi.

Fig. 6 shows the measured output voltage characteristic (i.e., the inputoutput characteristic) of the MOS differential pair 4, where K2 = K, = 1. In this measurement, an n-channel MOSFET array (type: [tPA572T) was used. The threshold voltage VTH of the MOSFETs in this MOSFET array was approximately 1.5 V, and the t rans conductance parameter P thereof was greater by approximately two f igures than that of the popular MOSFETs that have been fabricated by the Complementary MOS (CMOS) processes and used in popular. Therefore, the power supply voltage VDD and the tail current Iss needed to be as large as possible in order to expand the input voltage range. As a result, the power supply voltage VDD was set as 5.0 V and the tail current Iss was set as 10.5 mA.

In Fig. 6, the curves bl and b2 denote the f irst and second output voltages V01 and V02 of the MOS differential pair 4, respectively, the curve b3 denotes the differential output voltage AV, (= V01 - V02) thereof, and the curve b4 denotes the differential output_ voltage -AV, (= V02 - V01) thereof. As seen from Fig. 6, the differential output voltage AV1 of the MOS dif f erential pair 4 is proportional to the input voltage Vj, within the wide input voltage range. (b. MOS Triple-Tail Cell) Next, the operation principle of the MOS triple-tail cell comprising the MOSFETs M5, M6, and M7 is explained below.

An output current of the MOS triple-tail cell 5 is disclosed in (i) the Japanese Non-Examined Patent Publication No.

8-83314 published in March 1996, which corresponds to the US Patent No. 5, 712, 810 issued to the inventor, K. Kimura, on January 27, 1998, (ii) the Japanese Non-Examined Patent Publication No. 8-84037 published in March 1996, which corresponds to the US Patent No. 5, 521, 542 issued to the inventor, K. Kimura, on May 28, 1996, and (iii) the Japanese Non-Examined Patent Publication No. 8-315056 published in November 1996, which corresponds to the US Patent No. 5, 617, 0 52 issued to the inventor, K. Kimura, on April 1, 1997.

In the amplifier-rectifier circuit S1 shown in Fig. 3, the output voltages V01 and V02 Of the MOS differential pair 4 are respectively applied to the input terminal pair of the triple-tail cell 5, i.e., to the gates of the MOSFETs M5 and M6. In other words, the differential output voltage AV, of the MOS differential pair 4 is applied across the gates of the MOSFETs M5 and M6. Accordingly, when the differential output current AI, of the 20 triple-tail cell 5 is given as AI1 = IDS - ID6, where ID5 and ID6 are drain currents of the MOSFETs M5 and M6, respectively.

According to the expression disclosed on the Japanese Non-Examined Patent Publication No. 8-84037, the differential output current AI, of the triple-tail cell 5 is expressed as the following equation (16).

AII ID5 - ID6 -2K3,8AV,Vc'+2,6AV, (K,+2)I' p 1 AV, 1:: min.

- 4V, 2 9 K3 +2 2 -2K V 2 2 (A V,) - 3 C K3 + 2 V 2 2 K3 V,' + 2 K3 + 4)LO - 4 K3 C K3 + 4 (16) In the expression (16), Vcl is a control voltage defined as consideration.

VC = VCM2 + VC' (1 6a) Here, the following facts (i) and (ii) are taken into (i) The differential output voltage AV, (= Vol - Vo2) of the MOS differential pair 4, which is applied across the gates of the MOSFETs M5 and M6 of the triple-tail cell 5, has a linear characteristic with respect to the input voltage Vi applied to the MOS differential pair 4 (i.e., the first amplifier-rectifier -43- 1 circuit S1).

(ii) Each of the drain currents IDs and ID6 Of the MOSFETs M5 and M6 of the triple-tail cell 5 has a square low characteristic with respect to its input voltage AV, (= V01 - V02) - As a result, it is seen that the differential output current AI, (= IDS - ID6) of the triple-tail cell, which is given by the above equation (16), needs to have a linear characteristic with respect to its input voltage AV,. In other words, the differential output current AI, needs to be proportional to the input voltage AV,. Thus, the following relationship AI, - c AV, needs to be established, where c is a constant.

Accordingly, the coefficient of AV, in the numerator of the equation (16) is equal to the constant c; i.e., the following 15 equation (17) needs to be established.

K3+2 2 V,2 - K +2),o -2K ' (17) 3 VC'+ (K3 -(AV) - 3 C C 2 When the equation (17) is established, differential output current AI, of the triple-tal i.e. the 1 cell 5 is proportional to the input voltage AV,, the differential output current AI1 is given by the following equation.

Ail = 2c1P ( -'3+ 2) AV' (18) At this time, the control voltage Vcl is derived from the equation (17), as shown in the following equation (19).

V1 C = K3 c+ K3 (K3 + 2)2 10 fl K, (K3 + 2)2 (AV)2 - 2K3 C 2 2 K3 (K, + 2) (19) Accordingly, to make the differential output current AI, of the triple- tail cell 5 given by the above equation (16) linear with respect to the input voltage AVi, in other words, to output a current with a square-law characteristic as the rectified output of the first amplifier-rectifier circuit S1, the control voltage Vc' needs to be determined so as to satisfy the above equation - (19). At this time, the differential output current &I, is expressed by the above equation (18). The control voltage Vc used in Fig. 3 is readily obtained by using the equations (19) and (16a). 20 For example, when the constant c satisfies the following relationship (20), c 2.(K,, 2)2 10 4fl (20) the control voltage Vc' needs to be set so as to satisfy the following relationship (21).

VC 1= - 1 L--, 1(, 1 (AV,) (21) 2 F; 2K3 2K3 As described above, when the control voltage Vj is set to satisfy the above relationship (19), the differential output current AI, of the triple-tail cell 5 has a linear characteristic with respect to its input voltage AV,. In this case, the differential output current AI, is given by the above equation (18).

By the way, in the amplif ier-rectif ier circuit S1 of Fig.

3, the MOS triple-tail cell 5 is cascade-connected to the MOS differential pair 4 with the load MOSFETs M3 and M4. Therefore, the gate voltages of the MOSFETs M5, M6, and M7 of the triple-tail cell 5 are equal to V01, V02, and VC (= Vcm2 + Vc'), respectively.

If the gate voltage VC (= VCM2 + VC') of the MOSFET M7 is set as constant, the configuration of the bias circuit for generating the control voltage VC can be simplified. This simplified bias circuit can be realized under the following condition.

Specifically, the common-mode voltage Vcm2 of the two output voltages Vol and V02 is given by the above equation (15), 5 and the control voltage Vcl satisfies the above equation (19). Therefore, the gate voltage VC (= VCM2 + VC') of the MOSFET M7 is expressed by the following equation (22).

IFK 21 VC - VCM2 + VC'= V8 - VTH - 2 iE2FK 1 )2 10 -K3c+ K3(K3+2 A.

K1K3(K3+ 2)" - 2K2 (A V1)'- 2 K3 C2 K3(K3+2) = constant (22) As described above, to produce an output current with a square-law characteristic in the amplifier-rectifier circuit S1 of Fig. 3, the coefficients of all theterms containing the input voltage AV, in the equation (22) need to be zero. In other words, the equation (22) needs to be simplif ied to the following equation (23).

47- c VC = VCM2 + VC'= VB - VTH - - = constant K3 + 2 (23) The necessary condition to satisfy the equation (23) is that the following relationships (24a) and (24b) are established.

K3 =2 LO = ISS ' c 2 p K2 P 8 (24a) (24b) As a result, when the values of the constant currents 10 10 and Iss, and other parameters are set to satisfy the relationships (24a) and (24b), the above equation (23) is established and at the same time, the gate voltage VC (= VCM2 + VC") of the MOSFET M7 is kept constant. Thus, the configuration of the bias circuit for generating the control voltage VC can be simplified, as shown in Fig. 3. In this case, the control voltage VC satisfies the above equation (19) and (16a) in the circuit configuration of Fig.

3 and accordingly, the differential output current &I, of the triple-tail cell 5 has a linear characteristic with respect to its input voltage AV,, as expressed in the above equation (18).

Also, as already explained above in the "a. MOS Differential Pair", the input voltage AV, to the MOS triple-tail cell 5, which is equal to the differential output voltage AV, of the MOS differential pair 4 with their load MOSFETs M3 and M4 in Fig. 3, is proportional to the input voltage Vi to the first rectifying-amplifying circuit S1.

Thus, it is confirmed that the first rectifyingamplifying circuit S1 of Fig. 3 outputs the differential output current AI, with a square-law characteristic with respect to the input voltage Vi.

Additionally, in this case, the MOS triple-tail cell 5 is operated as an adapt ively-bia sed differential pair disclosed in the Japanese NonExamined Patent Publication No. 6-152275 published in May 1994, which corresponds to the US Patent No. 5,381,113 issued to the inventor, Kimura, on January 10, 1995.

On the other hand, in the triple-tail cell 5 of Fig. 3, the drain currents ID5 and ID6 Of the MOSFETs M5 and M6 are respectively square- root-compres sed by the load MOSFETs M8 and M9 and at the same time, they are respectively converted to the third and fourth output voltages V03 and V04. When the differential output voltage of the triple- tail cell 5 is defined as AV2, the differential output voltage AV2 is expressed by the following equation (25).

1 i A V2 = J'03 - V04 = _Xl A V, Fj4 (25) If the ratio K4 Of the gate-width to the gate-length ratios (W/L) of the MOSFETs M8 and M9 serving as the loads of the MOSFETs M5 and M6 is greater than the ratio K, of the gate-width to the gate-length ratios (W/L) of the MOSFETs M1 and M2 of the MOS differential pair 4 (i.e., K2 > K,), the MOS triple-tail cell 5 serves as an opposite-phase linear attenuator. If the ratio K4 of the MOSFETs M8 and M9 is equal to or less than the ratio K, of the MOSFETs M1 and M2 (i.e., K2:s K,), the tripletail cell serves as an opposite-phase linear amplifier.

Since the equation (10) is established in the MOS differential pair 4, the differential output voltage AV2 of the triple-tail cell 5 is given by the following equation (26).

2 4 T72 = 1703 - V04:K Vi JK2 4 (26) As seen from the equation (26), the differential output voltage AV2 of the triple-tail cell 5 is proportional to the input voltage Vi of the MOS differential pair 4, i.e., the first amplif ier-rectif ier circuit S1. The constant (K,/K2.K4) 112 in the proportional relationship between the differential output voltage AV2 and the input voltage Vi in the equation (26) corresponds to the voltage gain of the amplifier-rectifier circuit S1) This voltage gain does not contain the tail current 10, the t rans conductance parameter P, and the load resistance RL.

This means that the voltage gain of the circuit S1 has no temperature dependence or no temperature characteristic. (c. Operating Input Voltage Range) Next, the operating input voltage range of the first amplifier-rectifier circuit S1 used in the logarithmic amplifier according to the first embodiment of Fig. 2 is explained below.

When the differential output current AI, has a linear characteristic with respect to the input voltage Vi, in other words, the triple-tail cell 5 is operated as an adapt ively-biased differential pair, the drain currents ID5, ID6, and ID7 of the MOSFETs M5, M6, and M7 are expressed by the following equations (27a), (27b), and (27c), respectively, where K, = 1 and K3 = 2.

IDS P AV, - 1 A v, 1:- (27a) 4( CL;), FL;) ID6 '(,J V, I V, (27b) 4 {I" _ 6 (,A V ID7 2)2 A V, (27C) The effective tail current of the MOSFETs M5 and M6 forming the MOS triple-tail cell 5 is equal to the sum of the drain currents ID5 and ID6. Therefore, the following equation (28) is obtained from the equations (25a) and (25b).

IDS +1D6 - 1 {I" + 6 (A V,) 2 2 1 AV, 1: FL;_) As clearly seen f rom the above equations (2 7 c) and (2 8), the two output currents ID7 (= I,) and (ID5 + ID6) of the triple-tail cell 5 are proportional to its input voltage AV and therefore, it is seen that each of the output currents ID7 (= I,) and (ID5 + ID6) has an ideal square-law characteristic with respect to the input voltage AV,. In other words, the rectified output current I, of the first amplifier-rectifier circuit S1 has an ideal square-law characteristic with respect to the input voltage AV,.

The linear input voltage range of the triple-tail cell 5 of Fig. 3 can be equal to the operating input voltage range of -52- the MOS differential pair 4 of Fig. 3 under some condition. This condition is obtained in the following way.

First, unless all the MOSFETs M5, M6, and M7 of the triple-tail cell 5 are pinched off, the output voltages V01 and V02 of the MOS differential pair 4 and the control voltage Vc are expressed as the following equations (29a), (29b), (29c), respectively.

V01 - VB - VTH - I D FK2 (2 9a) V02 - VB - VTH - ID2 K2 P S V1 = VB - V111 - IS K2 1 (2 9b) (29c) The equations (29a) and (29b) are the same as the above equations (13a) and (13b), respectively.

The maximum value of the differential output voltage AV1 is obtained when ID1 -- Iss and ID2 0. In this case, the equations (29a), (29b), (29c) are changed to the following equations (30a), (30b), (30c), respectively.

VOI - VB - VTH - IS J2S (30a) V02 - VB - VTH (30b) VC = VB ISSI TH - F'2fl - V (30c) Here, the common-source voltage of the MOSFETs M5, M6, and M7 is defined as VS2. Then, the following equation (31) is established in the equation (27a) for the drain current ID5.

IDS A V, -;)2 = PKI - V1 2 - VII Y (31) 4( By substituting the equation (30a) intotheequation (31), the following equation (32) is obtained.

AV,= 2 Vt - 2VTs - VS2 - I'5 (32) P218) Similarly, the following equation (33) is established in the equation (27b) for the drain current ID6.

L p;)2 ID6 4 ( A V, + 0 (V02 - v. - v,,, (33) By substituting the equation (30b) into the equation (33) the following equation (34) is obtained.

i; + AV, = 2(VB-2VTH - VS2) (34) Subtraction of the equation (32) from the equation (34) results in the equation (35).

AV = ISS K2 P (35) The equation (35) shows the maximum value of the differential input voltage AV, applied to the triple-tail cell 15 5.

On the other hand, the minimum value of the differential input voltage AV, is obtained when ID2 - Iss and ID1 0, which is expressed as follows.

-55 I.5 AV, = - F2 fl (36) Accordingly, from the equations (35) and (36), the range of the differential input voltage AV, is given by the following expression (37) 1 AV, is I_.7 P2fl (37) Moreover, f rom the relationship between the drain current ID7 and the common source voltage VS2, and the equations (27c) and (30c), the following equation (38) is obtained for the drain current ID7, where K, = 1 and K3 = 2.

ID7 ' {I, -,8 (A V)2} = 2,8 (V, - V, Vj 2 2 ISS 2,6 (V,, - 2 V,,, - V, 2 7K 2 (38) By substituting the above equations (34) and (35) into the equation (38) and solved. the following equation (39) is obtained.

= 2 Iss K2 (39) As a consequence, when the values of the constant currents 10 and Iss of the constant current sinks 1, 2, and 3 and the ratio K2 of the gate-width to the gate-length ratio (W/L) of the MOSFETs M3 and M4 with respect to the unit MOSFET are set to satisfy the above equation (39), the input voltage range of the MOS triple-tail cell 5 is equal to the operating input voltage range of th e MOS differential pair 4. Accordingly, the first amplifier- rectifier circuit S1 shown in Fig. 3 has an ideal square-law (i.e., f ull- wave rectifier) characteristic within its whole the operating input voltage range.

In this case, the MOS triple-tail cell 5 is operated as the adapt ively-biased differential pair having the maximum linear input voltage range.

The simplest circuit configuration of the first amplifier-rectifier circuit S1 of Fig. 3 is given under the condition that K, = K2 = 1, K3 = 2, and Iss = 10/2, as shown in Fig.

3. In this case, the constant c is given by the following expression (40).

c=2 FL; (40) The constant c given by the expression (40) satisfies the above equation (19). The control voltages Vc and Vcy are given 5 by the following equations (41a) and (41b), respectively.

J'C m VCM2 + VC'= VB - V27H - 1 FL; 2 (4 la) VC (4 1b) = 2 + v, Y) (Operation of Logarithmic Amplifier) As explained above, the firstamplifier-rectifier circuit S1 shown in Fig. 3 has a function of a differential amplifier circuit with a linear characteristic and a voltage gain of W, 2 /K2.K4) 1/2 and a function of a f ull-wave rectifier outputting a rectified current with a square-law characteristic.

Accordingly, with the logarithmic amplifier according to the f irst embodiment comprising the f irst to n-th amplif ier-rectif ier circuits S1 to Sn cascade-connected, as shown in Fig. 2, each of the rectified output currents 1,, 12, 1,, has a characteristic as shown in Fig. 7.

The rectified output currents 1,, 12,..., In are added to one another through the connection line 9 and the sum of them is outputted as an output current IRss, at the output terminal 10, where Irs51 is defined as IRSS1 = I1 + 12 + -. - + In. The output current IRss, has a characteristic as shown in Fig. 7 with respect to the input voltage Vi. It is seen f rom, Fig. 7 that the output current IRss, has a pseudo logarithmic characteristic with respect to the input voltage Vi.

As described above, since the voltage gain of each of the first to n-th amplifier-rectifier circuits S1 to Sn has no temperature dependence, the rectified output currents 1,, 12e... r I, of the circuits S1 to Sn are difficult to be affected by the ambient temperature. Thus, the temperature dependence of the output current IRss, of the logarithmic amplifier according to the first embodiment can be decreased.

Moreover, the rectified output currents 1,, 12,..., I, of the amplifierrectifier circuits S1 to Sn will vary according to the change of the control voltages Vcj to Vc, applied to the gate of the MOSFETs M7 in the triple-tail cells 5 in each of the circuits S1 to Sn, respectively. Specifically, if the control voltages Vcj to Vc, are set as high, the rectified output currents 11, 12j,..., In increase. On the contrary, if the control voltages Vcl to Vcn are set as low, the rectified output currents 1,, 12,...

In decrease.

1 With the logarithmic characteristic of the output current Ip.ss, of the logarithmic amplifier, the dynamic range of the logarithmic characteristic of the rectified output current I,, 12,..., or I, at each stage is 'determined by the voltage ga of the corresponding triple-tail cell 5, thereby changing the superposition state among the rectified output currents I,, 12,..., and In. Accordingly, by suitably setting or adjusting the control voltages Vcj to Vc,, the logarithmic accuracy and the inclination angle of the logarithmic characteristic of the logarithmic amplifier can be readily adjusted.

Additionally, as seen from the above equation (27c), the rectified output current I, of the triple-tail cell 5 in the first amplifier-rectifier circuit S1 has a square-law characteristic. Therefore, when the input voltage Vi is expressed in dB, the operating dynamic range is as narrow as approximately 6 to 8 dB.

As a result, the product of the voltage gains of MOS dif f erential pair 4 and the MOS triple-tail cell 5 in each of the first to n-th amplifier-rectifier circuits S1 to Sn is equal to the total voltage gain per stage.

For example, the value of (K2wK4/K1 2) may be set as approximately 4 to 6.

SECOND EMBODIMENT Figs. 8 and 9 show a logarithmic amplifier according to a second embodiment of the present invention.

The logarithmic amplifier according to the second embodiment has the same configuration as that of the first embodiment shown in Figs. 2 and 3 except that a MOS quadritail cell 5A is used instead of the triple-tail cell 5 in each stage. Therefore, explanation about the same configuration is omitted here by attaching the same reference symbols as those of Figs. 2 and 3 to the same elements in Figs. 8 and 9.

Since the MOSFET M7 of the triple-tail cell 5 of the first amplif ierrectif ier circuit S1 shown in Fig. 3 has the ratio (W/L) which is twice as large as that of a unit MOSFET (i.e., K3 = 2), the MOSFET M7 can be divided into two unit MOSFETs M7A and M7B whose sources, drains, and gates are coupled together. Therefore, the triple-tail cell 5 can be changed to the quadritail cell 5A, as shown in Fig. 9.

The quadritail cell 5A formed by the four MOSFETs M5, M6, M7A, and M7B is equivalent ih operation to the triple-tail cell 5 of Fig. 3. Accordingly, like the first embodiment shown in Fig. 2, the rectified output currents 1,, 12,..., and In Of the first to n-th amplifier- rectifier circuits S1 to Sn are added to one another through the connection line 9, thereby outputting the rectified output current IRss, with a logarithmic characteristic at the output terminal 10. In this embodiment also, the temperature characteristic or dependence of the rectified output current IRss, is decreased.

Also, by suitably setting or adjusting the control voltages Vcj to Vc,, the logarithmic accuracy and the inclination angle of the logarithmic characteristic of the logarithmic amplifier can be readily adjusted.

Fig. 10 shows the calculated drain current characteristics of the MOSFETs M5, M6, M7A, and M7B of the quadritail cell 5A used in the logarithmic amplifier according to the second embodiment of Figs. 8 and 9. It is seen from the curves cl, c2, and c3 that all the drain currents IDS, ID6, ID.7A, and ID7B have a square-law characteristic. It is seen from the curve c4 that the sum of the drain currents ID7A and ID7B have a square-law characteristic. It is seen from the curve c5 that the sum of the drain currents ID5 and ID7A have a linear characteristic. It is seen from the curve c6 that the sum of the drain currents ID6 and ID7B have a linear characteristic. THIRD EMBODIMENT Fig. 11 shows a logarithmic amplifier according to a third embodiment of the present invention.

The logarithmic amplifier according to the third embodiment comprises first to n-th amplifier-rectifier circuits S1 to Sn ca s cade -connected, similar to the first embodiment. Since the first amplif ier-rectif ier circuit S1 is the same as that of the first embodiment, explanation about the circuit S1 is omitted here by attaching the same reference symbols as those of Figs. 2 and 3 to the same elements in Fig. 11.

On the other hand, each of the second to n-th amplifier-rectifier circuits S2 to Sn has a configuration obtained by removing the MOS differential pair 4 in that of the first embodiment, respectively.

Specifically, the second amplifier-rectifier circuit S2 is comprised of a triple-tail cell 15 formed by source-coupled nchannel MOSFETs M15, M16, and M17. Sources of the MOSFETs M15, M16, and M17 forming the triple-tail cell 15 are connected to the ground through a constant current sink 13 (current value: 102).

The triple-tail cell 15 is driven by the constant current 102 generated by the constant current sink 13. The constant current 102 is a tail current.

Gates of the MOSFETs M15 and M16, which are respectively connected to the drains of the MOSFETs M5 and M6, constitute an input terminal pair of the triple-tail cell 15, i.e., an input terminal pair of the second amplifier-rectifier circuit S2.

Drains of the MOSFETs M15 and M16 constitute an amplified output terminal pair of the circuit S2.

The output voltage of the first amplifier-rectifier circuit S1 is applied to the gates of the MOSFETs M15 and M16.

A gate of the MOSFET M17 is applied with a dc constant voltage, i.e., a control voltage VC2. A drain of the MOSFET M17 forms third output terminal (i.e., a rectif ied-signal output terminal) 1 of the arnplifier-rectifier circuit S2, from which a rectified output current 12 of the circuit S2 is derived.

The MOSFETs M15 and M16 have the same ratio (W/L), which is K, times as large as that of a unit MOSFET. The MOSFET M17 has a ratio (W/L), which is K3 times as large as that of a unit MOSFET.

An n-channel MOSFET M20 and a constant current sink 12 (current value: Issl/2) constitute a control voltage generator for generating the control voltage VC2 to be applied to the gate of the MOSFET M17. A gate of the MOSFET M20 is applied with the same bias voltage VB as that commonly applied to the gates of the MOSFETs M13 and M14. A drain of the MOSFET M20 is connected to the supply voltage line Of VDD. A source of the MOSFET M20 is connected to one terminal of the constant current sink 12.

The control voltage VC2 is equal to the source voltage of the MOSFET M20. In other words, the control voltage VC2 is generated at the source of the MOSFET M20. The gate of the MOSFET M17 of the triple-tail cell 15 is connected to the source of the MOSFET M20.

In the second amplifier-rectifier circuit S2, the triple-tail cell 15 serves as a differential amplifier circuit having an approximately linear characteristic with respect to the input voltage, forming a differential output voltage approximately proportional to the input voltage between the drains of the MOSFETs M15 and M16.

The linearity of the differential amplifier circuit or the amplif ierrectif ier circuit S2 is degraded compared with the first amplifierrectifier circuit S1 comprising the MOS differential pair 4 and the triple-tail cell 5. However, the 112 voltage gain is (K,1K,). In this case also, the voltage gain does not contain the tail current 10, t rans conductance parameter P, and the load resistor RL, which means that the voltage gain of the amplifier-rectifier circuit S2 contains no temperature 10 dependence.

On the other hand, a current proportional to the square of the input voltage of the triple-tail cell 15 flow through the drain of the MOSFET M17 of the triple-tail cell 15. The drain current of the MOSFET M17 is derived as an output current 12 Of 15 the second amplifier-rectifier circuit S2.

Each of the third to n-th amplifier-rectifier circuits S3 to Sn has the same configuration as that of the second amplifier-rectifier circuit S2. Similar to the second amplifier-rectifier circuit S2, rectified output currents 13 to 1, are derived f rom the third to n-th amplif ier-rectif ier circuits S3 to Sn, respectively. Rectified output currents 13 to I, are derived from the first to n-th amplifier-rectifier circuits S1 to Sn, respectively.

The currents I, to I, of the first to n-th amplifierrectifier circuits S1 to Sn are added to one anther through the connection line 9 to thereby produce the output current IRss, having a logarithmic characteristic with respect to the input voltage 5 Vi at the output terminal 10.

The voltage gains of the first to n-th amplifierrectifier circuits S1 to Sn do not have any temperature characteristic and therefore, the currents I, to I. are not affected by the ambient temperature. Thus, the temperature dependence of the output current IRss, of the logarithmic amplifier according to the third embodiment of Fig. 11 is decreased.

The currents I, to I,, are changed by changing the control voltages Vcj to Vc,, to be applied to the triple-tail cells 5 and 15. Thus, by suitably setting or adjusting the control voltages Vcj to Vc,, the logarithmic accuracy and the inclination angle of the logarithmic characteristic of the logarithmic amplifier according to the third embodiment can be readily adjusted.

FOURTH EMBODIMENT Fig. 12 shows a logarithmic amplifier according to a fourth embodiment of the present invention.

The logarithmic amplifier according to the fourth embodiment has the same configuration as that of the third embodiment shown in Fig. 11 except that a MOS quadritail cell 5A is used instead of the triple-tail cell 5 in each stage. Therefore, explanation about the same configuration is omitted here by attaching the same reference symbols as those of Fig. 11 to the same elements in Fig. 12.

Since the MOSFET M7 of the triple-tail cell 5 of the f irst amplifier-rectifier circuit S1 shown in Fig. 11 has the ratio (W/L) which is twice as large as that of a unit MOSFET (i.e., K3 - 2), the MOSFET M7 can be divided into two unit MOSFETs M7A and M7B whose sources, drains, and gates are coupled together. Therefore, the triple-tail cell 5 can be changed to the quadritail cell 5A without operation change, as shown in Fig. 12.

The quadritail cell 5A formed by the four MOSFETs M5, M6, M7A, and M7B is equivalent in operation to the triple-tail cell 5 and the quadritail cell 15A formed by the four MOSFETs M15, M16, M17A, and M17B is equivalent in operation to the quadritail cell 5A. Accordingly, like the first embodiment shown in Fig. 2, the rectif ied output currents 1,, 12,..., and I,, of the first to nth amplifier- rectifier circuits S1 to Sn are added to one another through the connection line 9, thereby outputting the logarithmically-amplified output current IRSS, at the output terminal 10. In this embodiment also, the temperature characteristic of the output current IRSSI is decreased.

Also, by suitably setting or adjusting the control voltages Vcj to Vc, applied to the quadritail cells 5A and 15A in the first to n-th amplifierrectifier circuits S1 to Sn, the logarithmic accuracy and the inclination angle of the logarithmic characteristic of the logarithmic amplifier can be readily adjusted.

FIFTH EMBODIMENT Fig. 13 shows a logarithmic amplifier according to a f if th embodiment of the present invention.

The logarithmic amplifier according to the fifth embodiment has the same configuration as that of the third embodiment shown in Fig. 11, except that the control voltages VC2 to Vcn are equal to one another and produced by the only control voltage generator circuit for the control voltage VC2.

There is an additional advantage that the circuit configuration is simplified in the fifth embodiment.

While the preferred forms of the present invention have been described, it is to be understood that modifications will be apparent to those skilled in the art without departing from the scope of the invention. The scope of the invention, therefore, is to be determined solely by the following claims.

Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.

Statements in this specification of the "objects of the invention,' relate to preferred embodiments of the invention, but not necessarily to all embodiments of the invention falling within the claims.

* The description of the invention with reference to the drawings is by way of example only.

The text of the abstract filed herewith is repeated here as part of the specification.

A logarithmic amplifier that makes it possible to decrease the temperature dependence of an output signal. This amplifier comprises cascade -connected amplifier-rectifier circuits located at first to n-th stages. Each of the amplifier-rectifier circuits is comprised of a MOS differential pair formed by first and second MOSFETs, third and fourth MOSFETs serving respectively as loads of the first and second MOSFETs, a triple-tail cell formed by sources-coupled fifth, sixth, and seventh MOSFETs driven by a tail current, and eighth and ninth MOSFETs serving respectively as loads of the fifth and sixth MOSFETs. A first constant voltage is commonly applied to gates of the third and fourth MOSFETs. A differential voltage generated between drains of the first and second MOSFETs is applied across drains of the fifth and sixth MOSFETs. A second constant voltage is commonly applied to gates of the eighth and ninth MOSFETs. Gates of the first and second MOSFETs constitute the input terminal pair of a corresponding one of the amplifier-rectifier circuits. Drains of the fifth and sixth MOSFETs constitute the amplified output terminal pair of a corresponding one of the amplifier-rectifier circuits. A drain of the seventh MOSFET constitutes the rectified output terminal of a corresponding one of the amplifier-rectifier circuits.

Claims

CLAIMS: 1. A logarithmic amplifier comprising: cascade -connected amplifierrectifier circuits located at first to n-th stages, where n is an integer equal to or greater than two; each of said amplifier-rectifier circuits receiving an input signal and producing an amplified output signal and a rectified output signal; an initial input signal to be amplified being used as the input signal to said amplifier-rectifier circuit at said first stage; said amplified output signals from said amplifier rectifier circuits located at said f irst to (n - 1) -th stages being used as said input signals to said amplifier-rectifier circuits at said second to n-th stages, respectively; said rectified output signals from said amplifier rectifier circuits located at said first to n-th stages being added to one another to produce an output signal of said logarithmic amplifier; said output signal of said logarithmic amplifier being a logarithmically amplified signal of said initial input signal; each of said amplif ier-rectif ier circuits located at said first to n-th stages being comprised of a MOS differential pair formed by first and second MOSFETs; third and fourth MOSFETs serving respectively as loads of said first and second MOSFETs; a triple- tail cell formed by source-coupled fifth, sixth, and seventh MOSFETs driven by a single tail current; and eighth and ninth MOSFETs serving respectively as loads of said fifth and sixth MOSFETs; a first constant voltage being commonly applied to gates of said third and fourth MOSFETs; a differential voltage generated between drains of said f irst and second MOSFETs of said MOS differential pair being applied across drains of said fifth and sixth MOSFETs of said triple-tail cell; a second constant voltage being commonly applied to gates of said eighth and ninth MOSFETs; and gates of said first and second MOSFETs of said MOS differential pair constituting an input terminal pair of a corresponding one of said amplifier-rectifier circuits located at said first to n-th stages; drains of said fifth and sixth MOSFETs of said triple-tail cell constituting an amplif ied-signal output terminal pair of said corresponding one of said amplifier-rectifier circuits located at said first to n-th stages; a drain of said seventh MOSFET of said triple-tail cell constituting a rectified-signal output terminal of said corresponding one of said amplifier-rectifier circuits located at said first to n-th stages.

1 1 1 i

2. The amplifier as claimed in claim lt wherein said gate of said seventh MOSFET is applied with a third constant voltage in each of said amplif ier-rectif ier circuits at said first to n-th stages.

3. The amplifier as claimed in claim 1, wherein said gate of said seventh MOSFET is applied with a third constant voltage in each of said amplif ier-rectif ier circuits at said f irst to n-th stages, and at least one of said third constant voltages in said amplifier-rectifier circuits at said first to n-th stages is changeable, thereby making the logarithmic characteristic of said output signal of said logarithmic amplifier adjustable.

4. A logarithmic amplifier comprising: cascade-connected amplifierrectifier circuits located at first to n-th stages, where n is an integer equal to or greater than two; each of said amplif ier-rectif ier circuits receiving an input signal and producing an amplified output signal and a rectified output signal; an initial input signal to be amplified being used as said input signal to said amplifier-rectifier circuit at said first stage; said amplified output signals from said amplifierrectifier circuits located at said f irst to (n 1) -th stages being i used as said input signals to said amplifier-rectifier circuits at said second to n-th stages, respectively; said rectified output signals from said amplifierrectifier circuits located at said first to n-th stages being added to one another to produce an output signal of said logarithmic amplifier; said output signal of said logarithmic amplifier being a logarithmically amplified signal of said initial input signal; each of said amplif ier-rectif ier circuits located at said first to n-th stages being comprised of a MOS differential pair formed by first and second MOSFETs; third and fourth MOSFETs serving respectively as loads of said first and second MOSFETs; a quadritail cell formed by source-coupled fifth, sixth, seventh, and eighth MOSFETs driven by a single tail current; and ninth and tenth MOSFETs serving respectively as loads of said fifth and sixth MOSFETs; a first constant voltage being commonly applied to gates of said third and fourth MOSFETs; a differential voltage generated between drains of said first and second MOSFETs of said MOS differential pair being applied across drains of said fifth and sixth MOSFETs of said quadritail cell; a second constant voltage being commonly applied to gates of said ninth and tenth MOSFETs; and gates of said f irst and second MOSFETs of said MOS differential pair constituting an input terminal pair of a corresponding one of said amplifier-rectifier circuits located at said f irst to n-th stages; drains of said f if th and sixth MOSFETs of said quadritail cell constituting an amplif ied- signal output terminal pair of said corresponding one of said amplifierrectifier circuits located at said first to n-th stages; coupled drains of said seventh and eighth MOSFETs of said quadritail cell constituting a rectified-signal output terminal of said corresponding one of said amplifier-rectifier circuits located at said first to n-th stages.

5. The amplifier as claimed in claim 4, wherein said gates of said seventh and eighth MOSFETs are commonly applied with a third constant voltage in each of said amplif ier-rectif ier circuits at said first to n- th stages.

6. The amplifier as claimed in claim 4, wherein said gates of said seventh and eighth MOSFETs are commonly applied with a third constant voltage in each of said amplif ier-rectif ier circuits at said first to n-th stages, and at least one of said third constant voltages in said amplifier-rectifier circuits at said first to n-th stages is changeable, thereby making the logarithmic characteristic of said output signal of said logarithmic amplifier adjustable.

7. A logarithmic amplifier comprising: cascade-connected amplifierrectifier circuits located at first to n-th stages, where n is an integer equal to or greater than two; each of said amplifier-rectifier circuits receiving an input signal and producing an amplified output signal and a rectified output signal; an initial input signal to be amplified being used as said input signal to said amplifier-rectifier circuit at said first stage; said amplified output signals from said amplifier rectifier circuits located at said first to (n - 1) -th stages being used as said input signals to said amplif ier-rectif ier circuits at said second to n-th stages, respectively; said rectified output signals from said amplifier rectifier circuits located at said first to n-th stages are added to one another to produce an output signal of said logarithmic amplifier; said output signal of said logarithmic amplifier being a logarithmically amplified signal of said initial input signal; said amplifier-rectifier circuit located at said first stage being comprised of a first MOS differential pair formed by first and second MOSFETs; third and fourth MOSFETs serving respectively as loads of said first and second MOSFETs; a first triple-tail cell formed by source-coupled fifth, sixth, and seventh MOSFETs driven by a single tail current; and eighth and ninth MOSFETs serving respectively as loads of said fifth and sixth MOSFETs; a first constant voltage being commonly applied to gates of said third and fourth MOSFETs; a differential voltage generated between drains of said first and second MOSFETs of said first MOS differential pair being applied across drains of said fifth and sixth MOSFETs of said f irst triple-tail cell; a second constant voltage being commonly applied to gates of said eighth and ninth MOSFETs; and gates of said first and second MOSFETs of said first MOS differential pair constituting an input terminal pair of said amplifier-rectifier circuits located at said first stage; drains of said fifth and sixth MOSFETs of said first triple-tail cell constituting an amplified-signal output terminal pair of said amplifier- rectifier circuit located at said first stage; a drain of said seventh MOSFET of said f irst triple-tail cell constituting a rectified-signal output terminal of said amplifier-rectifier circuit located at said first stage; each of said amplif ier-rectif ier circuits located at said second to n-th stages being comprised of a second triple-tail cell formed by source-coupled tenth, eleventh, and twelfth MOSFETs driven by a single tail current; and thirteenth and fourteenth MOSFETs serving respectively as loads of said tenth and eleventh MOSFETs; a third constant voltage being commonly applied to gates of said thirteenth and fourteenth MOSFETs; and gates of said tenth and eleventh MOSFETs of said second triple-tail cell constituting an input terminal pair of a corresponding one of said amplifier-rectifier circuits located at said second to n-th stages; drains of said tenth and eleventh MOSFETs of said second triple-tail cell constituting an amplif ied-signal output terminal pair of said corresponding one of said amplifier-rectifier circuits located at said second to n-th stages; a drain of said twelfth MOSFET of said second triple-tail cell constituting a rectif ied-signal output terminal of said corresponding one of said amplifier-rectifier circuits located at said second to n-th stages.

8. The amplifier as claimed in claim 7, wherein said gate of said seventh MOSFET in said amplif ier-rectif ier circuit at said first stage is applied with a fourth constant voltage, and said twelfth MOSFET in each of said amplif ier-rectif ier circuits at said second to n-th stages is applied with a fifth constant voltage.

9. The amplifier as claimed in claim 7, wherein said gate of said seventh MOSFET in said amplifier-rectifier circuit at said first stage is applied with a fourth constant voltage, and said twelfth MOSFET in each of said amplif ier-rectif ier circuits at said second to n- th stages is applied with a fifth constant voltage; and wherein at least one of said fourth and f if th constant voltages is changeable, thereby making the logarithmic characteristic of said output signal of said logarithmic amplifier adjustable.

10. A logarithmic amplifier comprising: cascade-connected amplifierrectifier circuits located at first to n-th stages, where n is an integer equal to or greater than two; each of said amplif ier-rectif ier circuits receiving an input signal and producing an amplified output signal and a rectified output signal; an initial input signal to be amplified being used as said input signal to said amplifier-rectifier circuit at said first stage; said amplified output signals from said amplifier rectifier circuits located at said f irst to (n - 1) -th stages being used as said input signals to said amplifier-rectifier circuits at said second to n-th stages, respectively; said rectified output signals from said amplifierrectifier circuits located at said first to n-th stages being added to one another to produce an output signal of said logarithmic amplifier; said output signal of said logarithmic amplifier being a logarithmically amplified signal of said initial input signal; said amplifier-rectifier circuit located at said first stage being comprised of a f irst MOS dif f erential pair f ormed by first and second MOSFETs; third and fourth MOSFETs serving respectively as loads of said first and second MOSFETs; a first quadritail cell formed by source-coupled f if th, sixth, seventh, and eighth MOSFETs driven by a single tail current; and ninth and tenth MOSFETs serving respectively as loads of said fifth and sixth MOSFETs; a first constant voltage being commonly applied to gates of said third and fourth MOSFETs; a dif f erential voltage generated between drains of said first and second MOSFETs of said first MOS differential pair being applied across drains of said fifth and sixth MOSFETs of said first quadritail cell; a second constant voltage being commonly applied to gates of said ninth and tenth MOSFETs; gates of said first and second MOSFETs of said first MOS differential pair constituting an input terminal pair of said amplif ier-rectif ier circuits located at said first stage; drains of said fifth and sixth MOSFETs of said first quadritail cell constituting an amplified-signal output terminal pair of said amplifier-rectifier circuit located at said first stage; coupled drains of said seventh and eighth MOSFETs of said f irst quadritail cell constituting a rectified-signal output terminal of said amplifier-rectifier circuit located at said first stage; each of said amplif ier-rectif ier circuits located at said second to n- th stages being comprised of a second quadritail cell formed by source-coupled eleventh, twelfth, thirteenth, and fourteenth MOSFETs driven by a single tail current; and fifteenth and sixteenth MOSFETs serving respectively as loads of said eleventh and twelfth MOSFETs; a third constant voltage being commonly applied to gates of said thirteenth and fourteenth MOSFETs; and gates of said eleventh and twelfth MOSFETs of said second quadritail cell constituting an input terminal pair of a corresponding one of said amplifier-rectifier circuits located at said second to n-th stages; drains of said eleventh and twelfth and MOSFETs of said second triple-tail cell constituting an amplified- signal output terminal pair of said corresponding one of said amplifier- rectifier circuits located at said second to n-th stages; coupled drains of said thirteenth and fourteenth MOSFETs of said second quadritail cell constituting a rectified-signal output terminal of said corresponding one of said amplif ier-rectif ier circuits located at said second to n-th stages.

11. The amplifier as claimed in claim 10, wherein said gates of said seventh and eighth MOSFETs are commonly applied with a fourth constant voltage in said amplifier-rectifier circuit at said first stage, and said gates of said thirteenth and fourteenth MOSFETs are commonly applied with a f if th constant voltage in each of said amplifier-rectifier circuits at said second to n-th stages.

12. The amplifier as claimed in claim 10, wherein said gates of said seventh and eighth MOSFETs are commonly applied with a fourth constant voltage in said amplifier-rectifier circuit at said first stage, and said gates of said thirteenth and fourteenth MOSFETs are commonly applied with a f if th constant voltage in each of said amplifier- rectifier circuits at said second to n-th stages; and wherein at least one of said third and f ourth constant voltages in said amplifier-rectifier circuits at said first to n-th stages is changeable, thereby making the logarithmic characteristic of said output signal of said logarithmic amplifier adjustable.

13. A method of operating a logarithmic amplifier, said amplifier comprising cascade-connected amplifier-rectified circuits located at first to n-th stages, where n is an integer greater than one, each of said amplifier-rectified circuits comprising a MOS differential pair formed by first and second MOSFETs; third and fourth MOSFETs serving as respective loads of the first and second MOSFETs; a tripletail cell formed by source-coupled fifth, sixth and seventh MOSFETs driven by a single tail current; and eighth and ninth MOSFETs serving respectively as loads of the fifth and sixth MOSFETs, gates of the first and second MOSFETs of said MOS differential pair constituting an input terminal pair of a corresponding one of said amplif ier-rectif ier circuits located at said first to n-th stages, drains of each fifth and sixth is MOSFETs constituting an amplif ied- signal output pair of a corresponding one of said amplifier- rect if ier circuits located at said f irst to n-th stages; and a drain of each seventh MOSPET constituting a rectified-signal output terminal of a corresponding one of said amplif ier-rectif ier circuits located at said first to n-th stages, said method comprising the steps of:- inputting an input signal to the amplifier-rectifier circuit at said first stage; using amplified output signals from said amplifier rectifier circuits located at said first to (n-1)-th stages as input signals to said amplif ier-rectif ier circuits at said second to n-th stages respectively; adding rectified output signals from said amplifier-83- rectifier circuits located at said first to nth stages to produce an output signal of said logarithmic amplifier, said output signal being a logarithmically amplified signal of said input signal; 5 applying a first constant voltage commonly to gates of said third and fourth MOSFETs to generate a differential voltage between drains of said first and second MOSFETs of said MOS differential pair; applying the differential voltage across drains of the fifth and sixth MOSFETs of the triple-tail cell; and applying a second constant voltage commonly to gates of the eighth and ninth MOSFETs.

14. A method of operating a logarithmic amplifier, said is amplifier comprising cascade-connected amplifier-rectified circuits located at first to n-th stages, where n is an integer greater than one, each of said amplifier-rectified circuits comprising a MOS differential pair formed by first and second MOSFETs; third and fourth MOSFETs serving as respective loads of the first and second MOSFETs; a quadritail cell formed by sourcecoupled f if th, sixth, seventh and eighth MOSFETs driven by a single tail current; and ninth and tenth MOSFETs serving respectively as loads of the fifth and sixth MOSFETs, gates of the first and second MOSFETs of said MOS differential pair constituting an input terminal pair of a corresponding one of said amplif ier-rectif ier circuits located at said first to n-th stages, drains of each fifth and sixth MOSFETs constituting an amplif ied- signal output pair of a corresponding one of said amplif ier-rectif ier circuits located at said f irst to n-th stages; and coupled drains of each seventh and eighth MOSFETs constituting a rectif ied-signal output terminal of a corresponding one of said amplifiers rectifier circuits located at said first to n-th stages, said method comprising the steps of:inputting an input signal to the amplifier-rectifier circuit at said first stage; using amplified output signals from said amplifier- rectifier circuits located at said first to (n-1)-th stages as input signals to said amplif ier-rectif ier circuits at said second to n-th stages respectively; adding rectified output signals from said amplifier rectifier circuits located at said first to n-th stages to is produce an output signal of said logarithmic amplifier, said output signal being a logarithmically amplified signal of said input signal; applying a first constant voltage commonly to gates of said third and fourth MOSFETs to generate a differential voltage between drains of said first and second MOSFETs of said MOS differential pair; applying the differential voltage across drains of the fifth and sixth MOSFETs of the quadritail cell; and applying a second constant voltage commonly to gates of the ninth and tenth MOSFETs.

15. A method of operating a logarithmic amplifier, said amplifier comprising cascade-connected amplifier-rectified -85- circuits located at f irst to n-th stages, where n is an integer greater than one, the amplif ier-rectif ied circuits located at the first stage comprising a MOS differential pair formed by first and second MOSFETs; third and fourth MOSFETs serving as respective loads of the first and second MOSFETs, a f irst triple-tail cell f ormed by source-coupled f if th, sixth and seventh MOSFETs driven by a single tail current, and eighth and ninth MOSFETs serving respectively as loads of the f if th and sixth MOSPETs, gates of the first and second MOSFETs of said MOS differential pair constituting an input terminal pair of the amplifier-rectified circuit at said first stage, drains of the fifth and sixth MOSFETs constituting an amplified-signal output pair of the amplifier-rectified circuit located at said f irst stage; and a drain of the is seventh MOSFET constituting a rectified-signal output terminal of the amplifier-rectifier circuit located at said first stage, each of the amplifier-rectified circuit located at the second to n-th stages comprising a second triple-tail cell formed by source-coupled tenth, eleventh and twelfth MOSFETs driven by a single tail current, and thirteenth and fourteenth MOSFETs serving respectively as loads of the tenth and eleventh MOSFETs, gates of the tenth and eleventh MOSFETs constituting an input terminal pair of a corresponding one of the amplif ier-rectif ied circuits located at the second to n-th stages, drains of the tenth and eleventh MOSFETs constituting an amplif ied- signal output terminal pair of the corresponding one of the amplifier-rectified circuits located at the second to n-th stages, and a drain of the twelfth MOSFET constituting a rectified-signal output terminal of the corresponding one of the amplifier-rectified circuits located at the second to n-th stages, said method comprising the steps of:inputting an input signal to the amplifierrectifier circuit at said first stage; using amplified output signals from said amplifierrectifier circuits located at said first to (n-1)-th stages as input signals to said amplifier-rectifier circuits at said second to n-th stages respectively; adding rectified output signals from said amplifier rectifier circuits located at said first to n-th stages to produce an output signal of said logarithmic amplifier, said output signal being a logarithmically amplified signal of said input signal; applying a first constant voltage commonly to gates of said third and fourth MOSFETs to generate a differential voltage between drains of said first and second MOSPETs of said MOS differential pair; applying the differential voltage across drains of the fifth and sixth MOSFETs of the triple-tail cell; applying a second constant voltage commonly to gates of the eighth and ninth MOSFETs; and applying a third constant voltage commonly to gates of the thirteenth and fourteenth MOSFETs.

16. A method of operating a logarithmic amplifier, said amplifier comprising cascade-connected amplifier-rectified -87 circuits located at first to n-th stages, where n is an integer greater than one, the amplifier-rectified circuits located at the first stage comprising a MOS differential pair formed by first and second MOSFETs; third and fourth MOSPETs serving as respective loads of the first and second MOSFETs; a first quadritail cell formed by source-coupled fifth, sixth, seventh and eighth MOSFETs driven by a single tail current; and ninth and tenth MOSFETs serving respectively as loads of the fifth and sixth MOSFETs, gates of the first and second MOSFETs of said MOS differential pair constituting an input terminal pair of the amplifier-rectified circuit located at said first stage, drains of the fifth and sixth MOSFETs constituting an amplif ied-signal output pair of the amplif iedrectified circuit located at said first stage; and coupled is drains of the seventh and eighth MOSFETs constituting a rectified- signal output terminal of the amplifier-rectified circuit located at said first stage, each of the amplifierrectified circuit located at the second to n-th stages comprising a second quadritail cell formed by source- coupled eleventh, twelfth, thirteenth and fourteenth MOSFETs driven by a single tail current, and fifteenth and sixteenth MOSFETs serving respectively as loads of the eleventh and twelfth MOSFETs, gates of the eleventh and twelfth MOSFETs constituting an input terminal pair of a corresponding one of the amplifier-rectifier circuits located at the second to n-th stages, drains of the eleventh and twelfth MOSFETs constituting an amplified-signal output terminal pair of the corresponding one of the amplif ier-rectif ier circuits located at the second to n-th stages, and coupled drains of the thirteenth and fourteenth MOSFETs constituting a rectifiedsignal output terminal of the corresponding one of the amplifier-rectifier circuits located at the second to n-th stages, said method comprising the steps of:inputting an input signal to the amplifier-rectifier circuit at said first stage; using amplified output signals from said amplifier- rectifier circuits located at said first to (n-1)-th stages as input signals to said amplifier-rectifier circuits at said second to n-th stages respectively; adding rectified output signals from said amplifier rectifier circuits located at said first to n-th stages to is produce an output signal of the logarithmic amplifier, said output signal being a logarithmically amplified signal of said input signal; applying a first constant voltage commonly to gates of said third and fourth MOSFETs to generate a differential voltage between drains of said first and second MOSFETs of said MOS differential pair; applying the differential voltage across drains of the fifth and sixth MOSFETs of the quadritail cell; applying a second constant voltage commonly to gates of the eighth and ninth MOSFETs: and applying a third constant voltage commonly to gates of the thirteenth and fourteenth MOSPETs.

17. A logarithmic amplifier or a method of operating a logarithmic amplifier substantially as herein described with reference to any of Figures 2, 8, 11, 12 and 13 of the accompanying drawings.

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