JPS6324377A - Squaring circuit - Google Patents

Abstract

PURPOSE:To obtain a squaring circuit suitable for MOSIC by connecting two differential pairs consisting of MOSFET different in ratio of gate width to gate length W/L with the drain of FET of the same W/L, and connecting so as to make output opposite phase to each other. CONSTITUTION:The first and second differential pairs 1, 2 consisting of two MOSFET M11, M1k and M21, M2k in which W/L is 1:k (k is positive integer except 1) are provided. The first and the second output liens 3, 4 are connected to a common connection point of MOSFET of the same W/L that constitute differential pairs 1, 2. A pair of input terminal 5-1, 5-2 are connected respectively to a common connection point of gates of MOSFET M11, M2k and M1k, M21 of different W/L. Current that is conducted in output liens 3, 4 is taken out and the difference is taken by a subtracter circuit 6. By this constitution, output including square term of input voltage DELTAVi can be obtained from the circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a squaring circuit, and particularly to a squaring circuit constructed of MOS transistors.

[Conventional technology]

Is the squaring circuit used in conventional rectifier circuits an analog multiplier? The one used is known.

[Problem that the invention seeks to solve]

The above-mentioned conventional squaring circuit is realized by a bipolar integrated circuit, and has the disadvantage that the circuit becomes extremely large in order to realize the entire squaring circuit with an MO8 type integrated circuit.

An object of the present invention is to provide a squaring circuit which is small in circuit scale and suitable for an i'vl OS type performance circuit.

[Means for solving problems]

Each uninvented square circuit has a gate width to gate length ratio W/
Two MOSs where L is 1:k (positive real number excluding k & X1)
The first transistor consists of a transistor. a second differential pair; and a second differential pair;
．． The first . a pair of input terminals respectively connected to a second output line and a common connection point between the gates of MOS transistors of different W/L; It includes a subtraction circuit that extracts the current flowing to the second output side and calculates the difference.

〔Example〕

Next, embodiments of the present invention will be described with reference to all the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

This embodiment consists of two MO8 transistors each having a gate width to gate length ratio W/L of 1:k (where k is a positive real number excluding 1). a second differential pair 1, 2;
1ili that constitutes the 20th differential pair 1 and 2]
The first . Connect the second output line 3.4 and the common connection point between the gates of MO8) synristors of different W/L? A pair of J'C input terminals 5
-1.5-2, and a subtraction circuit 6 which calculates the difference between the current flowing in the 1st and second output lines 3.4.

Next, solve the characteristics of this example.ff? go to

The drain currents of transistors Mu, Mtk, M21, and Mzk are expressed as I d+ , Idl, and Ias, respectively.
, Id4.

Cox W+ Idt =μn ding (Vgsx-Vt)...
(1) COX W2 Idz = μn2 (Vgsz −Vt)
・・t21Cox W+ Id3=μn 薯"(Low) (Vgs3-Vt)
...(3) COX W2 Id4=-μn-(-) (Vgs 4-Vt
)...(4)2 L2 However, μn is the electron mobility, COX is the gate capacitance, and W
is the gate width, LVi gate length, Vgs is the gate-source voltage, and vt is the threshold voltage.

k= (W2/L2)/(Wl/L+)...(6)
far.

Idl+Idz=Iss... (7
) Id3+Id+ = Ias... (8
) and Vgs l−Vgs2 = JVi 1−
(9) Vgsa −Vgss: JVi −1
(10).

If we set ΔId = Idl-Idz, (i+,) ΔIdn = Id4- Ias...(12), °, Δworkd= ΔIdl-ΔIdn(1+order)2...(13) Also, ΔId= Since (Id++Ids) - (Idz + Id<), the subtraction circuit 6 includes the square term of the input pressure ΔVi (
It can be seen that the output of equation 13) can be obtained.

)vlm s and Δ1mz are transistors on the primary side of the current mirror circuit.

When ΔVi=O is set in equation (13), FIG. 2 is a loading diagram showing the relationship between the constant term and k.

Since the coefficients of the constant term (ΔId)ΔVi=O and (Δy i)2 have opposite signs, looking at Figure 2 shows that the full dynamic range of the square circuit can be secured when k<1 or k>1. I understand.

Now, if k>1, for example, =3 and 1-1r, it is given as ΔId+Iss+−α(ΔV1−1(15)).

By adding Iss to equation (15), the offset can be made O after all. This can be easily achieved using a differential pair of constant current sources.

Further, in FIG. 2, when k>1, for example, 1 (=3, the slope of the curve becomes 0 with respect to the change in the value of k; -C becomes gentle, that is, there is little change in the characteristics due to the offset of the differential pair.

For reference, Equation (11) or (12) is considered to represent the characteristics of a conventional differential amplifier pair composed of bare transistors. In formula (11), ΔVi=
Q is the offset current due to the unevenness of the characteristics of the bare transistors, but as in equation (14), this shows a steep change around 1, so the offset current is due to the unevenness of the characteristics of the paired transistors. is found to be sensitive.

〔Effect of the invention〕

As explained above, the present invention provides a differential pair 21 consisting of two transistors with different W/L. There is an effect that can be realized in a squaring circuit consisting of MOS transistors with a simple 75-configuration in which all the drains of transistors of the same W/L are connected in common and the outputs are connected in opposite phases to each other.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a second embodiment of the present invention, and FIG. 2 is a characteristic diagram for explaining the characteristics of the squaring circuit of the embodiment. 1...First differential pair, 2...Second differential pair, 3...First output line, 4...Second Output line, 5~1゜5-2...Input terminal, 6
・・・・・・Subtraction circuit, bXll. Mzl, Mtk, Mzk-n MOS transistor, Mml, Mmz...mirror transistor. , l- Agent Patent Attorney Susumu Uchihara $ 7 Diagram 2 Diagram

Claims (1)

[Claims] The gate width to gate length ratio W/L is 1:k (k is 1
A first and second differential pair consisting of two MOS transistors (a positive real number excluding ) and a common connection between the drains of MOS transistors of the same W/L constituting the first and second differential pairs. a pair of input terminals each connected to a common connection point between the gates of MOS transistors of different W/L; A squaring circuit characterized by comprising a subtraction circuit that takes out flowing currents and calculates the difference.