JPS6228088Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a reference voltage circuit using an insulated gate field effect transistor (hereinafter referred to as MOS).

The object of the present invention is to provide a configuration that can be used as a simple reference voltage circuit in various analog circuits, a configuration that can coexist with MOS digital circuits, and a reference voltage circuit that can be manufactured by a process that can coexist.

Based on the above, the reference voltage source of the present invention has a two-power supply configuration of V _{DD -V g} -V SS where the power supply has _an intermediate voltage V _g between V _DD -V _SS with V _SS as a reference. It has a configuration that generates a reference voltage with respect to V _g or V _SS .

FIG. 1 shows a circuit that generates a reference voltage for V _g in a dual power supply configuration of V _DD -V _g -V _SS .
This reference voltage generates a voltage that is stable against power supply fluctuations and temperature fluctuations, and also that V _g is V _DD
Because of the requirement that a stable circuit configuration should be achieved even if the potential is not exactly midway between V _SS and V SS , the MOS transistor is characterized in that a difference in threshold voltage of the same polarity MOS is generated with respect to the intermediate potential V _g . N-channel transistors 1 and 2
are elements with exactly the same geometric dimensions and characteristics, so the current flowing through them is the same, so the gate-source voltages of both transistors are the same. In other words, the voltage at the connection point of transistors 1 and 2 is set to V ₁₀ with V _SS as the reference, and the difference between the two power supply voltages is V _DD −V _SS =V _d
d (based on V _SS ), the gate-source voltage of transistor 2 is V _dd −V ₁₀ .
On the other hand, since an intermediate voltage V _g is connected to the gate of transistor 1, the gate-source voltage is V _g .

Therefore, V _dd −V ₁₀ =V _g (1) Therefore, V ₁₀ is expressed by the following relational expression.

V ₁₀ = V _dd - V _g (2) Next, focusing on transistors 3 and 4, if the threshold voltage of transistor 3 is V _TN , then the effective gate voltage (gate voltage - threshold voltage) is V ₁₀ - V _TN . Further, when the threshold voltage of the transistor 4 is V _GTN , its effective gate voltage is V _dd -V ₁ -V _GPN , where the output voltage is V ₁ . The transistors 3 and 4 have the same conductance coefficient and are configured to differ only in threshold voltage, so the following equation holds true that the effective gate voltage is equal.

V ₁₀ −V _TN =V _dd −V ₁ −V _GTN (3) In other words, the output voltage V ₁ becomes V ₁ =V _TN −V _GTN +V _g (4) by substituting equation (2). This voltage is based on V _SS , and when the intermediate voltage V _g is used as a reference, the desired voltage V _TN -V _GTN is generated. V _TN −V _GTN is a constant voltage determined by the threshold voltage, and a reference voltage circuit that generates a constant voltage with the intermediate voltage V _g as a reference can be realized. Here, N-channel transistors with different threshold voltages are manufactured by ion implantation into the gate (channel doping).
In a normal C-MOS (complementary connected insulated gate transistor), a P ^- well is formed on a low concentration N ^- substrate to create an N ^- channel _transistor . A relatively high concentration can be produced by channel doping with donor ions such as 31P ⁺ to obtain V _GTN . At that time, if transistors 3 and 4 are made to have the same gate film thickness, approximately equal channel length, and channel width, transistors 3 and 4 can have approximately the same conductance coefficient and different threshold voltages, and also have temperature characteristics that are equal to the threshold voltage. The implantation amount with a net voltage shift is Nnet, the elementary charge is q, and the unit gate capacitance is Cox (Cox=EoEoc/
Tox), it can be considered that they are equivalent because they are given by qNnet/Cox, and it is safe to assume that they are equivalent if the conductance coefficient can be corrected experimentally and the channel width is slightly corrected. However, on the other hand, in a configuration in which the P ^- layer has a low concentration and a high threshold voltage is obtained by channel doping with acceptor ions, such as 11B ⁺ , the structure is sensitive, and the conductance coefficient and threshold voltage cannot be equalized by experimentally correcting them. It is difficult to do so, and the temperature characteristics are also quite different. Further, although the conductance coefficients can be made equal due to the geometrical dimensions of the structure in which the gate film thickness is controlled to be thicker at 3 and thinner at 4, this is also undesirable because the temperature characteristics of the threshold voltage depend on the gate film thickness. After all, the reference potential can be obtained with the configuration described at the beginning. Hereinafter, a transistor with a low threshold voltage due to such channel doping will be represented by a broken line at the gate as shown in FIG. In addition, the N-channel transistor used in this circuit is common in C-MOS, which is normally formed on an N ^- substrate, and the substrate N ^- of P channel transistors is common, and the substrate that can be floated from the power supply is P. ^- Because only. Furthermore, in order to match the characteristics of the first and second transistors, it is necessary to use a common substrate source that does not cause the body effect.

FIG. 2 shows a circuit that generates a reference voltage for V _SS in a dual power supply configuration of V _DD -V _g -V _SS . This circuit is a constant voltage reference voltage circuit that uses the V1 reference voltage shown in FIG. ₁ and outputs only the difference in threshold voltage, which is unrelated to _Vg , as the output voltage. To explain the operation, N channel transistors 5 and 7
By matching the ratio of the conductance coefficients of P channel transistors 6 and 8, the following voltage relationship is derived. That is, the connection point between transistors 5 and 6 is set to _V20 , the currents flowing through both transistors are equal, and therefore the effective gate voltages are also equal. The threshold voltage of transistors 5 and 7 is V _GTN , transistors 6 and 8
Letting the threshold voltage of V _TP be V TP , the effective gate voltage of transistor 5 is V ₁ -V _g -V _GTN , and the effective gate voltage of transistor 6 is V _dd -V ₂₀ -V _TP , so the following equation holds true.

V ₁ −V _g −V _GTN =V _dd −V ₂₀ −V _TP (5) Substituting equation (4) into V ₁ , the output voltage V ₂₀ is: V ₂₀ =V _dd −(V _TP +V _TN )+2V _GTN (6) becomes. Next, since the same current flows through transistors 7 and 8, the gate voltages are also the same, and the effective gate voltage of transistor 7 is V ₂ −V _GTN and the effective gate voltage of transistor 8 is V _dd −V ₂₀ −V _TP . The following formula holds.

V ₂ −V _GTN =V _dd −V ₂₀ −V _TP (7) When formula (6) is substituted for V ₂₀ , the output voltage V ₂ becomes V ₂ =V _TN −V _GTN (8), and V _g and A reference voltage circuit in which a constant voltage V _TN -V _GTN determined only by the threshold values V _TN and V _GTN , which are unrelated to each other, is generated based on V _SS has been realized.

As a matter of course, in C-MOS by selecting a P ^- substrate as the transistor substrate and configuring a P ^- well therein, the transformations from FIG. 1 to FIG. 3 and from FIG. 2 to FIG. 4 are realized. This changes from N, P channel transistor to P, N channel transistor,
Donor ions in Figures 1 and 2, for example 31P ⁺
Figures 3 and 4 show the channel doping at the gate of an N-channel transistor.
This is an alternative to doping the gate channel of a P channel transistor with ions such as 11B ⁺ . The normal threshold voltage of a P channel transistor is V. The threshold voltage due to _TP channel doping is V.
_GTP and change the potential at the connection point of transistors 9 and 10.
When V is ₃₀ , the following relational expression holds true as described above.

V _dd −V _g =V ₃₀ (9) Therefore, V ₃₀ =V _dd −V _g (10) Also, the next stage transistors 11 and 12 have the above relationship, and since they are P channel transistors, the sign of the threshold voltage is Since is the opposite, take the absolute value and the following formula holds true.

V ₃₀ − | V _TP | = V _dd −V ₃ − | V _GTP | (11) Therefore, by substituting equation (10), the output voltage V ₃ is: V ₃ = | V _TP | − | V _GTP | +V _g (12). That is, the same constant voltage power supply circuit as shown in FIG. 1 can be realized by using P channel transistors using the circuit shown in FIG. In Figure 2, the P-channel transistor and the N-channel transistor are simply replaced, so if we take the absolute value, we get V ₄ = |V _TP |-|V _GTP | (13), which corresponds to equation (8). , a reference voltage circuit related only to the threshold voltage unrelated to V _g has been realized. At this time, the channel
Since the arbitrariness of doping concerns only the difference in threshold voltage, there are several variations in FIGS. 1 to 4. For example, in Figure 1, channel doping is applied to both 1 and 2 (in this case, strictly speaking, the channel doping of 1 and 2 may be acceptor ions). 5 and 7 in Figure 2.
For example, 6 and 8 may be channel-doped with acceptor ions (in this case, 6 and 8 may also be donor ions).

It is also possible to extract the difference in threshold voltage from FIGS. 1 and 2 in the same manner as in FIGS. 5 and 6. In this circuit, the ratio of the conductance coefficients of N-channel transistors 17 and 19 and the conductance coefficient of P-channel transistors 18 and 20 are made to match, and the potential at the connection point of transistors 17 and 18 is set to V ₅₀ with respect to V _SS . Then, the following formula holds true using the same calculation formula as described above.

V ₅₀ =V _dd −V _g (14) V ₅₀ −V _TN =V _dd −V ₅ −|V _GTP | (15) Therefore, V ₅ =V _TN −|V _GTP |+V _g (16) holds. , when the intermediate voltage V _g is used as a reference, the difference between the threshold voltages V _TN -V _GTP can be taken as a stable reference voltage. In this case as well, in order to create products with different threshold voltages, it is necessary to use a relatively high concentration of N.
The substrate is then channel-doped with acceptor ions, such as 11B, to create transistors with low threshold voltages. Also 21, 23 N
Similarly, by matching the ratio of the conductance coefficients of the channel transistor to the ratio of the conductance coefficients of the P channel transistors 22 and 24,
Only the voltage related to the threshold voltage can be output from _V1 . That is, transistors 21 and 22
If the potential at the connection point with V ₆₀ is _{V 60} , then V ₅ −V _g −V _TN =V _{dd −V 60} −|V _{GTP |} (17 ₎ (18) Substituting equation (16) for V ₅ , from equations (17) and (18), V ₆ = V _TN − | V _GTP |, which is the output voltage simply related to V _TN and V _GTP . , V _SS as a reference voltage V _TN − | V _GT
P | can be generated.

With the above configuration, the intermediate voltage V _g or V _SS
Based on this, we have realized a reference voltage circuit that generates a reference voltage that depends only on the threshold voltage.

Such a reference voltage circuit with a difference in threshold voltage is used not only as a bias voltage for constant current source transistors of differential amplifiers and operational amplifiers, but also as a simple reference voltage for various analog circuits. .

Furthermore, with the recent rapid shift to MOS digital circuits, this reference voltage circuit can coexist with both MOS analog circuits and digital circuits without any process changes, and can also be used in the ion implantation process together with the digital part, eliminating process differences. do not have. Also, since this reference voltage circuit relies only on the difference in threshold voltage, if there is a double or triple ion implantation process, this reference voltage circuit can also use the difference in ion implantation, and together with the integer multiple circuit, the reference voltage can be adjusted to the desired value. It can take a wide range of values. or,
If this reference voltage circuit is inserted as a monitor during MOSIC manufacturing, it is possible to immediately measure the difference in threshold voltage, and hence the net dose of ions and the difference in dose.

[Brief explanation of the drawing]

1, 2, 3, 4, 5, and 6 are reference voltage circuits of the present invention. 1, 2, 3, 4, 5, 7, 10, 12, 14,
15, 17, 19, 21, 23, 25, 27, 2
8, 29, 30, 31, 32, and 33 are N-channel transistors. 6, 8, 9, 11, 13, 16,
18, 20, 22, 24, and 26 are P channel transistors. V _DD is the positive power supply voltage, V _SS is the negative power supply voltage, V _g is the intermediate voltage, V ₁ , V ₂ , V ₃ , V ₄ ,
V ₅ and V ₆ are reference voltages.

Claims (1)

[Scope of utility model registration request] The first MOS transistors 1, 18 and the second MOS transistor
MOS transistors 2 and 17 are connected in series between the first and second power supply voltages, third MOS transistors 3 and 19 and fourth MOS transistors 4 and 20.
are connected in series between the first and second power supply voltages,
the first MOS transistor and the fourth MOS
The transistors are of the same channel type, the second MOS transistor and the third MOS transistor.
The MOS transistors are of the same channel type, the first and second MOS transistors have equal conductance coefficients, and the third and fourth MOS transistors have equal conductance coefficients, and the first and second MOS transistors have equal conductance coefficients. A connection point between the MOS transistor and the second MOS transistor is connected to the gate of the third MOS transistor, the gate and drain of the second and fourth MOS transistors are short-circuited, and the connection point of the first MOS transistor is connected to the gate of the third MOS transistor. A third power supply voltage, which is an intermediate voltage between the first and second power supply voltages, is applied to the gate of the fourth MOS transistor, and the threshold of the fourth MOS transistor is made different from the threshold of the third MOS transistor. A reference voltage circuit characterized in that a difference in threshold voltage between the third and fourth MOS transistors is output from a connection point between the third and fourth MOS transistors as a reference voltage from the third power supply voltage.