JPH0119303B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog switch device using MOS field effect transistors.

An analog switch device is one that is turned on (conducting) by a clock signal that controls the device.
state or off (non-conducting) state,
It is a device in which input information, ie, an analog input signal, is transmitted to the output when it is in the on state, and no analog input signal is transmitted when it is in the off state.

FIG. 1 is a circuit diagram of a conventional analog switch device. This device consists of a source electrode S of an N-channel enhancement type MOS field effect transistor (hereinafter abbreviated as MOS transistor) 1 and a P-channel enhancement type MOS field effect transistor (hereinafter referred to as MOS transistor).
The drain electrode D of the transistor 2 is connected, and this connection point is connected to the supply terminal 3 of the analog input signal IN, and the drain electrode D of the MOS transistor 1 and the source electrode S of the MOS transistor 2 are connected.
and connect this connection point to the analog output signal.
Connect to OUT output terminal 4, and then
A clock signal φ is supplied to the gate electrode G of the MOS transistor 1, and a clock signal that is a complementary pair to the clock signal φ is supplied to the gate electrode G of the MOS transistor 2.
The substrate electrode B of the transistor 1 has a voltage V _SS (for example,
0V or negative polarity voltage), P channel MOS
It is constructed by supplying a voltage V _DD (for example, a positive polarity voltage) corresponding to the high potential of the clock signal φ to the substrate electrode B of the transistor 2, respectively.

In such a device, when the clock signal φ is set to the H level (V _DD ) and the clock signal is set to the L level (V _SS ), both the N-channel and P-channel MOS transistors 1 and 2 are turned on. As a result, the resistances R _N and R _P become small, the input signal IN is transmitted through both MOS transistors 1 and 2, and the output signal OUT is taken out from the terminal 4. On the other hand, when the clock signal φ is set to L level and the clock signal is set to H level, both MOS transistors 1 and 2 are turned off, their resistances R _N and R _P become extremely large, and the input signal IN is 4, and the output signal OUT is not taken out.

By the way, in an analog switch device, the input signal
Even if IN passes through MOS transistors 1 and 2, it is necessary to make the voltage of the output signal OUT equal to or linearly proportional to the voltage of the input signal IN. To do this, when both MOS transistors 1 and 2 are turned on, It is necessary to always keep the resistance value between terminals 3 and 4 constant. However, in conventional analog switch devices, the resistance between terminals 3 and 4 changes according to the voltage at terminals 3 or 4. this is
MOS transistors have a source-substrate bias effect (backgate bias effect), and this effect changes the threshold of the MOS transistor, which in turn affects the on-resistance of the MOS transistor. be. That is,
The following proportional equation holds true for the on-resistance R of the MOS transistor.

R∝1/V _GS −V _th (1) V _GS : Bias voltage between the gate electrode and source electrode V _th : Threshold value Further, the threshold value V _th of the MOS transistor is expressed by the following equation.

V _th = V _th0 + t _OX /ε _OX・√2・・_S・・(√2 _F + _BS −√2 _F ) …(2) V _th0 : Threshold of linearity (the difference between the source electrode and the substrate electrode) (When the bias voltage between is 0V) t _OX : Film thickness of gate oxide film ε _OX : Dielectric constant of gate oxide film ε _S : Dielectric constant of silicon q : Amount of electron charge N : Substrate impurity concentration V _BS : Source electrode Bias voltage between and the substrate electrode φ _F : Fermi level As is clear from the above equation (2), as V _BS increases, the threshold value V _th also increases, and as V _th increases, the above equation (1) R becomes larger.

Furthermore, the N-channel MOS transistor 1 of the analog switch device shown in FIG. In addition, the P channel MOS transistor 2 is connected to the substrate 11.
If the impurity concentration of the P well region 12 is naturally higher than that of the substrate 11,
The sensitivity of the threshold value of N-channel MOS transistor 1 to source-substrate bias effects is higher than that of P-channel MOS transistor 2, typically about three times higher. Therefore both
When MOS transistors 1 and 2 are on, the voltage of the input signal IN applied to terminal 3 is changed from V _SS (0V) to V _DD (+
5V), the resistance R _N of MOS transistor 1 and
The characteristics of MOS transistor 2 are not symmetrical with respect to resistor R _P , and as a result, near 1/2V _DD (+2.5V), which is the intermediate voltage of input signal IN, the terminal that is the parallel resistance of R _N and R _P The resistance R _ON (=R _N · R _P /R _N +R _P ) between 3 and 4 becomes a high value.

As described above, the conventional method has a disadvantage in that large distortion occurs in the output signal OUT because the resistance between the input and output terminals is not constant.

The present invention was made in consideration of the above-mentioned circumstances, and its purpose is to supply a bias voltage approximately equal to the analog signal voltage to the substrate electrode of a MOS field effect transistor so that the source of this transistor The substrate bias effect is minimized to eliminate threshold fluctuations, thereby keeping the resistance value between the input and output terminals of the analog signal constant.
An object of the present invention is to provide an analog switch device that can obtain an output signal with less distortion.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a circuit diagram of an analog switch device according to the present invention. In this device, instead of supplying V _SS to the substrate electrode B of the N-channel MOS transistor 1, the source electrode S of another N-channel enhancement type MOS transistor 5 is connected, and the drain electrode of this MOS transistor 5 is connected to the substrate electrode B of the N-channel MOS transistor 1. D is connected to the gate electrode G of the MOS transistor 1, the gate electrode G is connected to the terminal 3, and the substrate electrode B is connected to the source electrode S thereof. That is, the substrate electrode B of the MOS transistor 1 receives the input signal IN as a gate input.
It is connected via a MOS transistor 5 to a clock signal φ supply point. Note that, as in the past, N
As shown in FIG. 2, the P-channel MOS transistor 1 is provided in a P-well region 12 formed in an N-type semiconductor substrate 11 by a diffusion method or the like, and the P-channel MOS transistor 2 is provided in the substrate 11.
It is located inside.

In the analog switch device having the above configuration, first, when the clock signal φ is set to H level and the clock signal is set to L level,
Both MOS transistors 1 and 2 are turned on.
Next, when both the above MOS transistors 1 and 2 are in the on state, the resistance R _ON between terminals 3 and 4 is set as in the conventional case.
When the input signal IN voltage is 1/2V _DD (+2.5V), the MOS transistor 5 is on, and the voltage at the substrate electrode B of the MOS transistor 1 is V _IN −V _th5 = 1/ Asymptotically approaches 2V _DD -V _th5 (V _th5 is the threshold value of the MOS transistor 5). Therefore
Regarding MOS transistor 1, the voltage of substrate electrode B is approximately equal to the potential V _IN of input signal IN, V _IN -
V _th5 , and the voltage of the source electrode S is V _IN , so the source-to-substrate voltage V _BS is at most MOS
The threshold value of transistor 5 is V _th5 . This V _th5
Since the value of V remains constant and hardly changes even if V _IN changes, the source-substrate bias effect given to the MOS transistor 1 is extremely small. Therefore, changes in the on-resistance of the MOS transistor 1 due to threshold fluctuations can be almost eliminated.

Next, when clock signal φ is set to L level and clock signal φ is set to H level, the potential of drain electrode D of MOS transistor 5 becomes L level (V _SS ), and at this time, V _IN is higher than V _th5 . For example, the MOS transistor 5 is turned on,
The substrate electrode B of the MOS transistor 1 is applied with the L level potential of the clock signal φ, that is, V _SS .
On the other hand, if V _IN is lower than V _th5 , MOS transistor 5 is turned off, but MOS transistor 1
The P well region 12 is provided with a substrate electrode B of
A PN junction diode is formed between and the N-type semiconductor substrate 11, and the cathode side of this PN junction diode is maintained at V _SS , so that the voltage of the substrate electrode B of the MOS transistor 1 also is set to a sufficiently low value close to V _SS . Therefore, in this case, MOS transistor 1 is in the off state,
Furthermore, since the MOS transistor 2 is also turned off, both its resistances R _N and R _P have extremely large values, and as a result, the input signal IN is not transmitted to the terminal 4 and the output signal OUT is not taken out.

Figure 5 shows the resistance R _N of MOS transistor 1 and the MOS transistor when the voltage of input signal IN applied to terminal 3 is varied from 0V to +5V when both MOS transistors 1 and 2 are on in the above embodiment device. 2 _, and the resistance R _ON between terminals 3 and 4, which is expressed as a parallel resistance of R _N and R _P. In the characteristic diagram of the conventional device shown in Fig. 3, the voltage of the input signal IN is +
At around 2.5V, ΔV _th of N-channel MOS transistor 1 increased, and the value of R _N changed significantly.
In the above embodiment device, as shown in _FIG .
With R _P , the voltage of the input signal IN changes in line symmetry around +2.5V. In other words, this is the voltage between the substrate electrode B of the N-channel MOS transistor 1 and the predetermined voltage when the MOS transistor 1 is turned on.
Between clock signal φ which becomes V _DD (H level)
By inserting a MOS transistor 5 and applying an input signal IN to the gate electrode G of this MOS transistor 5, the substrate electrode B of the MOS transistor 1 is
A bias voltage almost equal to the voltage of the input signal IN is supplied to the source of MOS transistor 1.
The substrate bias effect is minimized, thereby eliminating threshold changes and eliminating threshold fluctuations.
This is because changes in R _N are kept to a minimum. Therefore, the resistance R _ON between the terminals 3 and 4 has a substantially flat characteristic, and can be kept at a constant value without being affected by the voltage of the input signal IN. As a result, distortion generated in the output signal OUT can be extremely reduced.

6 to 13 are circuit configuration diagrams of other embodiments of the present invention, respectively.

In the one shown in FIG. 6, another N-channel MOS transistor 6 is provided in parallel with the MOS transistor 5, and the gate electrode G of this MOS transistor 6 is connected to the terminal 4. Both can be used as an input signal terminal and an output signal extraction terminal.

In the case of FIG. 7, the drain electrode D of the MOS transistor 5 is connected to a constant potential V _B application point instead of being connected to the clock signal φ supply point.

In the one shown in FIG. 8, instead of directly connecting the MOS transistor 5 to the clock signal φ supply point, it is connected via another N-channel MOS transistor 7 which is controlled on/off by the clock signal φ. This is what I did.

In the one shown in FIG. 9, the drain electrode D of the MOS transistor 5 is connected to a point to which a constant potential V _B is applied via an N-channel MOS transistor 7 which is controlled on and off by a clock signal φ.

In FIG. 10, the drain electrode D of the MOS transistor 5 is connected to a point to which a constant potential V _B is applied via an N-channel MOS transistor 8 whose conduction is controlled by the output signal OUT.

In the case of FIG. 11, the drain electrode D of the MOS transistor 8 in FIG. 10 is connected to the clock signal φ supply point instead of being connected to the constant potential V _B application point.

In the case of FIG. 12, instead of connecting the gate electrode G of the MOS transistor 8 in FIG. 8 to the clock signal φ supply point, it is connected to the constant potential V _E application point, so that the MOS transistor 8 has a predetermined on-resistance. It is designed to be used as a resistive element with .

In the case of FIG. 13, the positions of MOS transistors 5 and 8 in FIG. 10 are switched.

In each of the embodiments shown in FIGS. 6 to 13, two MOS transistors are inserted between the substrate electrode _B of the MOS transistor 1 and a predetermined voltage, that is, the clock signal φ or VB. Even in this case, the gate electrode G of one of these MOS transistors is supplied with the input signal IN or the output signal OUT, so the substrate electrode B of the MOS transistor 1 is supplied with the voltage of the input signal IN or the output signal OUT. A bias voltage approximately equal to this voltage will be supplied. Therefore, in each of these embodiment circuits, the fifth
Characteristics equivalent to those shown in the figure can be obtained, and distortion generated in the output signal OUT can be extremely reduced.

Note that the present invention is not limited to the above-mentioned embodiment. For example, in the embodiment shown in FIG. 4, terminal 3 is described as an input signal supply terminal and terminal 4 as an output signal extraction terminal. 4
may be used as an input signal supply terminal, and terminal 3 may be used as an output signal extraction terminal.

Furthermore, in each embodiment device including the embodiment device shown in FIG. The substrate electrode B of the transistor may be connected to another potential point.

Furthermore, in the above embodiment, the N-channel
The MOS transistor 1 is placed in a P well region formed in an N type semiconductor substrate by a diffusion method or the like.
The case has been described in which the channel MOS transistors 2 are each provided in an N-type semiconductor substrate, and a bias voltage approximately equal to the voltage of the input signal IN or output signal OUT is supplied to the substrate electrode B of the N-channel MOS transistor 1. A P-channel MOS transistor 2 is provided in an N-well region formed in a P-type semiconductor substrate by a diffusion method, etc., and an N-channel MOS transistor 2 is provided in a P-type semiconductor substrate.
When providing transistor 1, the P channel
The sensitivity of the threshold value of MOS transistor 2 to the source-substrate bias effect is N-channel MOS.
Since it is larger than that of transistor 1, in this case, it is sufficient to supply a bias voltage corresponding to the voltage of terminal 4 or terminal 3 to the substrate electrode B of P-channel MOS transistor 2;
The MOS transistor inserted between the substrate electrode B of the transistor 1 or 2 and the predetermined voltage application point may also be a P-channel one.

In addition, if the impurity concentration of the substrates of N-channel MOS transistor 1 and P-channel MOS transistor 2 is high, a MOS transistor is inserted between each of the substrate electrodes B of both MOS transistors 1 and 2 and a predetermined voltage application point. Then, input signal IN or output signal to each substrate electrode B.
A bias voltage may be supplied depending on the voltage of OUT.

As explained above, according to the present invention, another MOS field effect transistor is inserted between the substrate electrode of a MOS field effect transistor for a switch and a predetermined voltage application point, and an analog signal is sent to the gate electrode of this transistor. By inputting a voltage and supplying a voltage lower than the analog signal voltage by the threshold voltage to the substrate electrode of the MOS field effect transistor for the switch, the analog switch can minimize distortion occurring in the output signal. equipment can be provided.

[Brief explanation of drawings]

Figure 1 is a circuit configuration diagram of a conventional analog switch device, Figure 2 is a cross-sectional view of the structure of a MOS field effect transistor that constitutes the device, Figure 3 is a characteristic diagram of the conventional device, and Figure 4 is the invention. FIG. 5 is a characteristic diagram of the device of the same embodiment, and FIGS. 6 to 13 are circuit diagrams of other embodiments of the present invention. 1...N channel enhancement type MOS
type field effect transistor, 2...P channel enhancement type MOS type field effect transistor,
3... Input signal supply terminal, 4... Output signal extraction terminal, 5, 6, 7, 8... N channel enhancement type MOS field effect transistor, 1
1...N-type semiconductor substrate, 12...P well region.

Claims (1)

[Claims] 1 Source and drain electrodes for inputting analog signals or outputting analog signals,
A first switch for a switch is provided with a gate electrode and a substrate electrode into which a control signal for conducting conduction control is input.
MOS type field effect transistor and the first
a second MOS field effect transistor inserted between the substrate electrode of the MOS field effect transistor and a predetermined voltage application point, the analog signal being input to the gate electrode; A voltage that is lower than the analog signal voltage by a certain voltage via the effect transistor is applied to the first
is supplied to the substrate electrode of the MOS field effect transistor, and the first
An analog switch device characterized in that it is configured to minimize distortion of an output analog signal by minimizing changes in resistance of a MOS field effect transistor.