JPH0368572B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog switch device using MOS field effect transistors.

An analog switch device is one that is turned on (conducting) by a clock signal that controls the device.
state or off (non-conducting) state,
It is a device in which input information, ie, an analog input signal, is transmitted to the output when it is in the on state, and no analog input signal is transmitted when it is in the off state.

FIG. 1 is a circuit diagram of a conventional analog switch device. This device consists of a source electrode S of an N-channel enhancement type MOS field effect transistor (hereinafter abbreviated as MOS transistor) 1 and a P-channel enhancement type MOS field effect transistor (hereinafter referred to as MOS transistor).
The drain electrode D of the transistor 2 is connected, and this connection point is connected to the supply terminal 3 of the analog input signal IN, and the drain electrode D of the MOS transistor 1 and the source electrode S of the MOS transistor 2 are connected.
and connect this connection point to the analog output signal.
Connect to OUT output terminal 4, and then
A clock signal φ is supplied to the gate electrode G of the MOS transistor 1, and a clock signal that is a complementary pair to the clock signal φ is supplied to the gate electrode G of the MOS transistor 2.
The substrate electrode B of the transistor 1 has a voltage V _SS (for example,
0V or negative polarity voltage), P channel MOS
It is constructed by supplying a voltage V _DD (for example, a positive polarity voltage) corresponding to the high potential of the clock signal φ to the substrate electrode B of the transistor 2, respectively.

In such a device, the clock signal φ is set to the H level V _DD and the clock signal is set to the L level.
When set to V _SS , both the N-channel and P-channel MOS transistors 1 and 2 are turned on, and their resistances R _N and R _P become small, respectively, and the input signal IN is applied to both MOS transistors 1 and 2.
2 and an output signal from terminal 4.
OUT is retrieved. On the other hand, when the clock signal φ is set to L level and the clock signal is set to H level, both MOS transistors 1 and 2 are turned off, and their resistances R _N and R _P become extremely large, and the input signal IN is applied to terminal 4. and the output signal OUT is not taken out.

By the way, in an analog switch device, the input signal
Even if IN passes through MOS transistors 1 and 2, it is necessary to make the voltage of the output signal OUT equal to or linearly proportional to the voltage of the input signal IN. To do this, when both MOS transistors 1 and 2 are turned on, It is necessary to always keep the resistance value between terminals 3 and 4 constant. However, in conventional analog switch devices, the resistance between terminals 3 and 4 changes according to the voltage at terminals 3 or 4. this is
MOS transistors have a source-substrate bias effect (backgate bias effect), and this effect changes the threshold value of the MOS transistor. This is because the on-resistance of the MOS transistor is affected by this. That is,
The following proportional equation holds true for the on-resistance R of the MOS transistor.

R∝1/V _GS −V _th (1) V _GS : Bias voltage between the gate electrode and source electrode V _th : Threshold value Further, the threshold value V _th of the MOS transistor is expressed by the following equation.

V _th = V _th0 +t _px /ε _px・√2・・_S・・(
√2 _F + _BS −√2 _F )…(2) V _th0 : Intrinsic threshold (when the bias voltage between the source electrode and substrate electrode is 0V) t _px : Thickness of gate oxide film ε _px : Dielectric constant of gate oxide film ε _s : Dielectric constant of silicon q : Amount of electron charge N : Substrate impurity concentration V _BS : Bias voltage between source electrode and substrate electrode φ _F : Fermi level Equation (2) above As is clear from the equation (1), as V _BS increases, the threshold value V _th also increases, and as V _th increases, R increases according to equation (1).

Furthermore, the N-channel MOS transistor 1 of the analog switch device shown in FIG. In addition, the P channel MOS transistor 2 is connected to the substrate 11.
If the impurity concentration of the P well region 12 is naturally higher than that of the substrate 11,
The threshold sensitivity of the N-channel MOS transistor 1 to source-substrate bias effects is higher than that of the P-channel MOS transistor 2, typically about three times higher. Therefore both
When MOS transistors 1 and 2 are on, the voltage of the input signal IN applied to terminal 3 is changed from V _SS (0V) to V _DD (+
5V), the resistance R _N of MOS transistor 1 and
The characteristics of MOS transistor 2 are not symmetrical with respect to the resistor R _P , and as a result, near 1/2V _DD (+2.5V), which is the intermediate voltage of the input signal IN, the terminal that is the parallel resistance of R _N and R _P The resistance R _ON (=R _N · R _P /R _N +R _P ) between 3 and 4 becomes a high value.

As described above, the conventional method has a disadvantage in that large distortion occurs in the output signal OUT because the resistance between the input and output terminals is not constant.

The present invention was made in consideration of the above-mentioned circumstances, and its purpose is to supply a bias voltage approximately equal to the analog signal voltage to the substrate electrode of a MOS field effect transistor so that the source voltage of the transistor is By minimizing the body bias effect and eliminating fluctuations in the threshold value, the resistance value between the analog signal input and output terminals is kept constant.
An object of the present invention is to provide an analog switch device that can obtain an output signal with less distortion.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a circuit diagram of an analog switch device according to the present invention. In this device, instead of supplying V _SS to the substrate electrode B of the N-channel MOS transistor 1, the source electrode S of another N-channel enhancement type MOS transistor 5 is connected, and the drain electrode of this MOS transistor 5 is connected to the substrate electrode B of the N-channel MOS transistor 1. D to terminal 3, gate electrode G to terminal 4
In addition, the substrate electrodes B are connected to the source electrodes S, respectively.

In the analog switch device having the above configuration, first, when the clock signal φ is set to L level and the clock signal is set to H level, both N-channel MOS transistor 1 and P-channel MOS transistor 2 are turned off, and their resistance
R _N and R _P have extremely large values. As a result, the input signal IN is not transmitted to terminal 4, and the output signal
OUT is not retrieved.

Next, the clock signal φ is set to the H level, and the clock signal φ is set to the H level. At this time,
MOS transistor 1 and MOS transistor 2
Since both are turned on, the input signal IN is transmitted to the terminal 4 via both MOS transistors 1 and 2, and the output signal OUT is taken out from the terminal 4. Furthermore, at this time, the voltage V _IN of the input signal IN is applied to the drain electrode D of another N-channel MOS transistor 5, and the output signal is applied to the gate electrode G.
Since the OUT voltage V _OUT is given, if the threshold value of this MOS transistor 5 is now V _th5 , when V _IN ≧V _OUT −V _th5 , the MOS transistor 5 enters the saturation operation region and becomes stable. , the potential of the source electrode S becomes V _OUT −V _th5 . On the other hand, V _IN <V _OUT
-V _th5 , the MOS transistor 5 enters the non-saturated operating region and becomes stable, and the potential of the source electrode S at this time becomes V _IN . The source electrode S of this MOS transistor 5 is the substrate electrode B of the MOS transistor 1.
Since the voltage applied to the substrate electrode B of this MOS transistor 1 is V _OUT −V _th5
Either V _IN . Also, the above V _IN ≧V _OUT −V _th5
When , the source-substrate voltage V _BS of the MOS transistor 1 becomes V _th5 , and when V _IN <V _OUT -V _th5 , it becomes V _IN -V _OUT (≈0). As a result, M.O.S.
The source-substrate voltage V _BS of transistor 1 is always
V _th5 or less, and the source-substrate bias effect given to this MOS transistor 1 becomes extremely small or almost zero. Therefore, changes in the on-resistance of the MOS transistor 1 due to threshold fluctuations can be almost eliminated.

Figure 5 shows the resistance R _N of MOS transistor 1 and the MOS transistor when the voltage of input signal IN applied to terminal 3 is varied from 0V to +5V when both MOS transistors 1 and 2 are on in the above embodiment device. 2 _, and the resistance R _ON between terminals 3 and 4, which is expressed as a parallel resistance of R _N and R _P. In the characteristic diagram of the conventional device shown in Fig. 3, the voltage of the input signal IN is +
At around 2.5V, △V _th of the N-channel MOS transistor 1 increased, and the value of R _N changed greatly, but in the above example device, as shown in FIG.
R _N and R _P change line-symmetrically when the voltage of the input signal IN is around +2.5V. That is, by supplying the signal voltage at the source electrode S or drain electrode D to the substrate electrode B of the N-channel MOS transistor 1 via the MOS transistor 5, the source-substrate bias effect is minimized, and the MOS transistor 1
By eliminating fluctuations in the threshold value, R _N
This is because we tried to minimize the change in
Therefore, the resistance R _ON between the terminals 3 and 4 has a substantially flat characteristic, and can be kept at a constant value without being affected by the voltage of the input signal IN. As a result, the output signal
Distortion generated at OUT can be made extremely small.

FIG. 6 is a circuit diagram of another embodiment of the invention. In this example circuit, another N-channel, enhancement type MOS transistor 6
, the source electrode S of this MOS transistor 6 is connected to the substrate electrode B of MOS transistor 1, the drain electrode D of this MOS transistor 6 is connected to terminal 4, the gate electrode G is connected to terminal 3, and the substrate electrode B is connected to terminal 4. The terminals 3 and 4 are connected to the source electrode S, respectively, and both terminals 3 and 4 can be used as an input signal supply terminal and an output signal extraction terminal.

Note that the present invention is not limited to the above-described embodiment; for example, in the embodiment shown in FIG. 4, the source electrode S of the MOS transistor 1 and
Connect the drain electrode D of the MOS transistor 2, and connect this connection point to the input signal supply terminal 3.
Also, the drain electrode D of MOS transistor 1 and
Connect the source electrode S of the MOS transistor 2,
Although a case has been described in which this connection point is connected to the output signal take-out terminal 4, the terminal 4 may be used as the input signal supply terminal and the terminal 3 may be used as the output signal take-out terminal.

Furthermore, in the above example, the newly added MOS
Although the case has been described in which the substrate electrodes B of the transistors 5 and 6 are connected to the respective source electrodes S, the substrate electrodes B of the MOS transistors 5 and 6 may be connected to other potential points.

Furthermore, in the above embodiment, the N-channel
The MOS transistor 1 is placed in a P well region formed in an N type semiconductor substrate by a diffusion method or the like.
Each of the channel MOS transistors 2 is provided in an N-type semiconductor substrate, and the voltage at the source electrode S (terminal 4) or drain electrode D (terminal 3) of the N-channel MOS transistor 1 is applied to only the N-channel MOS transistor 5. Or MOS
The case where the supply is supplied to the substrate electrode B of the MOS transistor 1 through the transistors 5 and 6 has been described, but this is a case in which a P channel is supplied to the substrate electrode B of the MOS transistor 1 through the transistors 5 and 6.
When a MOS transistor 2 is provided and an N-channel MOS transistor 1 is provided in a P-type semiconductor substrate, the sensitivity of the threshold value of the P-channel MOS transistor 2 to the source-substrate bias effect is the same as that of the N-channel MOS transistor 1. In this case, it is sufficient to supply the voltage of terminal 4 or terminal 3 to the substrate electrode B of the P-channel MOS transistor 2 via the MOS transistor, and also supply the voltage of the terminal 4 or 3 to the substrate electrode of the MOS transistor 1 or The MOS transistors inserted between B and terminals 3 and 4 may also be of P channel type.

Further, when the impurity concentration of the substrates of N-channel MOS transistor 1 and P-channel MOS transistor 2 is high, the substrate electrodes B of both MOS transistors 1 and 2 and terminals 3 and 4
A MOS transistor may be inserted between either one or both of them.

As explained above, according to this invention, the MOS
The analog signal voltage at the source electrode or drain electrode of the type field effect transistor is supplied to the substrate electrode of the MOS transistor via a switch element that is switch-controlled in accordance with the analog signal voltage at the drain electrode or source electrode. Accordingly, it is possible to provide an analog switch device that can extremely minimize distortion generated in an output signal.

[Brief explanation of drawings]

Figure 1 is a circuit configuration diagram of a conventional analog switch device, Figure 2 is a cross-sectional view of the structure of a MOS field effect transistor that constitutes the conventional device, Figure 3 is a characteristic diagram of the conventional device, and Figure 4 is a diagram of the structure of the conventional analog switch device. A circuit configuration diagram of an embodiment of this invention, FIG. 5 is a characteristic diagram of the device of the embodiment,
FIG. 6 is a circuit diagram of another embodiment of the invention. 1...N channel enhancement type MOS
type field effect transistor, 2...P channel enhancement type MOS type field effect transistor,
3... Input signal supply terminal, 4... Output signal extraction terminal, 5, 6... N channel enhancement type MOS field effect transistor, 11... N type semiconductor substrate, 12... P well region.

Claims (1)

[Claims] 1. A first MOS field effect transistor provided with a source and a drain electrode for inputting and outputting an analog signal, a gate electrode and a substrate electrode to which a control signal for conducting conduction control is input. , a drain electrode is connected to the source electrode of the first MOS field effect transistor, a source electrode is connected to the substrate electrode of the first MOS field effect transistor,
Gate electrodes are respectively connected to the drain electrodes of the first MOS field effect transistors, and the analog signal voltage at the source electrode of the first MOS field effect transistor is connected to the first MOS field effect transistor.
and a second MOS type field effect transistor for controlling supply to the substrate electrode of the MOS type field effect transistor, and the second MOS type field effect transistor controls the supply voltage to the substrate electrode of the input analog signal.
Reduces threshold fluctuations due to source/substrate bias effects of MOS field effect transistors,
An analog switch device characterized in that the change in resistance of the first MOS field effect transistor is reduced to reduce distortion of the output analog signal. 2. A first channel first MOS field effect transistor provided with a source and drain electrode for inputting and outputting an analog signal, a gate electrode and a substrate electrode to which a first control signal for conducting conduction control is input; , a second channel whose source and drain electrodes are respectively connected to the drain and source electrodes of the first MOS field effect transistor, and whose gate electrode is inputted with a second control signal having an opposite phase to the first control signal; 2, a MOS field effect transistor having a drain electrode connected to the source electrode of the first MOS field effect transistor, and a source electrode connected to the substrate electrode of the first MOS field effect transistor;
Gate electrodes are respectively connected to the drain electrodes of the first MOS field effect transistors, and the analog signal voltage at the source electrode of the first MOS field effect transistor is connected to the first MOS field effect transistor.
a third MOS type field effect transistor of the first channel for controlling supply to the substrate electrode of the type field effect transistor;
Reduces threshold fluctuations due to source/substrate bias effects of MOS field effect transistors,
An analog switch device characterized in that the change in resistance of the first MOS field effect transistor is reduced to reduce distortion of the output analog signal.