JP2853599B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JP2853599B2
JP2853599B2 JP5026595A JP5026595A JP2853599B2 JP 2853599 B2 JP2853599 B2 JP 2853599B2 JP 5026595 A JP5026595 A JP 5026595A JP 5026595 A JP5026595 A JP 5026595A JP 2853599 B2 JP2853599 B2 JP 2853599B2
Authority
JP
Japan
Prior art keywords
semiconductor element
ceramic package
package
opening
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5026595A
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English (en)
Other versions
JPH08250617A (ja
Inventor
健二 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
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Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5026595A priority Critical patent/JP2853599B2/ja
Priority to US08/613,690 priority patent/US6084298A/en
Publication of JPH08250617A publication Critical patent/JPH08250617A/ja
Application granted granted Critical
Publication of JP2853599B2 publication Critical patent/JP2853599B2/ja
Priority to US09/304,989 priority patent/US20010013648A1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】
【0001】
【産業上の利用分野】本発明は、セラミックパッケージ
とこれを用いた半導体装置の製造方法に関する。
【0002】
【従来の技術】セラミックパッケージは、電気絶縁特
性、熱伝導特性、熱膨張特性、機械的強度、科学的安定
性等において比較的優れた材料特性を有し、かつ経済的
量産技術が確立しているため高信頼性のパッケージとし
て産業LSI等に広く適用されている。
【0003】以下、従来のセラミックパッケージを用い
た半導体装置について図面を用いて説明する。図4は、
従来のセラミックパッケージ図であり、以下、このパッ
ケージの製造方法を示す。
【0004】セラミックの生パッケージ(以下グリーン
シートと記す)を成形し、配線等のヴィアホール及び半
導体素子を搭載する開口部を形成した後に、パッケージ
内部配線を形成する。
【0005】その後、複数のグリーンシートを積層した
後に焼成を行い、さらに外部リード3のロー付け・外装
メッキを施しパッケージを作成する。さらに、パッケー
ジの半導体搭載部(以下キャビティーと記す)に金属ロ
ー材6を介して半導体素子5をセラミックパッケージキ
ャビティー部に固定し、AlもしくはAuの金属配線8
を用いて半導体素子5とパッケージ配線の電気的接続を
行なう。以上の手段より図4が形成される。さらに、パ
ッケージを封止し、半導体装置を形成する。
【0006】
【発明が解決しようとする課題】従来のセラミックパッ
ケージの製造方法ならびに半導体装置の組立方式では、
セラミックパッケージの製造工程においてグリーンシー
トの燃成時に20〜30%のシート収縮が発生する。ま
たグリーンシートを積層する際に積層シート間での位置
ずれの発生等によりキャビティー部のような開口部の寸
法公差は、設計寸法に対して10%程度を必要とする。
【0007】また、半導体装置の組立工程においてもパ
ッケージキャビティー部に半導体素子を固定する工程に
おいて、図5に示すように半導体素子5を保持し、キャ
ビティー部へ移動させるために治工具9寸法及び半導体
素子5とキャビティー部への密着を向上させるための振
動を付加するための間隔が必要であり、実際のキャビテ
ィー寸法は搭載させる半導体素子より最低でも2mm以上
は大きくしなければならなかった。
【0008】以上、このようなセラミックパッケージに
おいては、半導体素子とパッケージとを電気的に接続す
る金属配線の長さが長くなってしまい、金属配線部のイ
ンダクダ成分より半導体素子の同時動作数が制限される
場合や動作速度を高速化できないという問題が生じてい
る。
【0009】したがって、本発明の目的は、小型化され
たセラミックパッケージ及び同パッケージを用いた半導
体装置の製造方法を提供することにある。。
【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体装置は、セラミックパッケージを焼
成後に、搭載する半導体素子が挿入できるような穴をキ
ャビティー部の一部を開口することを特徴とする。
【0010】
【作用】上記手段を採用することにより、セラミックパ
ッケージキャビティーサイズを半導体サイズに近づける
ことができ、その結果、金属配線長を短くすることがで
きる。
【0011】
【実施例】本発明の上記及び他の目的、特徴及び効果を
明確にすべく、以下、図面を用いて本発明の実施例につ
いて説明する。
【0012】図1は、本発明のセラミックパッケージの
製造方法を示す。
【0013】セラミックパッケージを用いた半導体装置
は、Al2O3等のセラミック粉末にガラス成分・顔料成
分及び有機溶剤成分を調合し、ドクターフレーズ法等を
使用してグリーンシートを成形する。つぎに、配線等の
ヴィアホールをプレス法等により成形した後、パッケー
ジ内部配線を導体ペーストをスクリーン印刷法により成
形する。
【0014】その後、2枚のグリーンシートを積層した
後にキャビティー部の開口部を設けずにバインダ(接着
剤)を介してグリーンシートを加圧接着し、その後水素
雰囲気中にてセラミックの焼成を行う(a)。次に、セ
ラミックパッケージ燃成終了後にワイヤー放電加工等の
機械的加工方法を用いて搭載する半導体素子を収納でき
る大きさのキャビティー部を形成し、また外部リード3
のロー付け・外装メッキを施しパッケージを作成する
(b)。後は、従来の方法によりパッケージを封止して
セラミックパッケージを完成させる。
【0015】本方式での製造方法は、セラミックパッケ
ージを積層・焼成後にキャビティー部を開口しているた
め、加工寸法精度を数μm単位での加工が可能であり、
よって、従来のセラミックパッケージの製造方法と比較
して寸法精度を著しく向上できる。
【0016】図2は、本発明のセラミックパッケージを
使用した半導体装置の組立工程を示している。CuW、
AlN等の熱伝導率の優れる半導体素子搭載基板4上に
半導体素子5をAuSi等の金属ロー材6を介して固定
しておき、その後、半導体素子5をセラミックパッケー
ジ1に機械的加工により設けた開口部に挿入して、セラ
ミックパッケージ1と半導体素子6に搭載した基板4と
をAuSn合金、半田又は樹脂等を用いて固定する
(a)。AuSn合金は、融点温度が300℃程度であ
るために半導体素子に熱的影響が少なくて済むという効
果がある。
【0017】このセラミックパッケージ1と半導体素子
5を固定した基板6とを接合した後、金属配線8により
半導体素子5とセラミックパッケージ1上に設けられた
電極と電気的に接続し半導体装置を形成する(b)。
【0018】図3の(a)に、図2(b)の斜視図、図
3の(b)に図2(b)の底面図を示す。図3(a)に
示されるように、セラミックパッケージの密封性をよく
するために先に示した接合材料7が半導体素子搭載基板
4の周辺を取り囲むように設けられている。また、図
(b)に示されるように、半導体素子5は、金属配線8
を介してセラミックパッケージ1上のリード配線(図示
無し)に接続されている。そして、そのリード配線は、
外部リード配線3に接続されセラミックパッケージ外に
設けられている電極と接続される。
【0019】さらに、本願構成は、セラミックパッケー
ジを開口して半導体素子を設ける構成であるために、半
導体素子5、AuSi合金6、半導体搭載基板4、及び
AuSn7等の導電材料を介して半導体素子5を接地す
ることも可能である。
【0020】
【発明の効果】以上説明したように、本発明のセラミッ
クパッケージは、半導体素子と同一サイズのキャビティ
ーを形成することが可能となり、半導体素子とセラミッ
クパッケージとを接続する金属配線部を長さで少なくと
も1.5mm以上、インダクタンス値で少なくとも1nH
以上低減でき、半導体装置の同時動作数、高速駆動特性
を著しく改善できる。
【0021】また、1種類のセラミックパッケージにお
いて、異なったサイズの半導体素子を搭載することが可
能であり、汎用性に優れたセラミックパッケージを提供
することができる。
【0022】また、本発明は、グリーンシート部を開口
して半導体素子を埋め込む方式のため、グリーンシート
は2枚ですみ、コストが安くなるという効果がある。
【0023】また、半導体基板は、外気にさらされてい
る放熱性の優れた基板上に設けてられているため、半導
体基板の温度が上昇しにくいという効果を有する。
【0024】また、開口部から半導体素子を埋め込む形
式のため、セラミックパッケージ外に前記開口部を介し
て端子を設けることができるという効果もある。
【図面の簡単な説明】
【図1】本発明のセラミックパッケージの断面図・斜視
図。(a)はキャビティー部開口前、(b)はキャビテ
ィー部開口後である。
【図2】本発明のセラミックパッケージを用いた半導体
装置の組立方法。(a)は半導体素子を搭載した基板と
セラミックパッケージの接合前、(b)は接合後であ
る。
【図3】(a)は図2(b)の斜視図、(b)は図2
(b)の底面図である。
【図4】従来のセラミックパッケージを用いた半導体装
置の断面図。
【図5】従来のセラミックパッケージを用いた半導体素
子固定方法。
【符号の説明】
1. セラミックパッケージ 2. キャビティー部 3. 外部リード 4. 半導体素子搭載基板 5. 半導体素子 6. AuSi合金 7. AuSn合金 8. 金属配線 9. 半導体素子搭載用治工具

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項1】 予め開口部を設けた焼成前のセラミック
    からなるグリーンシート上に、配線パターンが印刷さ
    れ、開口部が設けられていないグリーンシートを積層す
    る工程と、 前記グリーンシート群を焼成する工程と、 前記開口部が設けられていないグリーンシートに半導体
    素子を挿入するための開口部を形成する工程と、 を有することを特徴とするセラミックパッケージの製造
    方法。
  2. 【請求項2】 放熱性の優れた基板上に固定された半導
    体素子を、前記焼成後に設けられた開口部に挿入するこ
    とを特徴とする請求項1記載の半導体装置の製造方法。
JP5026595A 1995-03-10 1995-03-10 半導体装置の製造方法 Expired - Lifetime JP2853599B2 (ja)

Priority Applications (3)

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JP5026595A JP2853599B2 (ja) 1995-03-10 1995-03-10 半導体装置の製造方法
US08/613,690 US6084298A (en) 1995-03-10 1996-03-11 Manufacturing of semiconductor device
US09/304,989 US20010013648A1 (en) 1995-03-10 1999-05-04 Method of manufacturing a ceramic package utilizing green sheets

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5026595A JP2853599B2 (ja) 1995-03-10 1995-03-10 半導体装置の製造方法

Publications (2)

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JPH08250617A JPH08250617A (ja) 1996-09-27
JP2853599B2 true JP2853599B2 (ja) 1999-02-03

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TWI540768B (zh) * 2012-12-21 2016-07-01 鴻海精密工業股份有限公司 發光晶片組合及其製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5471572A (en) * 1977-11-18 1979-06-08 Fujitsu Ltd Semiconductor device
US4513355A (en) * 1983-06-15 1985-04-23 Motorola, Inc. Metallization and bonding means and method for VLSI packages
JPH0719155Y2 (ja) * 1988-12-06 1995-05-01 旭硝子株式会社 半導体パツケージ
JP2678489B2 (ja) * 1988-12-21 1997-11-17 京セラ株式会社 半導体素子収納用パッケージの製造方法
JPH06295962A (ja) * 1992-10-20 1994-10-21 Ibiden Co Ltd 電子部品搭載用基板およびその製造方法並びに電子部品搭載装置
KR0143870B1 (ko) * 1993-12-27 1998-07-01 사토 후미오 고열전도성 질화규소 구조부재 및 반도체 패키지, 히터, 서멀헤드
US5650593A (en) * 1994-05-26 1997-07-22 Amkor Electronics, Inc. Thermally enhanced chip carrier package
US5721454A (en) * 1995-12-20 1998-02-24 Intel Corporation Integrated circuit package with a plurality of vias that are electrically connected to an internal ground plane and thermally connected to an external heat slug
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure

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US20010013648A1 (en) 2001-08-16
JPH08250617A (ja) 1996-09-27
US6084298A (en) 2000-07-04

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