JP2636776B2 - ワイヤーボンディング方法 - Google Patents

ワイヤーボンディング方法

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Publication number
JP2636776B2
JP2636776B2 JP7021459A JP2145995A JP2636776B2 JP 2636776 B2 JP2636776 B2 JP 2636776B2 JP 7021459 A JP7021459 A JP 7021459A JP 2145995 A JP2145995 A JP 2145995A JP 2636776 B2 JP2636776 B2 JP 2636776B2
Authority
JP
Japan
Prior art keywords
wire
electrode
lead
connection point
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7021459A
Other languages
English (en)
Other versions
JPH08222595A (ja
Inventor
賢治 大谷内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP7021459A priority Critical patent/JP2636776B2/ja
Priority to US08/597,163 priority patent/US5647527A/en
Priority to KR1019960002971A priority patent/KR100205728B1/ko
Publication of JPH08222595A publication Critical patent/JPH08222595A/ja
Application granted granted Critical
Publication of JP2636776B2 publication Critical patent/JP2636776B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
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    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】
【0001】
【産業上の利用分野】本発明は、半導体素子の各電極を
対応するリードピンにワイヤでボンディングするワイヤ
ボンディング方法に関し、特にワイヤのボンディングの
順序の改良に関する。
【0002】
【従来の技術】半導体素子の電極は通常素子周辺に沿っ
て設けられているが、半導体素子の中には、図2に示す
ような、素子1の中央部に一列に電極2を配置したもの
がある。このような素子はダイナミック型半導体メモリ
にみられる。
【0003】半導体素子の各電極は対応するリードピン
にワイヤで接続されるが、図2のように素子1の中央部
に一列に電極2が配置されたものでは、素子1上に接着
テープ9によりリードピン3が取り付られ、ワイヤ4に
より接続される。
【0004】ワイヤ4と対応する電極2およびリード3
との接続は、まず、図3(a)のように、ワイヤ4の先
端に、電気放電等の方法により、金属小球5を形成す
る。次に図3(b)のようにキャピラリー6により、金
属小球5を電極2に押圧して接合し、その後図3(c)
のようにキャピラリー6を引き上げる。次に図3(d)
のように、キャピラリー6を接合すべきリードと反対方
向に水平に移動し、ワイヤ4に屈曲部7を設ける。この
屈曲部7を設ける作業は接合後のワイヤ4の形状を均一
化するのに重要であり、特に半導体素子1からのワイヤ
4の最高部位の高さを常に一定に保つのに重要である。
【0005】ワイヤ4に屈曲部7を設けた後、図3
(e)のように、ワイヤ4をくり出しながらキャピラリ
6を接合すべきリード3の方向へ、円の軌跡を描きなが
ら移動させる。そして、キャピラリ6が図3(f)のよ
うにリード3上に移動した時点でワイヤ4をキャピラリ
6でリード3に押圧してワイヤ4とリード3を接合す
る。
【0006】以上が一つの電極4と対応するリード3と
の間のワイヤ4による電気的接合を得るための手順であ
るが、半導体素子1は、複数の電極4及び複数のリード
3を有している。図2の例では、所渭ノンコネクト電極
を除いて26箇所の接合が必要である。
【0007】かかる26箇所の接合順序は、一般に、図
4(a)〜(f)に示すように電極2が配置された列の
端の電極2から接合を始め、電極が配置された順番に接
合していくという方法がとられていた。
【0008】
【発明が解決しようとする課題】図3を用いて説明した
ように、ボンディング後のワイヤ4の形状を安定させる
ため、半導体素子1上の電極2とワイヤ4先端の金属小
球5と接合した後、キャピラリ6を電極4の真上に上
げ、そして、ワイヤ4を接合すべきリードと反対方向に
素子1の表面と水平に移動してワイヤ4に屈曲部7を設
けることが要求されている。ところが、図4(d)に示
すように、例えば電極2−13に対するワイヤ4−13
のボンディングを行うとき、キャピラリの移動方向に電
極2−12にすでにボンディングされているワイヤ4−
12が存在するため、キャピラリ6が移動すると、かか
るワイヤ4−12にキャピラリが接触してこのワイヤ4
−12を変形又は切断してしまうという不具合いがあっ
た。この不具合の解消のためには、電極2及びリード3
の配置が制限されることになり、半導体素子及びリード
の設計が困難になる。さらに、キャピラリの移動する領
域を確保するために、余分な領域が必要となり、半導体
素子1そのものが大きくなってしまうという不具合いも
あった。
【0009】したがって、本発明の目的は、他のワイヤ
やリードを変形或いは切断することなく各電極と対応す
るリードとの間のワイヤによるボンディングを可能とし
たワイヤボンディング方法を提供することにある。
【0010】
【課題を解決するための手段】本発明のワイヤボンディ
ング方法は、正方形あるいは長方形の半導体素子の相対
する辺の中央近傍同志を結ぶ直線上に、概略一列に配列
された電極と、前記電極の周辺に配置されたリードとを
ワイヤにて結線するワイヤボンディング方法において、
そのボンディング順序が、前記半導体上の電極と前記リ
ードを半導体素子に垂直な方向から見た平面図上でリー
ド上の結線点と、前記リードに対応する結線点を結ぶ線
分が、他のリード上の結線点と、各々に対応する電極上
の結線点を結ぶ線分をリードから電極に向かって延長し
た半直線と交差する時、前記リード上の結線点と電極上
の結線点を結ぶ線分に対応するワイヤすなわち前記半直
線により分割され得る線分に対応するワイヤを、前記半
直線に含まれるリード上の結線点と電極上の結線点に対
応するワイヤより後にボンディングするワイヤボンディ
ング方法である。
【0011】
【実施例】次に、本発明の実施例につき図面を参照して
詳細に説明する。
【0012】図1(a)は本発明の一実施例によるワイ
ヤボンディング法が施された後の素子平面図である。前
述のとおり、例えば電極207に対するワイヤボンディ
ングを施した後に電極208のボンディングを行うと、
ワイヤ407が変形もしくは切断される可能性がある。
その理由をより詳細に解析すると以下のとおりとなる。
【0013】すなわち、ワイヤ407は、図1(b)の
ボンディング前の素子平面図において電極207上の設
計における結線点827と、リード307上の設計にお
ける結線点837とを結線するものである。一方、ワイ
ヤ408は電極208上の設計における結線点828
と、リード308上の設計における結線点838を結線
して成るワイヤである。ここで、結線点838と結線点
828とを結ぶ線分を、結線点828方向に延長した半
直線は、図示のように、結線点827と結線点837と
を結ぶ線分すなわちワイヤ407と交差する。このた
め、ワイヤ407を結線した後にワイヤ408を結線す
るとキャピラリがワイヤ407に接触してワイヤ407
が変形する。このように結線点838と結線点828と
を結ぶ線分を結線点828方向に延長した半直線が結線
点827と結線点837とを結ぶ線分を分割するのであ
るから、結線点827と結線点837とを結ぶ線分に対
応するワイヤ407を、結線点828と結線点838を
結ぶ線分に対応するワイヤ408の後にボンディングす
ればよいことを示している。
【0014】同様に全てのワイヤに対して図1(b)の
考察を対応する一対のワイヤ結線点同士についてくり返
し行なうと図1(c)のようになる。この図から解るよ
うに、図1(a)に示された半導体装置におけるワイヤ
ボンディング順序は、ワイヤ408,ワイヤ407,ワ
イヤ406,ワイヤ405の順番でボンディングするグ
ループとワイヤ401,ワイヤ402,ワイヤ403,
ワイヤ404の順序でボンディングするグループの2つ
に分けられる。この時、ボンディングを最初に行なうワ
イヤは、どの半直線にも分割されないワイヤからとな
る。
【0015】また、この2つのグループはボンディング
におけるキャピラリとワイヤの干渉の不具合いについ
て、互いに無関係なためどちらのグループを先にボンデ
ィングしてもよい。さらにグループ内でのボンディング
順序が前述のとおりであれば例えば、ワイヤ408,ワ
イヤ401,ワイヤ407,ワイヤ402,ワイヤ40
6,ワイヤ403,ワイヤ405,ワイヤ404のよう
な順序でボンディングすることもできる。
【0016】
【発明の効果】以上説明したように本発明では、ワイヤ
のボンディング順序を、半導体素子上の電極と、リード
を半導体素子に対して垂直な方向から見た平面図上で、
リード上の結線点と前記リードに対応する電極上の結線
点を結ぶ線分が、他のリード上の結線点と各々に対応す
る電極上の結線点を結ぶ線分をリードから電極に向かっ
て延長した半直線と交差する時、前記リード上の結線点
と電極上の結線点を結ぶ線分に対応するワイヤすなわち
前記半直線により分割され得る線分に対応するワイヤを
前記半直線に含まれるリード上の結線点と電極上の結線
点に対応するワイヤより後にボンディングするようにし
ている。したがってボンディング装置が、半導体素子上
の電極と、ワイヤ先端に形成した金属小球を接合した
後、ギャピラリを電極の真上に上げた後、ワイヤを接合
すべきリードと反対方向に半導体素子と水平に移動し、
ワイヤに屈曲部を設ける際に、すでにボンディングを完
了している隣接ワイヤにキャピラリが接触し前記の隣接
ワイヤを変形又は切断してしまうという不具合いが解消
されるという利点がある。
【0017】すなわち、半導体素子設計者においては、
前記の不具合いについて全く注意することなく、半導体
素子及びリードの設計を行なうことが可能となる。例え
ば、従来の方法においては、図2の設計によるボンディ
ングは可能であるが、図5の設計によるボンディングは
不可能であり許され得ない設計となっていた。しかしな
がら本発明のワイヤボンディング方法によれば、図2及
び図5の設計によるボンディングも可能であり設計の自
由度を増すという利点がある。
【図面の簡単な説明】
【図1】(a)は本発明の一実施例のボンディング完了
時の上面図、(b),(c)は本発明の一実施例のボン
ディング順序決定方法説明図。
【図2】半導体素子電極及びリード配置設計図。
【図3】(a)〜(f)はワイヤボンディング工程動作
説明図。
【図4】(a)〜(f)はワイヤボンディング順序説明
図。
【図5】半導体素子電極及びリード配置設計図。
【符号の説明】
1 半導体素子 2,207,208 電極 3,307,308 リード 4,401,402,403,404,405,40
6,407,408ワイヤ 5 金属小球 6 キャピラリ 7 屈曲部 8,827,828,837,838 結線点 9 接着テープ

Claims (3)

    (57)【特許請求の範囲】
  1. 【請求項1】 半導体素子の中央近傍に、概略一列に配
    列された複数の電極の各々を対応するリードにワイヤに
    て結線するワイヤボンディング方法において、前記半導
    体素子上の第1の電極上のワイヤ結線点と対応するリー
    ド上のワイヤ結線点とを結ぶ線分の延長線が前記第1の
    電極に隣接する第2の電極のワイヤ結線点と対応するリ
    ード上の結線点とを結ぶ線分と交差する時、前記第1の
    電極に対するワイヤの結線を行ないその後前記第2の電
    極に対するワイヤの結線を行うことを特徴とするワイヤ
    ボンディング方法。
  2. 【請求項2】 半導体素子上に略一列に配列された第
    1,第2,第3および第4の電極を、当該第1乃至第4
    の電極の配列の右側に配置された第1および第2のリー
    ドならびに左側に配置された第3および第4のリード
    に、前記第1の電極と前記第1のリードとを、前記第2
    の電極と前記第3のリードとを、前記第3の電極と前記
    第4のリードとを、前記第4の電極と前記第2のリード
    とをそれぞれ対応させて各々ワイヤにて結線する際に、
    結線すべき電極とリードとを結ぶ線分の延長線がすでに
    結線ずみのワイヤと交差しない順番をもってそれぞれ結
    線することを特徴とするワイヤボンディング方法。
  3. 【請求項3】 前記ワイヤによる結線を、前記第1の電
    極と前記第1のリード、前記第2の電極と前記第3のリ
    ード、前記第3の電極と前記第4のリード、および前記
    第4の電極と前記第2のリードの順に行うことを特徴と
    する請求項2のワイヤボンディング方法。
JP7021459A 1995-02-09 1995-02-09 ワイヤーボンディング方法 Expired - Fee Related JP2636776B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP7021459A JP2636776B2 (ja) 1995-02-09 1995-02-09 ワイヤーボンディング方法
US08/597,163 US5647527A (en) 1995-02-09 1996-02-05 Method of determining order of wire-bonding
KR1019960002971A KR100205728B1 (ko) 1995-02-09 1996-02-08 접선순서결정방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7021459A JP2636776B2 (ja) 1995-02-09 1995-02-09 ワイヤーボンディング方法

Publications (2)

Publication Number Publication Date
JPH08222595A JPH08222595A (ja) 1996-08-30
JP2636776B2 true JP2636776B2 (ja) 1997-07-30

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Country Link
US (1) US5647527A (ja)
JP (1) JP2636776B2 (ja)
KR (1) KR100205728B1 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3413340B2 (ja) * 1997-03-17 2003-06-03 株式会社新川 ワイヤボンディング方法
JPH1140595A (ja) * 1997-07-16 1999-02-12 Mitsubishi Electric Corp ワイヤ配線方法、このワイヤ配線方法に使用する配線分岐パッド、および、ボンディング装置、並びに、ワイヤ配線方法をコンピュータに実行させるためのプログラムを記録したコンピュータ読み取り可能な記録媒体
WO2023158625A1 (en) * 2022-02-15 2023-08-24 Kulicke And Soffa Industries, Inc. Methods of determining a sequence for creating a plurality of wire loops in connection with a workpiece

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831733B2 (ja) * 1982-03-15 1983-07-08 株式会社日立製作所 集積回路装置
JPH05136193A (ja) * 1991-11-12 1993-06-01 Sumitomo Electric Ind Ltd 半導体デバイスのパツケージ構造
US5269452A (en) * 1992-11-12 1993-12-14 Northern Telecom Limited Method and apparatus for wirebonding

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KR100205728B1 (ko) 1999-07-01
JPH08222595A (ja) 1996-08-30
US5647527A (en) 1997-07-15

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