JP2615821B2 - Digital information signal reproducing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information signal reproducing apparatus applied to processing of a digital VTR audio signal for recording / reproducing a digital video signal and a digital audio signal.

[Summary of the Invention]

According to the present invention, the same first digital audio signal and second digital audio signal are duplicatedly recorded on the recording medium, and during the overlap period, the first digital audio signal and the second digital audio signal are duplicated. In a digital information signal reproducing apparatus in which only one of signals is rewritten, a first flag and a second flag indicating an overlap period separated from each of the first and second digital audio signals are set. The memory is reset and held at regular intervals, and the third and fourth flags indicating whether the first and second flags are correctly obtained are also reset at regular intervals. A first digital memory in accordance with the memory and first, second, third and fourth flags stored in the memory; And a circuit for selectively outputting a digital audio signal and a second digital audio signal, when the first and second flags indicating the overlap period are erroneous or cannot be obtained, Mixing and decoding of the digital audio signal and the second digital audio signal can be prevented.

[Conventional technology]

For example, a digital VTR for recording / reproducing a composite digital video signal and digital audio signal
As one of them, there is a digital audio signal which can be recorded twice. In such a digital VTR, only one digital audio signal is rewritten during editing to form a period in which new audio data and old audio data overlap, and cross-fade processing is performed in this overlap period. In the overlap period, the flag ELAP is recorded in the data, and during reproduction, the flag ELAP is viewed, and in the case of the overlap period, the first audio data (referred to as a first copy) and the first audio data are referred to. 2 (hereinafter referred to as a second copy) is separately decoded (eg, erasure-corrected) and output. If it is not an overlap period, decoding is performed using both the first copy and the second copy. Output. That is, during the non-overlap period, the same data is duplicatedly recorded as the first copy and the second copy. Therefore, referring to the error flag obtained by decoding the inner code, the first non-error data is referred to as the first copy. A code block of the outer code is selected from the copy and the second copy, and the outer code is corrected for this code block.

[Problems to be solved by the invention]

However, when the flag ELAP is wrong or cannot be obtained, the first
And decoding using the second audio data. In this case, there is a problem that the two data are mixed and erroneous decoding is performed, thereby deteriorating the quality of the reproduced audio signal.

Therefore, an object of the present invention is to provide a first method when a flag indicating an overlap period is incorrect or cannot be obtained.
Another object of the present invention is to provide a digital information signal reproducing apparatus which prevents decoding using both of the first and second audio data and eliminates the possibility of erroneous correction.

[Means for solving the problem]

According to the present invention, the same first digital audio signal and second digital audio signal are duplicatedly recorded on the recording medium, and during the overlap period, the first digital audio signal and the second digital audio signal are duplicated. In a digital information signal reproducing device in which only one of signals is rewritten, a first flag ELAP1 and a second flag indicating an overlap period separated from the first and second digital audio signals, respectively. While holding ELAP2,
In addition to holding memories 57 and 58 that are reset at regular intervals, and third and fourth flags EDT1 and EDT2 indicating whether the first flag ELAP1 and the second flag ELAP2 have been correctly obtained, A first digital audio signal and a first digital audio signal according to first, second, third, and fourth flags ELAP1, ELAP2, EDT1, and EDT2 stored in memories 57 to 60; And a circuit 62 for selectively outputting the second digital audio signal.

[Action]

The flags separated from the reproduction data of the first copy and the reproduction data of the second copy are stored in the memories 57 and 58, respectively. Memory 57,58
The flag ELAP1 and the flag ELAP2 stored respectively in the first period become “1” during the overlap period, and become “0” during the non-overlap period. Also, flags EDT1 and EDT2 indicating whether or not the flags are correctly set are stored in the memories 59 and 60. These flags EDT1 and EDT2 become "0" when the flags ELAP1 and ELAP2 are correctly taken, and become "1" when the ELAP1 and ELAP2 cannot be taken.

The above-mentioned flags ELAP1, ELAP2, EDT1, EDT2 are supplied to the ROM, and a signal for controlling the selector 62 is formed. And
Only when ELAP1 or ELAP2 is "1" and EDT1 or EDT2 is "0", the first copy and the second copy are separately decoded and the cross-fade processing is performed assuming that the overlap period is set. When EDT1 and EDT2 are “0” and ELAP1 and ELAP2 are “0”, it is determined that it is not an overlap period,
Decoding is performed using both the first copy and the second copy. Otherwise, decryption using both is not performed. Therefore, despite the overlap period, the first
By performing decryption using both the copy and the second copy, it is possible to prevent the two from being mixed and generating an abnormal reproduction sound.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to reproduction of audio data of a digital VTR will be described with reference to the drawings.

 This description is made in the following order.

a. Configuration of recording and playback circuits of digital VTR b. Scanner and track format c. Overlap editing d. First and second copy selection circuit a. Configuration of recording and playback circuits of digital VTR 1 shows a configuration of a recording side of a digital VTR. In FIG. 1, 1 is an input terminal for an analog audio signal, 2 is an input terminal for a digital audio signal, 3
Is an analog / digital interface. A buffer memory 4 is connected to the interface 3, and the buffer memory 4 compresses the time axis of the audio data and converts the audio data into an order of a block structure. Reference numeral 5 indicates an outer code encoder, and reference numeral 6 indicates a shuffling circuit. The outer code encoder 5 encodes an outer code that is an error correction code. The shuffling circuit 6 is constituted by a memory and rearranges the order of data.

7 is an input terminal for an analog video signal, 8 is an input terminal for a digital video signal, and 9 is an analog / digital interface. The output signal of the interface 9 is supplied to the channel demultiplexer 10 and
Converted to the channel data series. The data sequence of each channel is supplied to the outer code encoder 11, and is subjected to outer code encoding processing. The output data of the encoder 11 is supplied to the intra-sector shuffling circuit 12, and the order of the data in the sector is rearranged.

Synchronization and ID with audio data from shuffling circuit 6 and video data from intra-sector shuffling circuit 12
The synchronization signal and the ID signal from the generation circuit 13 are supplied to the data multiplexer 14. The output signal of the data multiplexer 14 is supplied to the inner code encoder 15. The inner code encoder 15 performs a process of encoding the inner code. Output signal of inner code encoder 15 is channel encoder 16
And undergoes a process of encoding a mirror square code. The output signal of the channel encoder 16 is
Through the output terminal 18.

The output terminal 18 is connected to a rotary head. The recording data is recorded on the magnetic tape by the rotating head.
The data reproduced from the magnetic tape is supplied to the reproducing amplifier 22 from the input terminal 21 in FIG. 2 by the rotating head. The output signal of the reproduction amplifier 22 is supplied to the channel decoder 23, where the mirror square code is decoded.

The output signal of the channel decoder 23 is supplied to the synchronization detection circuit 24, and the synchronization signal is detected. Sync detection circuit 24
Is supplied to the inner code decoder 25 to decode the inner code. An output signal of the inner code decoder 25 is supplied to a switch circuit 26, where audio data and video data are separated.

The audio data is supplied to the outer code decoder 28 after being deshuffled by the deshuffling circuit 27. The outer code is decoded by the outer code decoder 28 and stored in the memory.
Written to 29. Decoding of the outer code is, for example, erasure correction with reference to an error flag generated in decoding of the inner code. The memory 29 expands the time axis of the data.
The audio data read from the memory 29 is supplied to the error correction circuit 30, where the error data is corrected.
The output data of the error correction circuit 30 is supplied to an analog / audio interface 31, an analog audio signal is obtained at an output terminal 32, and a digital audio signal is obtained at an output terminal 33.

As will be described later, a first copy and a second copy selection circuit are provided between the deshuffling circuit 27 and the outer code decoder 28.

The above-described deshuffling circuit 27, outer code decoder 28,
The memory 29 is supplied with a start signal obtained from the start signal generation circuit 42. At the timing specified by the start signal, reading of the memory of the deshuffling circuit 27 is started, decoding of the outer code decoder 28 is started, and writing to the memory 29 is started.

The video data separated by the switch circuit 26 is written to the buffer memory 34. The video data read from the buffer memory 34 is transferred to the intra-sector deshuffling circuit 35.
Is supplied to the outer code decoder 36 via the. The error-corrected data from the outer code decoder 36 is supplied to the channel multiplexer 37, and the data of two channels is converted into the data of one channel. The output signal of the channel multiplexer 37 is supplied to an error correction circuit 38, where error data is corrected. The output signal of the error correction circuit 38 is supplied to an analog / digital interface 39. An analog video signal is obtained at the output terminal 40, and a digital video signal is obtained at the output terminal 41.

b. Scanner and Track Format FIG. 3 shows an example of a digital VTR scanner.
Four head chips H1 to H4 are attached to the drum 43 rotating in the direction of the arrow. Head chip H1 and
H2 approaches, head chips H3 and H4 approach, head chips H1 and H3 have a 180 ° facing distance, and head chip H
2 and H4 have a 180 ° facing distance. On the peripheral surface of the drum 43, a magnetic tape 44 with a winding angle slightly wider than 180 ° is used.
Is wound diagonally. A set of head chips H1 and H2 and a set of head chips H3 and H4 alternately contact the magnetic tape 44. The angle of the gap between the head chips H1 and H2 is made different, and similarly, the angle of the gap between the head chips H3 and H4 is made different, so that azimuth recording is performed.

In the case of a video signal having a field frequency of 60 Hz as in the NTSC system, one field is divided into three segments and one field is divided into three segments.
The segment is recorded as two tracks. That is, a video signal for one field is recorded on the magnetic tape 44 as three segments and six tracks.

FIGS. 4A and 4B show a track format formed on the magnetic tape 44. FIG. FIG. 4A shows a magnetic tape 44.
4B shows a track pattern viewed from the magnetic surface side of FIG.
Shows one track in the order of head scanning. A0, A1, A2, and A3 indicate audio sectors, and these audio sectors A0 to A3 are arranged at track ends. The same content of audio data is recorded twice at different ends of two tracks. That is, the same audio data is recorded at each of the end of the previous track on the head separation side and the end of the current track on the head entry side. The first audio data recorded at the end on the head separation side is called a first copy, and the second audio data recorded on the head entry side is called a second copy. The video sector is located in the center of the track.
T0 and T1 are track numbers, and S0 is a segment number.

As shown in FIG. 4B, an editing gap is provided between the audio sectors and between the audio sector and the video sector. Audio sectors A0 to A3 are 6
The video sector is composed of 204 sync blocks. In FIG. 4B, T is
E indicates a track preamble, E indicates an edit gap preamble, and P indicates a post preamble.

As shown in FIG. 5, each sync block has a length of 190 bytes, and a 2-byte synchronization pattern is added at the beginning. Next, a 2-byte ID pattern is added,
The ID code and the 85-byte data are encoded with an inner code to form an 8-byte check code. Also, an 8-byte check code is added to the other 85-byte data to form an inner code block.

The inner code is common to audio data and video data. A Reed-Solomon code is used as the inner code and the outer code. The number of samples of audio data recorded in each audio sector is 266 samples or 267 samples. FIG. 6 shows blocks included in one audio sector. Numerals 0 to 266 indicate audio sample numbers, PV0 to PV3 indicate outer code check codes, and AUX0 to AUX3 indicate auxiliary words. These audio data, check code, and auxiliary code are shuffled. Auxiliary word AUX0
~ AUX3 consists of 20 bits, and the first 4 words of each auxiliary word
The bit is set to the flag ELAP. For the data rewritten during the overlap period, ELAP is set to F (hexadecimal notation), and otherwise set to 0 (hexadecimal notation).
In FIG. 6, the check code of the inner code is not shown. Although the bit length of one sample of the audio data is 20 bits, the encoding of the inner code uses one byte as one symbol.

c. Overlap Edit The overlap edit will be described with reference to FIGS. 7 and 8. As shown in FIG. 7, when changing audio data of a certain channel from old data to new data, an overlap period in which both exist is provided, and the old data is faded out during this overlap period, and the new data (broken line) is displayed. ) Is performed. Similarly, when returning from new data to old data, an overlap period is provided, and cross-fade processing is performed in the overlap period.

As described above, since the audio data is duplicatedly recorded as the first copy and the second copy, the overlap period can be formed by rewriting only one of the audio data. As shown in FIG. 7, the length of the overlap period is N to N + 4 or M to
It is a period of four segments of M + 4.

For example, when forming an in-point overlap period for the first channel, only the first copy from the Nth segment is rewritten with new audio data as shown in FIG. Similarly, only the first copy is rewritten over four segments, and (N +
4) When it comes to segments, both the first copy and the second copy are rewritten with new data. The flag ELAP1 of the first copy on the side rewritten with new data is set to F in the overlap period.

When forming the overlap period of the out point, as shown in FIG.
Only the copy remains the old data, and similarly, only the first copy is the old data over four segments.
In the (M + 4) segment, both the first copy and the second copy are rewritten with old data. In the overlap period, the flag ELAP2 of the second copy is set to F.

d. First copy and second copy selection circuit The first copy and second copy selection circuit shown in FIG. 9 is provided between the deshuffling circuit 27 and the outer code decoder 28 for data processing during the overlap period. Is provided.

In FIG. 9, audio data and auxiliary data whose inner code has been decoded are supplied to an input terminal denoted by reference numeral 51.
An error flag EF indicating the presence or absence of an error in these data is supplied to the input terminal indicated by. The first copy of the audio data from the input terminal 51 is the first copy data memory
The second copy is stored in the second copy data memory 54.
Is stored in Further, the error flag of the first copy is set to the first
The copy flag is stored in the copy EF memory 55, and the error flag of the second copy is stored in the second copy EF memory 56.

Regarding the flag ELAP indicating the overlap period in the data, the one related to the first copy is stored in the first copy ELAP memory 57, and the one related to the second copy is stored in the second copy ELAP memory 58. These ELAP memories 57,5
8 is supplied with an error flag. Further, the flag E
ELAP detection circuits 59 and 60 for detecting whether the LAP has been removed.
Are provided for each of the first copy and the second copy. An error flag is supplied to these ELAP detection circuits 59 and 60, and a reset pulse is supplied from a terminal 61.

The first copy from the first copy data memory 53 and the second copy from the second copy data memory 54 are supplied to the selector 62, and one audio data selected by the selector 62 is taken out to the output terminal 63. The selector 62
It is controlled by a control signal generated by the ROM 65. ROM
The output signal of the ROM 64 and the error flags EF1 and EF2 are supplied to 65, and the flags ELAP1, ELAP2, and the flags EDT1 and EDT2 stored in the memories 57, 58, and 60 are supplied to the ROM 64. You. Further, an error flag relating to the data selected at the output terminal 66 is extracted from the ROM 65.

FIG. 10 shows the first copy ELAP memory 57 and the first copy EL
6 shows an exemplary configuration of an AP detection circuit 59. That is, the ELAP memory 57
Is constituted by a flip-flop 71, and an ELAP detection circuit 59
Are constituted by the flip-flop 72. Data from the terminal 51 is supplied as a data input of the flip-flop 71, and data “0” is always supplied as a data input of the flip-flop 72. A flag ELAP1 indicating whether or not an overlap period is obtained from the flip-flop 71,
A flag EDT1 indicating whether or not ELAP has been obtained is obtained from the flip-flop 72.

A common reset pulse is supplied from a terminal 61 to a clear terminal of the flip-flop 71 and a preset terminal of the flip-flop 72, and a clock CK is commonly supplied.
The reset pulse occurs after reading the data,
This reset pulse causes the output of flip-flop 71
ELAP1 becomes “0”, and the output EDT1 of the flip-flop 72 becomes “0”.

Further, the error flag EF1 of the first copy and the load pulse are supplied to the OR gate 73, and the output signal of the OR gate 73 is supplied to the flip-flops 71 and 72 as a load pulse. The error flag EF1 becomes “0” when it is determined that there is no error by decoding the inner code, and becomes “1” when it is determined that there is an error. Therefore, the flip-flops 71 and 72 are loaded by the load pulse only when it is determined that there is no error. The load pulse goes low at the position of ELAP1 in the data.

The error-free flag ELAP1 is loaded into the flip-flop 71 configuring the ELAP memory 57 described above. Young
When an error ELAP1 is input, ELAP1 is set to “0”
Becomes On the other hand, the flip-flop 72 generates a flag EDT1 which becomes “0” when a load pulse is generated, that is, when the flag is removed, and becomes “1” when it is not.

Second copy ELAP memory 58 and second copy ELAP detection circuit
Reference numeral 60 is the same as the configuration relating to the first copy shown in FIG. Therefore, the meanings of the flags and the detection signals obtained from these memories are as follows.

ELAP1, ELAP2: When "0", it is not the overlap period.

ELAP1, ELAP2: “1” indicates an overlap period.

EDT1, EDT2: When "0", the flags ELAP1, ELAP2 were correctly taken.

EDT1, EDT2: When "1", flags ELAP1, ELAP2 cannot be taken.

ROM64 reads 4 from the above flag as shown in FIG.
Generates an output signal to specify the type of mode (double, F / S, S, F). These modes are described below.

Double: Flag EL for both the first copy and the second copy
AP1 and ELAP2 are correctly obtained, and ELAP1 and ELAP2 are “0”. Since this state is not an overlap period, the first state
A signal for selecting one of the copy and the second copy which is not an error (if both have an error, any signal may be used).
Occurs in M65.

F / S: One of the flags of the first copy and the second copy is correctly set, and ELAP1 or ELAP2 is "1". Since it is the overlap period, a signal for outputting both the first copy and the second copy is generated in the ROM 65. Outer code decoder 2
At 8, the first copy and the second copy are decrypted separately,
Cross-fade processing is performed by the decrypted first copy and second copy.

S ((01) for the first copy, (00) for the second copy)... The flag ELAP1 of the first copy cannot be correctly set, the flag ELAP2 of the second copy can be correctly set, and ELAP2
Is “0”. In this case, since it is not known whether ELAP1 of the first copy is “0” or “1”, decoding using both is not performed. Also, since it is considered that almost no data has been taken for the first copy for which the flag could not be taken, the second copy was used.
A signal for selecting a copy is generated from the ROM 65.

F: The first copy flag ELAP2 could not be obtained correctly,
The copy flag ELAP1 is correctly taken and (ELAP1:
“0”). Since it is not known whether ELAP2 of the second copy is "0" or "1", decoding using both is not performed. In addition, for the second copy for which the flag could not be taken, it is considered that data has hardly been taken, so that a signal for selecting the first copy is generated from the ROM 65.

S ((01) for the first copy, (01) for the second copy)... The flag ELAP1 of the first copy and the flag ELAP2 of the second copy cannot be correctly obtained. In this case, since it is considered that almost no data can be obtained, here, a signal for selecting the second copy only and giving the priority to the second copy is a RO signal.
Generated from M65.

As described above, only in the case of, the overlap period is determined, and cross-fade processing is performed after decoding of the outer code.

FIG. 12A shows the reproduced signal, and FIG. 12B shows the timing of decoding the outer code. The decoding of the outer code consists of one outer code block consisting of 12 bytes per channel.
85 are decrypted. The decoding of the outer code is performed as shown in FIGS. 12C to 12F in accordance with each mode described above.

FIG. 12C shows the F / S mode, in which both the first copy and the second copy of each channel are respectively decoded. Twelfth
FIG. D shows the mode F, in which only the first copy of each channel is decoded. FIG. 12E shows the mode of S, in which only the second copy of each channel is decoded. Thus, when decoding only one copy, the data at the later timing is not actually output, but the same one is duplicated twice for decoding the first copy and the second copy separately. Decrypted. FIG. 12F shows a double mode, in which the error-free one of the first copy and the second copy is selectively decoded byte by byte.

〔The invention's effect〕

According to the present invention, both the first copy and the second copy are separately decoded only when the flag separated from the reproduction data is correctly obtained and the flag indicates the overlap period, and then the cross-fade processing is performed. Is performed, the data is decrypted using the first copy and the second copy, even though the portion has been overlap-edited, thereby preventing data from being mixed.

[Brief description of the drawings]

FIG. 1 shows a digital VT to which the present invention can be applied.
FIG. 2 is a block diagram on the reproducing side of an example of a digital VTR to which the present invention can be applied, FIG. 3 is a plan view showing the configuration of the scanner, and FIG.
FIG. 5 is a schematic diagram showing a format of a digital VTR on a tape, FIG. 5 is a schematic diagram showing a configuration of a sync block, FIG. 6 is a schematic diagram showing a block arrangement of audio data,
7 and 8 are schematic diagrams used to explain the overlap editing, FIG. 9 is a block diagram of the first copy and second copy selection circuits, and FIGS. 10 and 11 are ELAP memories and ELAP detection circuits. FIG. 12 is a block diagram of an example and a schematic diagram used for the description, and FIG. 12 is a timing chart of a decoding operation of an outer code. Explanation of main symbols in the drawings 21: input terminal of reproduction data, 27: deshuffling circuit,
28: outer code decoder, 29: memory, 30: error correction circuit, 5
3, 54: data memory, 57, 58: ELAP memory, 59, 60: ELAP detection circuit, 62: selector.

Claims (1)

(57) [Claims] 1. A first digital audio signal and a second digital audio signal identical to each other are double-recorded on a recording medium, and during the overlap period, the first digital audio signal and the second digital audio signal are duplicated.
A digital information signal reproducing apparatus for rewriting only one of the digital audio signals, wherein the first and second digital audio signals each have an overlap period separated from the first and second digital audio signals.
And a memory that is reset at regular intervals, and a third flag and a fourth flag that indicate whether the first and second flags have been correctly obtained. Along with
A memory reset at regular intervals; and a first digital audio signal and a second digital audio signal according to the first, second, third, and fourth flags stored in the memory. And a circuit for selectively outputting a digital information signal.