JPH01276469A - Digital information signal reproducing device - Google Patents

Abstract

PURPOSE:To prevent respective data from being mixed by separately decoding respective copies and after that, executing cross fade processing only when a flag in reproducing data shows an overlap period. CONSTITUTION:The flags to be respectively separated from the reproducing data of respective first and second copies are stored in memories 57 and 58. Then, storing flags ELAP1 and ELAP2 go to be '1' in the overlap period and flags EDT1 and EDT2, which show the propriety of the flag, are stored in memories 59 and 60. The flags ELAP1, ELAP2, EDT1 and EDT2 are supplied to ROMs 64 and 65 and the control signal of a selector 62 is formed. Only when the ELAP1 or 2 is '1' and the EDT1 or 2 is '0', the respective copies are separately decoded as the overlap period and the cross face processing is executed. As a result, an abnormal reproducing tone is prevented from being generated by the mixing of the respective copies.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital information signal reproducing device that is applied to processing audio signals of a digital VTR that records/reproduces digital video signals and digital audio signals.

[Summary of the invention]

In this invention, the first digital audio signal and the second digital audio signal, which are the same as each other, are recorded in duplicate on the recording medium, and during the overlap period, the first digital audio signal and the second digital audio signal are In a digital information signal reproducing device configured to rewrite only one of the first and second digital audio signals, a first flag and a second flag are held that indicate an overlap period separated from each of the first and second digital audio signals. In addition, a memory that is reset at regular intervals, and a memory that holds a third flag and a fourth flag indicating whether or not the first and second flags are correctly obtained, and that is reset at regular intervals. By providing a circuit that selectively outputs the first digital audio signal and the second digital audio signal according to the first, second, third, and fourth flags stored in the memory, the overlap can be achieved. It is possible to prevent mixed decoding of the first digital audio signal and the second digital audio signal when the first and second flags indicating the period are incorrect or cannot be obtained.

[Conventional technology]

For example, a digital VTR that records/plays composite digital video signals and digital audio signals.
One of these is the ability to record digital audio signals in duplicate. In such a digital VTR, only one digital audio signal is rewritten during editing to form a period in which new audio data and old audio data overlap, and cross-fade processing is performed during this overlap period. During the overlap period, a flag ELAP is recorded in the data, and during playback, this flag ELAP is checked.In the overlap period, the first audio data (referred to as the first copy) and the second audio data The audio data (referred to as the second copy) is decoded (for example, erasure corrected) and output separately, and if it is not an overlap period, the audio data (referred to as the second copy) is decoded and output using both the first copy and the second copy. .

That is, when there is no overlap period, the same data is recorded twice as the first copy and the second copy, so by referring to the error flag obtained by decoding the inner code, the non-error data is recorded in the first copy. and the second copy to form a code block of the outer code, and the outer code is corrected with respect to this code block.

[Problem to be solved by the invention]

However, if the flag ELAP is incorrect or cannot be obtained, the first and second audio data will be used for decoding despite the overlap period, and in that case, the two data will be mixed. However, there is a problem in that erroneous decoding occurs and the quality of the reproduced audio signal is impaired.

Therefore, an object of the present invention is to prevent decoding using both first and second audio data when a flag indicating an overlap period is incorrect or cannot be obtained, thereby reducing the risk of erroneous correction. An object of the present invention is to provide a digital information signal reproducing device in which the

[Means to solve the problem]

In this invention, the first digital audio signal and the second digital audio signal, which are the same as each other, are recorded in duplicate on the recording medium, and during the overlap period, the first digital audio signal and the second digital audio signal are In a digital information signal reproducing device configured to rewrite only one of the first and second digital audio signals, a first flag ELAPI and a second flag ELAP2 are set to indicate an overlap period separated from each of the first and second digital audio signals. Memory 57.58 that is held and reset at regular intervals
and a memory 59.60 that holds a third flag EDTI and a fourth flag EDT2 indicating whether or not the first flag LAP1 and the second flag ELAP2 are correctly obtained, and is reset at regular intervals. , the first, second, third and fourth flags ELAPI, ELAP2゜EDTI, E stored in the memories 57-60.
A circuit 62 is provided that selectively outputs the first digital audio signal and the second digital audio signal according to the DT2.

[Effect]

Flags separated from the reproduced data of the first copy and the second copy are stored in the memories 57 and 58, respectively. memory 5
7. Flags ELAPI and EL stored in 58 respectively
AP2 becomes "1" during the overlap period, and becomes "0" when it is not the overlap period. Further, flags EDTI and EDT2 indicating whether the flag has been set correctly are stored in the memories 59 and 60. These flags EDT
I and EDT2 become 10" when the flags ELAPI and ELAP2 are correctly set, and become "1#" when the flags ELAPI and ELAP2 cannot be set.

The above flags ELAPI, ELAP2. EDT1, ED
T2 is supplied to the ROM to form a signal that controls selector 62. Then, only when ELAPl or ELAP2 is “1” and EDTI or EDT2 is “0”,
Assuming that it is an overlap period, the first copy and the second copy
The copies are decoded separately and cross-fade processing is performed. When EDTl and EDT2 are 00”, ELAP
When 1 and ELAP2 are "0", it is determined that there is no overlap period, and decoding is performed using both the first copy and the second copy. Otherwise, decoding using both is not possible. Therefore, even in the overlap period, decoding can be performed using both the first copy and the second copy, and it is possible to prevent the two copies from being mixed together and producing abnormal reproduced sound.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to the reproduction of audio data of a digital VTR will be described with reference to the drawings.

This description is given in the following order.

a. Configuration of the recording circuit and playback circuit of the digital VTR, scanner and track format C, overlap editing d, first copy and second copy selection circuit a. Configuration of the recording circuit and playback circuit of the digital VTR. The configuration of the recording side of a digital VTR is shown. In FIG. 1, 1 is an analog audio signal input terminal, 2 is a digital audio signal input terminal, and 3 is an analog/digital interface. A buffer memory 4 is connected to the interface 3, and the buffer memory 4 compresses the time axis of the audio data and converts it into the order of the block structure.

5 indicates an outer code encoder, and 6 indicates a shuffling circuit. The outer code encoder 5 encodes the outer code, which is an error correction code.

The shuffling circuit 6 is constituted by a memory and rearranges the order of data.

7 is an input terminal for an analog video signal, 8 is an input terminal for a digital video signal, and 9 is an analog/digital interface. The output signal of INK-7 ACE 9 is supplied to channel day multiplexer 10,
Converted to a channel data series. The data series of each channel is supplied to the outer code encoder 11 and subjected to outer code encoding processing. The output data of the encoder 11 is supplied to the intra-sector shirtling circuit 12, and the order of data within the sector is rearranged.

The audio data from the shuffling circuit 6 and the video data from the intra-sector shuffling circuit 12 are synchronized and
The synchronization signal and ID signal from the 0-shot generation path 13 are supplied to the data multiplexer 14. The output signal of data multiplexer 14 is supplied to inner code encoder 15 . The inner code encoder 15 performs inner code encoding processing. The output signal of the inner code encoder 15 is supplied to the channel encoder 16 and subjected to mirror square code encoding processing. An output signal from the channel encoder 16 is taken out to an output terminal 18 via a recording amplifier 17.

A rotary head is connected to the output terminal 18. Recorded data is recorded onto the magnetic tape by the rotating head.

Data reproduced from the magnetic tape by the rotary head is supplied to a reproduction amplifier 22 from an input terminal 21 in FIG. The output signal of the reproduction amplifier 22 is supplied to the channel decoder 23, and the Miller square code is decoded.

The output signal of the channel decoder 23 is sent to the synchronization detection circuit 24.
, and the synchronization signal is detected.

The output signal of the synchronization detection circuit 24 is supplied to the inner code decoder 25, and the inner code is decoded. Inner code decoder 25
The output signal is supplied to the switch circuit 26, and audio data and video data are separated.

The audio data is de-shuffled by the de-shuffling circuit 27 and then supplied to the outer code decoder 28 . The outer code is decoded by the outer code decoder 28 and written into the memory 29.

The decoding of the outer code is, for example, erasure correction with reference to an error flag generated in the decoding of the inner code.

The memory 29 expands the time axis of the data.

The audio data read from the memory 29 is supplied to the error correction circuit 30, and error data is corrected. The output data of the error correction circuit 3o is supplied to the analog/audio interface 31, and the output terminal 32
An analog audio signal is obtained at the output terminal 33, and a digital audio signal is obtained at the output terminal 33.

As will be described later, first copy and second copy selection circuits are provided between the deshuffling circuit 27 and the outer code decoder 28.

The above-mentioned de-shuffling circuit 27 and outer code decoder 28
, the memory 29 is supplied with a start signal obtained from a start signal generation circuit 42.

At the timing defined by this start signal, the deshuffling circuit 27 starts reading the memory, the outer code decoder 28 starts decoding, and furthermore, the writing into the memory 29 starts.

The video data separated by the switch circuit 26 is written into the buffer memory 34. Video data read from the buffer memory 34 is supplied to an outer code decoder 36 via an intra-sector deshuffling circuit 35. The error-corrected data from the outer code decoder 36 is supplied to the channel multiplexer 37, and the two-channel data is converted into one-channel data. The output signal of the channel multiplexer 37 is sent to the error correction circuit 38.
The error data is corrected.

The output signal of the error correction circuit 38 is provided to an analog/digital interface 39. An analog video signal is obtained at an output terminal 40, and a digital video signal is obtained at an output terminal 41.

b. Scanner and track format FIG. 3 shows an example of a scanner for a digital VTR. Four head chips H1 to H are mounted on the drum 43 rotating in the direction of the arrow.
4 is installed. Head chips H1 and H2 are close to each other, head chips H3 and H4 are close to each other, head chips H1 and H3 have a facing interval of 180@, and head chips H2 and H4 have a facing interval of 180°. A magnetic tape 44 is obliquely wound around the circumferential surface of the drum 43 at a winding angle slightly wider than 180'. A set of head chips H1 and H2 and a set of head chips H3 and H4 alternately come into sliding contact with the magnetic tape 44.

The angles of the gap between the head chips H1 and H2 are made different, and similarly the angles of the gap between the head chips H3 and H4 are made different to perform azimuth recording.

In the case of a video signal with a field frequency of 607, such as NTSC, one field is divided into three segments, and one segment is recorded as two tracks. That is, the video signal for one field is recorded on the magnetic tape 144 as three segments and six tracks.

4A and 4B show track formats formed on the magnetic tape 44. FIG. 4A shows the track format formed on the magnetic tape 44.
FIG. 4B shows a track pattern seen from the magnetic surface side of No. 4, and FIG. 4B shows one track in the order of scanning by the head. AO, Al, A2. A3 indicates an audio sector, and these audio sectors AO to A3 are arranged at the end of the track. Furthermore, the same content of audio data is recorded twice at different ends of two tracks.

That is, audio data having the same content is recorded on the end of the previous track on the head separation side and the end of the current track on the head entry side. The first audio data recorded on the end on the head separation side will be referred to as a first copy, and the second audio data recorded on the head entry side will be referred to as a second copy. The video sector is located in the center of the track. To, Tl are track numbers, S
O is the segment number.

As shown in FIG. 4B, editing gaps are provided between audio sectors and between audio and video sectors. Audio sectors AO to A3 each consist of 6 sync plotters, and the video sector consists of 20 sync plotters.
Consists of 4 sink blocks. In Figure 4B, T
indicates track preamble, E indicates edit gap preamble, and P indicates post preamble.

As shown in FIG. 5, each sync block has a length of 190 bytes, and a 2-byte synchronization pattern is added to the beginning. Next, a 2-byte ID pattern is added, and this ID pattern and 85-byte data are encoded with an inner code to form an 8-byte check code. Furthermore, an 8-byte check code is added to the other 85-byte data to form an inner code block.

The inner code is common to audio data and video data. Reed-Solomon codes are used as the inner code and outer code. The number of samples of audio data recorded in each audio sector is 266 or 267 samples. FIG. 6 shows blocks included in one audio sector. The numbers from 0 to 266 indicate the audio sample number, PVO-PV3
indicates the outer code check code, AUXO-AUX3
indicates an auxiliary word, these audio data, check code and auxiliary word are shuffled. The auxiliary words AUXO-AUX3 consist of 20 bits, and the first 4 bits of each auxiliary word are used as a flag ELAP. For data rewritten during the overlap period, ELAP is set to F (hexadecimal display), and for other data, it is set to 0 (hexadecimal display). In addition, in Fig. 6, the check code of the inner code is shown. is omitted. Although the bit length of one sample of audio data is 20 bits, the inner code is encoded using one byte as one symbol.

C. Overlap Editing Overlap editing will be explained with reference to FIGS. 7 and 8. As shown in Figure 7, when changing the audio data of a channel from old data to new data, an overlap period in which both exist is provided, the old data is faded out during this overlap period, and the new data (indicated by the broken line) is A cross-fade process is performed to fade in the image. Similarly, when returning from new data to old data, an overlap period is provided, and cross-fade processing is performed during this overlap period.

As mentioned above, since the audio data is recorded twice as the first copy and the second copy, an overlap period can be formed by rewriting only one of the audio data. The length of the overlap period is NNN+4 or M-N as shown in FIG.
It is assumed to be a 4-segment period of +4.

For example, when forming an in-point overlap period for the first channel, as shown in FIG.
Only the first copy of the Nth segment is rewritten with new audio data. Over four segments, only the first copy is rewritten in the same way, and when the (N+4) segment is reached, both the first copy and the second copy are rewritten with new data. The flag ELAPI of the first copy on the side that has been rewritten with new data is set to F during the overlap period.

When forming the out-point overlap period, as shown in FIG. 8, only the first copy from the Mth segment is kept as the old data, and similarly over the four segments, only the first copy is kept as the old data. . C
M+4) segment, both the first copy and the second copy are rewritten with old data. During the overlap period, the flag ELAP2 of the second copy is set to F.

d. First copy and second copy selection circuits For processing data during the overlap period, the first copy and second copy selection circuits shown in FIG. 9 are installed between the deshuffling circuit 27 and the outer code decoder 28. provided.

In FIG. 9, audio data and auxiliary data whose inner codes have been decoded are supplied to an input terminal indicated by 51;
An error flag EF indicating the presence or absence of an error in these data is supplied to an input terminal indicated by 2. A first copy of audio data from input terminal 51 is stored in first copy data memory 53, and a second copy is stored in second copy data memory 54. Further, the error flag of the first copy is stored in the first copy EF memory 55, and the error flag of the second copy is stored in the second copy EF memory 56.

The flag ELAP indicating the overlap period in the data is related to the first copy.
The information regarding the second copy is stored in the second copy ELAP memory 58. These ELAP memories 57, 58 are supplied with error flags. Further, ELAP detection circuits 59 and 60 are provided for each of the first copy and the second copy to detect whether the flag ELAP has been cleared. These LAP detection circuits 59 and 60 are supplied with an error flag and a reset pulse from a terminal 61.

The first copy from the first copy data memory 53 and the second copy from the second copy data memory 54 are selected by the selector 6.
2 and selected by the selector 62 is taken out to the output terminal 63. The selector 62 is controlled by a control signal generated by the ROM 65.

The ROM65 is supplied with the output signal of the ROM64 and the error flags EFI and EF2, and the ROM64 is supplied with the flags ELAPI, ELAP2, and the flags EDTI and ED stored in the above-mentioned memories 57.58 and 59.60, respectively.
T2 is supplied. In addition, the output terminal 66 from the ROM 65
Error flags related to the data selected are retrieved.

FIG. 10 shows an example of the configuration of the first copy ELAP memory 57 and the first copy ELAP detection circuit 59, that is,
The ELAP memory 57 is composed of a flip-flop 71, and the ELAP detection circuit 59 is composed of a flip-flop 72.

Data from the terminal 51 is supplied as a data input to the flip-flop 71, and a "0" data is always supplied as a data input to the flip-flop 72. A flag ELAPI indicating whether it is an overlap period is obtained from the flip-flop 71, and EL is obtained from the flip-flop 72.
A flag EDT1 indicating whether the AP has been acquired is obtained.

A common reset pulse is supplied from the terminal 61 to the clear terminal of the flip-flop 71 and a preset terminal of the flip-flop 72, and a clock CK is also supplied in common. A reset pulse is generated after reading the data, and this reset pulse causes the output ELAPI of the flip-flop 71 to become "0" and the output EDT1 of the flip-flop 72 to become 'Om.

Further, the error flag EFI of the first copy and the load pulse are supplied to the OR gate 73, and the output signal of the 6R gate 73 is supplied to the flip-flops 71 and 72 as the load pulse. The error flag EFI becomes "0" when it is determined that there is no error by decoding the inner code, and becomes "1" when it is determined that there is an error.
Therefore, flip-flops 71 and 72 are loaded by the load pulse only when it is determined that there is no error. The load pulse becomes low level at position t of ELAPI(7) in the data.

The error-free flag ELAP1 is loaded into the flip-flop 71 constituting the ELAP memory 57 described above. If ELAPl, which is an error, is input, ELAPI becomes 10''. On the other hand, the flip-flop 72 becomes 0 when a load pulse occurs, that is, when the flag is removed; otherwise, it becomes 0. A flag EDT1 that becomes "1" is generated.

Second copy ELAP memory 58 and second copy ELAP
The detection circuit 60 has the same configuration as that related to the first copy shown in FIG. Therefore, the meanings of the flags and detection signals obtained from these memories are as follows.

ELAPI, ELAP2: “When 0#, it is not an overlap period.

ELAPI, ELAP2: When "1", it is an overlap period.

EDTI, EDT2: When “0”, flag ELAP1
, ELAP2 was obtained correctly.

EDTI, EDT2: When “1”, flag E LAP
l, I can't get ELAP2.

The ROM 64 has four types of modes (double, F/S, S, etc.) as shown in FIG. 11 based on the above flags.

generate an output signal for specifying F). These modes are explained below.

■Double: The flags ELAPI and ELAP2 of both the first copy and the second copy are set correctly, and ELAPI and ELAP2 are "0". Since this state is not an overlap period, a signal is generated in the ROM 65 to select which one of the first copy and second copy is not in error (if both are in error, either one is fine).

■F/S...When the flag of either the first copy or the second copy is set correctly and ELAPI or ELAP2 is "1#." Since it is an overlap period, both the first copy and the second copy are A signal to be output is generated in the ROM 65. In the outer code decoder 28, the first copy and the second
The copies are decoded separately, and a cross-fade process is performed using the decoded first and second copies.

■S ((01) for the first copy, (00) for the second copy)...Flag ELAP of the first copy
1 cannot be set correctly, the flag ELAP2 of the second copy is set correctly, and ELAP2 is "0". In this case, it is not known whether ELAPI of the first copy is "O" or "1", so decryption using both is not performed, and most of the data is also removed from the first copy for which the flag was not removed. Since it is assumed that the second copy is not selected, a signal is generated from the ROM 65 to select the second copy.

■F...Flag ELAP2 of the second copy is not set correctly, flag ELAPI of the first copy is set correctly, and (ELAPI: "01"), ELAP of the second copy
Since it is not known whether 2 is "0" or '12, decoding using both is not performed. Furthermore, since it seems that almost no data has been captured in the second copy for which the flag has not been cleared, a signal for selecting the first copy is generated from the ROM 65.

■S ((01) for the first copy, (01) for the second copy)...Flag ELAP of the first copy
The flag ELAP2 of the first and second copies cannot be set correctly. In this case, since it seems that almost no data has been acquired, the ROM 65 generates a signal to select only the second copy, giving priority to the second copy.

As described above, only in the case (2), it is determined that it is an overlap period, and cross-fade processing is performed after the outer code is decoded.

FIG. 12A shows the reproduced signal, and FIG. 12B shows the timing of decoding the outer code. In the decoding of the outer code, 85 outer code blocks each consisting of 12 bytes are decoded for one channel. This outer code is decoded as shown in FIGS. 12C to 12F according to each of the above-mentioned modes.

FIG. 12C is the F/S mode in which both the first and second copies of each channel are decoded, respectively. The twelfth diagram is mode F, in which only the first copy of each channel is decoded. FIG. 12E is the S mode in which only the second copy of each channel is decoded. In this way, when only one copy is decoded, the data at the later timing is not actually output, but in case the first copy and the second copy are decoded separately, the data at the later timing is not actually output.
decrypting the same thing twice. FIG. 12F shows a double mode, in which the first copy and the second copy with no errors are selectively decoded one byte at a time.

〔Effect of the invention〕

According to this invention, only when the flag separated from the reproduced data is correctly set and the flag indicates an overlap period, both the first copy and the second copy are decoded separately, and then cross-fade processing is performed. Therefore, even though it is an overlap edited part, the first
The copy and the second copy can be used to decrypt and prevent the data from being mixed up.

[Brief explanation of the drawing]

Figure 1 shows a digital V to which this invention can be applied.
FIG. 2 is a block diagram of the recording side of an example of a TR, FIG. 2 is a block diagram of the reproduction side of an example of a digital VTR to which the present invention can be applied, and FIG. 3 is a plan view showing the configuration of a scanner.
Figure 4 is a route map showing the format on a digital VTR tape, Figure 5 is a route map showing the configuration of the sync block, Figure 6 is a route map showing the block arrangement of audio data, and Figures 7 and 8. is a route map used to explain overlap editing, FIG. 9 is a block diagram of the first copy and second copy selection circuits, and FIGS. 10 and 11 are block diagrams of an example of the ELAP memory and ELAP detection circuit and their explanation. The route map used in FIG. 12 is a timing chart of the outer code decoding operation. Explanation of main symbols in the drawings 21: Reproduction data input terminal, 27: Deshuffling circuit, 28: Outer code decoder, 29: Memory, 30: Error correction circuit, 53.54: Data memory, 57.58: ELAP Memory, 59.608 ELAP detection circuit, 62: Selector. Agent Patent Attorney Tadashi Sugiura Chiji'W + N N+4 M
M+4-$1 copy, Derm Fang 2] Pea tail handshake 10
Figure 9: 7 ohmas on the top of the top, Figure 4: 4-year-old child - Tough 0, Tsukura Otsu! Figure 6 Sync file lock format Figure 5

Claims (1)

[Claims] A first digital audio signal and a second digital audio signal, which are the same as each other, are recorded in duplicate on a recording medium, and in an overlap period, the first digital audio signal and the second digital audio signal are In a digital information signal reproducing device configured to rewrite only one of the two digital audio signals, a first digital audio signal indicating that the first digital audio signal is an overlap period separated from each of the first and second digital audio signals.
and a second flag, as well as a memory that is reset at regular intervals, and a third flag and a fourth flag that indicate whether the first and second flags have been obtained correctly. With,
a memory that is reset at regular intervals, and the first digital audio signal and the second digital audio signal according to the first, second, third, and fourth flags stored in the memory; 1. A digital information signal reproducing device comprising a selective output circuit.