JP2789598B2 - Digital information signal processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information signal processing apparatus which is applied to the processing of an audio signal of a digital VTR for recording / reproducing a digital video signal and a digital audio signal.

[Summary of the Invention]

According to the present invention, in a digital information signal processing device in which one sample of a digital information signal is processed by using a symbol having a bit length obtained by dividing the sample into a plurality of pieces, the symbols are error-corrected and then written to a memory.
By starting reading the memory after the number of error correction blocks required to form the sample data has been written to the memory, the output timing of the digital information signal can be advanced.

[Conventional technology]

For example, a digital VTR for recording / reproducing a composite digital video signal and digital audio signal
In, the reproduced digital audio signal is subjected to processing such as error correction and written into a memory. Then, the data is read at a sampling frequency (for example, 48 kHz), and further subjected to error correction processing and output. Conventionally, as the above-described memory, a switching system in which two systems of memories are provided and each memory is operated as write-only and read-only has been used. That is, while audio data is being written to one memory, the audio data is read from the other memory,
Reading is performed from one of the already written memories, and writing is performed on the other memory.

[Problems to be solved by the invention]

In the case of a digital VTR, the playback audio signal is
It is preferable that the video signal is output earlier than the reproduced video signal. This leading amount is called an advance amount. One of the reasons is that when muting is applied to an audio signal when reproduction data cannot be obtained, the level of the audio signal is gradually reduced.

However, in the conventional method of switching between two memories, after all the data is written,
Since the reading is started, the output of the audio data is delayed, and there is a problem that the advance amount cannot be sufficiently obtained. Further, two systems of memories are required, and there is a disadvantage that the circuit scale becomes large.

Accordingly, an object of the present invention is to provide a digital information signal processing device capable of obtaining a sufficient advance amount.

[Means for solving the problem]

According to the present invention, in a digital information signal processing apparatus in which one sample of a digital information signal is processed by using a symbol having a bit length obtained by dividing the sample into a plurality of pieces, the symbols are error-corrected, written into a memory, After the required number of error correction blocks are written to the memory, the reading of the memory is started.

[Action]

The encoding and decoding of the error correction code are processed in units of, for example, 8 bits (1 byte). On the other hand, one sample of the digital audio signal has 20 bits.
Therefore, one sample of the digital audio signal is completed by collecting three 8-bit error correction blocks. When reading a digital audio signal from a memory in sample units, it is necessary to write at least three error correction blocks. The delay time until the digital audio signal is output from the memory can be reduced to the minimum time corresponding to three error correction blocks.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to processing of audio data of a digital VTR will be described with reference to the drawings.

FIG. 1 shows the configuration on the recording side of a digital VTR. In FIG. 1, 1 is an input terminal for an analog audio signal, 2 is an input terminal for a digital audio signal, 3
Is an analog / digital interface. A buffer memory 4 is connected to the interface 3, and the buffer memory 4 compresses the time axis of the audio data and converts the audio data into an order of a block structure. Reference numeral 5 indicates an outer code encoder, and reference numeral 6 indicates a shuffling circuit. The outer code encoder 5 encodes an outer code that is an error correction code. The shuffling circuit 6 is constituted by a memory and rearranges the order of data.

7 is an input terminal for an analog video signal, 8 is an input terminal for a digital video signal, and 9 is an analog / digital interface. The output signal of the interface 9 is supplied to the channel demultiplexer 10 and
Converted to the channel data series. The data sequence of each channel is supplied to the outer code encoder 11, and is subjected to outer code encoding processing. The output data of the encoder 11 is supplied to the intra-sector shuffling circuit 12, and the order of the data in the sector is rearranged.

Synchronization and ID with audio data from shuffling circuit 6 and video data from intra-sector shuffling circuit 12
The synchronization signal and the ID signal from the generation circuit 13 are supplied to the data multiplexer 14. The output signal of the data multiplexer 14 is supplied to the inner code encoder 15. The inner code encoder 15 performs a process of encoding the inner code. Output signal of inner code encoder 15 is channel encoder 16
And undergoes a process of encoding a mirror square code. The output signal of the channel encoder 16 is
Through the output terminal 18.

The output terminal 18 is connected to a rotary head. The recording data is recorded on the magnetic tape by the rotating head.
The data reproduced from the magnetic tape is supplied to the reproducing amplifier 22 from the input terminal 21 in FIG. 2 by the rotating head. The output signal of the reproduction amplifier 22 is supplied to the channel decoder 23, and the mirror square code is decoded.

The output signal of the channel decoder 23 is supplied to the synchronization detection circuit 24, and the synchronization signal is detected. Sync detection circuit 24
Is supplied to the inner code decoder 25 to decode the inner code. The output signal of the inner code decoder 25 is supplied to the switch circuit 26, where it is separated from the video data which is the audio data.

The audio data is supplied to the outer code decoder 28 after being deshuffled by the deshuffling circuit 27. The outer code is decoded by the outer code decoder 28 and stored in the memory.
Written to 29. The memory 29 expands the time axis of the data. The audio data read from the memory 29 is supplied to the error correction circuit 30, where the error data is corrected. The output data of the error correction circuit 30 is supplied to the analog / audio interface 31, and the output terminal
An analog audio signal is obtained at 32, and a digital audio signal is obtained at an output terminal 33.

The video data separated by the switch circuit 26 is written to the buffer memory 34. The video data read from the buffer memory 34 is transferred to the intra-sector deshuffling circuit 35.
Is supplied to the outer code decoder 36 via the. The error-corrected data from the outer code decoder 36 is supplied to the channel multiplexer 37, and the data of two channels is converted into the data of one channel. The output signal of the channel multiplexer 37 is supplied to an error correction circuit 38, where error data is corrected. The output signal of the error correction circuit 38 is supplied to an analog / digital interface 39. An analog video signal is obtained at the output terminal 40, and a digital video signal is obtained at the output terminal 41.

FIG. 3 shows an example of a digital VTR scanner.
Four head chips H1 to H4 are attached to the drum 42 which is circuited in the direction of the arrow. Head chip H1 and
H2 approaches, head chips H3 and H4 approach, head chips H1 and H3 have a 180 ° facing distance, and head chip H
2 and H4 have a 180 ° facing distance. On the peripheral surface of the drum 42, a magnetic tape 43 with a winding angle slightly wider than 180 ° is used.
Is wound diagonally. A set of head chips H1 and H2 and a set of head chips H3 and H4 alternately contact the magnetic tape 43. The angles of the gaps of the head chips H1 and H2 are made different, and similarly, the angles of the gaps of the head chips H3 and H4 are made different so that azimuth recording is performed.

In the case of a video signal having a field frequency of 60 Hz as in the NTSC system, one field is divided into three segments and one field is divided into three segments.
The segment is recorded as two tracks. That is, the video signal for one field is recorded on the magnetic tape 43 as three segments and six tracks.

FIGS. 4A and 4B show a track format formed on the magnetic tape 43. FIG. FIG. 4A shows a track pattern viewed from the magnetic surface side of the magnetic day 43, and FIG.
Shows one track in the order of head scanning. A0, A1, A2, and A3 indicate audio sectors, and these audio sectors A0 to A3 are arranged at track ends. The same content of audio data is recorded twice at different ends of two tracks. That is, the same audio data is recorded at each of the end of the previous track on the head separation side and the end of the current track on the head entry side. The video sector is located in the center of the track. T
0 and T1 are track numbers, and S0 is a segment number.

As shown in FIG. 4B, an editing gap is provided between the audio sectors and between the audio sector and the video sector. Audio sectors A0 to A3 are 6
The video sector is composed of 204 sync blocks. In FIG. 4B, T is
E indicates a track preamble, E indicates an edit gap preamble, and P indicates a post preamble.

As shown in FIG. 5, each sync block has a length of 190 bytes, and a 2-byte synchronization pattern is added at the beginning. Next, a 2-byte ID pattern is added,
The ID code and the 85-byte data are encoded with an inner code to form an 8-byte check code. Also, an 8-byte check code is added to the other 85-byte data to form an inner code block.

The inner code is common to audio data and video data. A Reed-Solomon code is used as the inner code and the outer code. The number of samples of audio data recorded in each audio sector is 266 samples or 267 samples. FIG. 6 shows blocks included in one audio sector. Numerals 0 to 266 indicate audio sample numbers, and PV0 to PV3 indicate outer code check codes. These audio data and check codes are shuffled. In FIG. 6, the check code of the inner code is not shown. Although the bit length of one sample of the audio data is 20 bits, the encoding of the inner code uses one byte as one symbol.

FIG. 7 is a timing chart of this embodiment. FIG. 7A shows reproduced data supplied to the input terminal 21, and FIG. 7B shows output data of the deshuffling circuit 27. As mentioned above, the audio sectors are A0-A3
, And audio data of these channels are processed in parallel. However, in FIG. 7, for the sake of simplicity, one channel audio sectors A11, A12, A13,... Are located before the video data.

The output data of the deshuffling circuit 27 is supplied to the outer code decoder 28, and undergoes an outer code error correction process. The outer code is a block of 12 symbols in the column (vertical) direction in FIG. The audio data after error correction shown in FIG. 7C is obtained from the outer code decoder 28. This audio data is written to the memory 29. Memory 29
, Audio data is read out in real time (48 kHz sampling rate), and the audio data shown in FIG. 7D is obtained. The audio data of one sector is 26
Consists of 6 or 267 samples.

Since one sample of the audio data is 20 bits, the reading of the memory 29 is started after the three blocks of the outer code are decoded and written into the memory 29.
In FIG. 7D, τ is a delay time from when audio data is written to the memory 29 to when reading is started (corresponding to a time until the above-mentioned three outer code blocks are written). Show. In the memory 29, writing and reading are mixed in the sampling cycle of audio data, and reading and writing are performed in a time-division manner. Since the writing period is shorter than the reading period,
Reads do not overtake writes.

〔The invention's effect〕

According to the present invention, readout is performed simultaneously while writing output data of the outer code decoder to the memory, so that reproduced audio data can be obtained quickly. FIG. 7E shows the read output in the case of having the conventional two-system memory for comparison with the present invention. In the conventional memory, audio data is read out in real time from the other memory while the output data (FIG. 7C) of the outer code decoder 28 is being written into one memory. Therefore,
After the output data of the outer code decoder 28 is generated,
The delay time until the output of 29 is obtained
There was a pretty long problem. Further, according to the present invention, the capacity of the memory is one block, and the capacity of the memory and the scale of the peripheral circuit can be reduced.

[Brief description of the drawings]

FIG. 1 shows a digital VT to which the present invention can be applied.
FIG. 2 is a block diagram on the reproducing side of an example of a digital VTR to which the present invention can be applied, FIG. 3 is a plan view showing the configuration of the scanner, and FIG.
FIG. 5 is a schematic diagram showing a format of a digital VTR on a tape, FIG. 5 is a schematic diagram showing a configuration of a sync block, FIG. 6 is a schematic diagram showing an audio digital block arrangement, and FIG. 6 is a timing chart used for describing one embodiment. Explanation of main symbols in the drawings 21: input terminal of reproduced digital signal, 27: deshuffling circuit, 28: outer code decoder, 29: memory, 30: error correction circuit.

Claims (1)

(57) [Claims] 1. A digital information signal processing apparatus which processes a digital information signal using a symbol having a bit length obtained by dividing one sample of a digital information signal into a plurality of bits.
A digital information signal processing apparatus, wherein reading of the memory is started after the number of the error correction blocks required to form one sample of data is written to the memory.