JP2547690B2 - Method for manufacturing LDD transistor - Google Patents
Method for manufacturing LDD transistorInfo
- Publication number
- JP2547690B2 JP2547690B2 JP4116768A JP11676892A JP2547690B2 JP 2547690 B2 JP2547690 B2 JP 2547690B2 JP 4116768 A JP4116768 A JP 4116768A JP 11676892 A JP11676892 A JP 11676892A JP 2547690 B2 JP2547690 B2 JP 2547690B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- type impurity
- diffusion region
- manufacturing
- impurity diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000000034 method Methods 0.000 title claims description 10
- 239000012535 impurity Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 18
- 125000006850 spacer group Chemical group 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 238000001312 dry etching Methods 0.000 claims 1
- 238000004088 simulation Methods 0.000 description 11
- 239000000969 carrier Substances 0.000 description 10
- 230000005684 electric field Effects 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- -1 phosphorus ions Chemical class 0.000 description 4
- 241000112839 Ampheres Species 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 101150039027 ampH gene Proteins 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＬＤＤ（Ｌｉｈｔｌｙ
Ｄｏｐｅｄ Ｄｒａｉｎ）の構造を有するトランジス
タの製造方法に関し、特にソース／ドレーン領域の近傍
の電界によるホットキャリアの影響を減少させたものの
製造方法に関する。The present invention relates to an LDD (Lihtly).
The present invention relates to a method of manufacturing a transistor having a Doped Drain structure, and more particularly to a method of manufacturing a transistor in which the influence of hot carriers due to an electric field in the vicinity of a source / drain region is reduced.
【０００２】[0002]
【従来の技術】従来、一般のＬＤＤ構造を有するＮ型ト
ランジスタの製造工程を図１乃至図４を参照して説明す
る。まず、図１のように、Ｐ型基板１上にゲート２を形
成し、図２のように、低濃度のソース／ドレーン領域を
形成するためのＮ−型イオン注入を施す。ついで図３の
ように、ゲート側壁スペーサ３を形成し、熱工程を施し
て注入したＮ−型イオンを基板に拡散させ、低濃度のソ
ース／ドレーン領域４を形成する。そして図４のよう
に、Ｎ＋型イオン注入を施した後拡散させて高濃度のソ
ース／ドレーン領域５を形成する。2. Description of the Related Art Conventionally, a manufacturing process of an N-type transistor having a general LDD structure will be described with reference to FIGS. First, as shown in FIG. 1, a gate 2 is formed on a P-type substrate 1, and N − -type ion implantation for forming low concentration source / drain regions is performed as shown in FIG. Then, as shown in FIG. 3, a gate sidewall spacer 3 is formed, and a heat process is performed to diffuse the implanted N − type ions into the substrate to form a low concentration source / drain region 4. Then, as shown in FIG. 4, N + type ion implantation is performed and then diffused to form a high concentration source / drain region 5.
【０００３】[0003]
【発明が解決しようとする課題】ソース／ドレーン領域
の近傍に集中される強い電界を減少させるために、従来
は前記のように高濃度のソースドレーン領域５と低濃度
のソースドレーン領域とを形成して、最終商品の信頼性
を改善していた。しかしながら、強い電界によるホット
キャリアが側壁スペーサを形成するＬＴＯ（Ｌｏｗ Ｔ
ｅｍｐｅｒａｔｕｒｅ Ｏｘｉｄｅ）膜にトラップされ
て電界が存在することとなり、これにより、そのホット
キャリアのゲート酸化膜の信頼性が低下する不都合があ
った。In order to reduce the strong electric field concentrated near the source / drain regions, the high concentration source drain region 5 and the low concentration source drain region are conventionally formed as described above. And improved the reliability of the final product. However, hot carriers generated by a strong electric field form LTO (Low T
Since an electric field is trapped in the embossed oxide (Oxide Oxide) film, the reliability of the gate oxide film for the hot carriers is lowered.
【０００４】本発明は、このような従来の技術の不都合
を解消するためのもので、強い電界によりトラップされ
るホットキャリアを減少できる改良されたＬＤＤトラン
ジスタ及びその製造方法を提供するにある。SUMMARY OF THE INVENTION The present invention is intended to solve the above disadvantages of the conventional technique, and provides an improved LDD transistor capable of reducing hot carriers trapped by a strong electric field and a method of manufacturing the same.
【０００５】[0005]
【課題を解決するための手段】本発明は、基板上に、通
常の方法によりゲートを形成した後、基板と異なる型の
イオン注入を施した後拡散させ、低濃度のソース／ドレ
ーン領域を形成し、全面的に基板に同型の不純物がドー
ピングされた物質，例えばＢＳＧ（ＢｏｒｏｎＳｉｌｉ
ｃａｔｅ Ｇｌａｓｓ）を蒸着し、エッチングを施して
ゲート側壁を形成し、ポストアニーリング工程を施して
低濃度のソース／ドレーン領域の中の前記ゲート側壁の
直下に基板と同型の不純物拡散領域を形成し、前記基板
と異なる型のイオン注入を施した後拡散させ、高濃度の
ソース／ドレーン領域を形成するステップが含まれる。 This onset bright [Means for solving problems], on the substrate, after forming a gate in a conventional manner, is diffused after being subjected to ion implantation of a different type as the substrate, a low concentration source / drain regions of the A material, such as BSG (BoronSili), which is formed and entirely doped with the same type of impurities on the substrate.
and a gate sidewall is formed by etching, and a post-annealing process is performed to form an impurity diffusion region of the same type as the substrate just below the gate sidewall in the low concentration source / drain region. Ion implantation of a different type from the substrate and then diffusion to form high concentration source / drain regions are included.
【０００６】[0006]
【実施例】本発明を図５乃至図９を参照して詳細に説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to FIGS.
【０００７】まず、図５のように、濃度が２×１０１５
（ｃｍ−３）であるＰ型基板１０上に、ゲート酸化膜１
１とゲート１２を形成し、図６のように、低濃度のソー
ス／ドレーン領域を形成するために４０ｋｅＶのエネル
ギで２×１０１３（ｃｍ−２）の燐イオンを注入する。
一方、前記ゲート１２の下方の基板１０には４０ｋｅＶ
のエネルギで２×１０１３（ｃｍ−２）のドーズのＢＦ
２を注入してチャンネル１０ａを形成する。First, as shown in FIG. 5, the density is 2 × 10 15.
(Cm −3 ), on the P-type substrate 10, the gate oxide film 1 is formed.
1 and the gate 12 are formed, and as shown in FIG. 6, 2 × 10 13 (cm −2 ) of phosphorus ions are implanted at an energy of 40 keV to form a low concentration source / drain region.
On the other hand, 40 keV is applied to the substrate 10 below the gate 12.
BF with a dose of 2 × 10 13 (cm −2 ) with the energy of
2 is injected to form the channel 10a.
【０００８】そして図７のように、Ｐ型不純物であるホ
ウ素が６×１０１８（ｃｍ−３）の濃度でドーピングさ
れたシリケートガラス（ｓｉｌｉｃａｔｅ ｇｌａｓ
ｓ，ＢＳＧ）を全面的に蒸着した後、リアクチブイオン
エッチング（ＲｅａｃｔｉｖｅＩｏｎ Ｅｔｃｈｉｎ
ｇ，ＲＩＥ）法によりドライエッチングを施して１５０
０Åの厚さ（Ｔ）の側壁スペーサ１３を形成し、熱工程
を施して注入された燐イオンを前記基板１０に拡散させ
て低濃度のソース／ドレーン領域１４を形成する。Then, as shown in FIG. 7, a silicate glass doped with boron, which is a P-type impurity, at a concentration of 6 × 10 18 (cm −3 ).
s, BSG) is deposited on the entire surface, and then reactive ion etching (Reactive Ion Etchin) is performed.
g, RIE) and dry-etched to 150
A sidewall spacer 13 having a thickness (T) of 0Å is formed, and a phosphorous ion implanted by a thermal process is diffused into the substrate 10 to form a low concentration source / drain region 14.
【０００９】ついで図８のように、前記ホウ素がドーピ
ングされたゲート側壁１３の濃度を向上させ、低濃度の
ソース／ドレーン領域１４にホウ素を拡散させるための
ポストアニーリング（Ｐｏｓｔ ａｎｅａｌｉｎｇ）工
程が施される。その際前記ゲート側壁スペーサ１３の直
下の低濃度のソース／ドレーン領域１４にホウ素が拡散
され、Ｐ型層１５を形成させる。Next, as shown in FIG. 8, a post annealing process is performed to increase the concentration of the boron-doped gate sidewall 13 and diffuse the boron into the low concentration source / drain regions 14. It At that time, boron is diffused into the low-concentration source / drain region 14 immediately below the gate sidewall spacer 13 to form a P-type layer 15.
【００１０】その後、図９のように、６０ｋｅＶのエネ
ルギで５×１０１５（ｃｍ−２）のドーズのひ素イオン
を注入して高濃度のソース／ドレーン領域１６を形成す
る。After that, as shown in FIG. 9, arsenic ions with a dose of 5 × 10 15 (cm −2 ) are implanted at an energy of 60 keV to form high-concentration source / drain regions 16.
【００１１】以上のように、本発明によれば、ＬＤＤ構
造のＮ型トランジスタにおいて、ＢＳＧによりゲート側
壁１３を形成し、ポストアニーリングの時、ホウ素をゲ
ート側壁１３を直下部分に拡散してＰ型層１５を形成さ
せる。この時、このソース／ドレーン領域と反対型のＰ
型層１５はホットキャリアがゲート酸化膜１１とゲート
側壁１３とに進出するのを阻止する。As described above, according to the present invention, in the N-type transistor having the LDD structure, the gate sidewall 13 is formed by BSG, and at the time of post-annealing, boron is diffused into the portion immediately below the gate sidewall 13 to form the P-type. Form layer 15. At this time, a P type opposite to the source / drain region
-Type layer 15 is hot carriers deter to advance into the gate oxide film 11 and the gate sidewalls 13.
【００１２】すなわち、３価不純物であるホウ素は、５
価不純物である燐によって強い電界が発生するのを防ぐ
バッファの役割をするものであり、ホットキャリアがソ
ース領域からドレーン領域に強く流入することを阻止
し、ゲート酸化膜とゲート側壁とにトラップされること
を防ぐ。That is, boron, which is a trivalent impurity, is 5
It is intended to the role of a buffer to prevent the strong electric field is generated by phosphorus valence impurities, sealed inhibitory that hot carrier flows strongly from the source region to the drain region, trapped in the gate oxide film and the gate sidewall To be prevented.
【００１３】従来のＬＤＤトランジスタと本発明による
ＬＤＤトランジスタとに対するシミュレーションの結果
は次の通りである。The simulation results for the conventional LDD transistor and the LDD transistor according to the present invention are as follows.
【００１４】まず、図１０，１１はインパクトイオン
（ｉｍｐａｃｔ ｉｏｎ）のポテンシャル分布を示すグ
ラフであり、従来構造（図１０）では、ゲート酸化膜に
インパクトイオンのポテンシャルが広く分布してホット
キャリアがゲート酸化膜にトラップされ易くなる。First, FIGS. 10 and 11 are graphs showing the potential distribution of impact ions. In the conventional structure (FIG. 10), the potential of impact ions is widely distributed in the gate oxide film and hot carriers are generated in the gate. It is easily trapped in the oxide film.
【００１５】逆に、本発明の構造（図１１）では、側壁
スペーサの下方にホウ素が拡散されて形成されたＰ型層
のため、インパクトイオンのポテンシャルが狭く形成さ
れ、ホットキャリアがホウ素イオンと再結合してゲート
酸化膜へ進出することが減少する。したがって、素子特
性がよくなる。ここで、シミュレーション条件でＶｄｓ
＝３．３（Ｖｏｌｔｓ），Ｖｇｓ＝５（Ｖｏｌｔｓ）を
印加した。On the contrary, in the structure of the present invention (FIG. 11), since the P-type layer is formed by diffusing boron under the side wall spacer, the potential of impact ions is narrowed, and the hot carriers are boron ions. Recombination and extension into the gate oxide film are reduced. Therefore, the device characteristics are improved. Here, Vds under simulation conditions
= 3.3 (Volts) and Vgs = 5 (Volts) were applied.
【００１６】図１２〜１４は従来のＬＤＤトランジスタ
と本発明によるＬＤＤトランジスタとのＬＤＤ（図９
で、Ａ−Ａ′の部分）のドーピング輪郭を示し、比較し
たもので、図示のように、本発明によるＬＤＤドーピン
グ輪郭（図１３）では、従来のＬＤＤドーピング輪郭
（図１２）に比較して、側壁スペーサの濃度のため、屈
曲が現れている、図１４では、従来のものと本発明のＬ
ＤＤドーピング輪郭とを同時に示したものである。12 to 14 show the LDD of the conventional LDD transistor and the LDD transistor of the present invention (see FIG. 9).
In FIG. 13, the LDD doping profile according to the present invention (FIG. 13) is compared with the conventional LDD doping profile (FIG. 12). since the concentration of the sidewall spacer, bending is present, in Figure 14, the conventional ones and the present invention L
3 shows the DD doping profile at the same time.
【００１７】図１５〜１７は従来のＬＤＤトランジスタ
と本発明との特性を評価するパラメータに関するグラフ
である。各パラメータはゲートにバイアス電圧が印加さ
れる時、正孔によって基板に流れる電流（Ｉｓｕｂ）で
ある。従来の構造（図１５）においてはゲート電圧（Ｖ
ｇｓ）が１．８Ｖ印加される時、電流（Ｉｓｕｂ）の値
が１．５０６×１０−６（Ａｍｐｈｅｒｅ／ｍｉｃｒｏ
ｎ）と最大になり、本発明の構造（図１６）において
は、ゲート電圧（Ｖｇｓ）が１．６Ｖ印加される時、電
流（Ｉｓｕｂ）の値が３．０１６×１０−７（Ａｍｐｈ
ｅｒｅ／ｍｉｃｒｏｎ）と最大になる。結局、側壁スペ
ーサの下のＰ型領域で多数のホットキャリアが再結合さ
れ、ドレイン電界に衝突して発生する電子，正孔対の生
成が少なくなるので、基板に流れる電流の量も少くなく
なる。本発明によるシミュレーションの結果は従来のも
のより約１／５位減少されるよい特性であることを示し
ている。また、この基板に流れる電流（Ｉｓｕｂ）は、
ゲートにバイアス電圧が印加された状態での、ゲート電
流を間接的に測定するパラメータである。結局、これは
ホットキャリアにより、低下するゲート酸化膜の品質を
評価するパラメータである。図１７は従来のトランジス
タと本発明のトランジスタとの電流（Ｉｓｕｂ）を比較
したものである。15 to 17 are graphs relating to parameters for evaluating the characteristics of the conventional LDD transistor and the present invention. Each parameter is a current ( Isub ) flowing through the substrate by holes when a bias voltage is applied to the gate. In the conventional structure (FIG. 15), the gate voltage (V
gs) is applied at 1.8 V, the current (I sub ) value is 1.506 × 10 −6 (Amphere / micro).
n) and the maximum, in the structure (FIG. 16) of the present invention, when the gate voltage (Vgs) is 1.6V applied, the value of the current (I sub) is 3.016 × 10 -7 (Amph
ere / micron). Eventually, a large number of hot carriers are recombined in the P-type region under the sidewall spacers, and the number of electron-hole pairs generated by collision with the drain electric field is reduced, so that the amount of current flowing through the substrate is also small. The result of the simulation according to the present invention shows that it has a good characteristic that it is reduced by about 1/5 as compared with the conventional one. In addition, the current (I sub ) flowing through this substrate is
This is a parameter that indirectly measures the gate current when a bias voltage is applied to the gate. After all, this is a parameter for evaluating the quality of the gate oxide film which is deteriorated by hot carriers. FIG. 17 compares the current (I sub ) between the conventional transistor and the transistor of the present invention.
【００１８】図１８，１９はＬＤＤトランジスタの特性
を評価する他のパラメータを示すグラフである。各パラ
メータはゲートにバイアス電圧が印加される時、電子に
よってゲートに流れる電流（Ｉｇ）である。図示のよう
に、ゲート電圧（Ｖｇｓ）が３．０Ｖ印加される時、従
来の構造（図１８）においてはＩｇは１×１０
−１５（Ａｍｐｈｅｒｅ／ｍｉｃｒｏｎ）であり、本発
明の構造（図１９）においては、その値が３×１０
−１８（Ａｍｐｈｅｒｅ／ｍｉｃｒｏｎ）になる。ここ
でも、従来の構造による電流（Ｉｇ）より本発明の構造
による電流（Ｉｇ）がずっと小さいことがわかる。18 and 19 are graphs showing other parameters for evaluating the characteristics of the LDD transistor. Each parameter is a current (Ig) flowing through the gate by electrons when a bias voltage is applied to the gate. As shown in the figure, when a gate voltage (Vgs) of 3.0V is applied, Ig is 1 × 10 in the conventional structure (FIG. 18).
-15 (Amphere / micron), and the value is 3 × 10 in the structure of the present invention (FIG. 19).
It becomes -18 (Amphere / micron). Again, it can be seen that the current (Ig) according to the structure of the present invention is much smaller than the current (Ig) according to the conventional structure.
【００１９】[0019]
【発明の効果】以上に説明したように、本発明によれ
ば、側壁スペーサに第１導電型をドーピングされた物質
を使用し、その側壁スペーサから第１導電型の不純物を
拡散させるようにしたので、低濃度の第２導電型不純物
拡散領域の所定の位置に正確に第１導電型不純物を拡散
させることができ、強い電界によるゲート酸化膜とゲー
ト側壁とにトラップされるホットキャリアを減少させて
トランジスタの特性および信頼性を大きく改善させるこ
とができた。 As described above, according to the present invention, the sidewall spacers are doped with the first conductivity type material.
Is used to remove impurities of the first conductivity type from the sidewall spacers.
Since it is made to diffuse, a low concentration second conductivity type impurity
Accurately diffuses the first conductivity type impurity at a predetermined position in the diffusion region
Gate oxide and gate due to the strong electric field.
To reduce hot carriers trapped in the sidewall
To greatly improve the characteristics and reliability of transistors.
I was able to.
【図１】従来のＬＤＤトランジスタの製造工程断面図で
ある。FIG. 1 is a cross-sectional view of manufacturing steps of a conventional LDD transistor.
【図２】従来のＬＤＤトランジスタの製造工程断面図で
ある。FIG. 2 is a cross-sectional view of manufacturing steps of a conventional LDD transistor.
【図３】従来のＬＤＤトランジスタの製造工程断面図で
ある。FIG. 3 is a cross-sectional view of manufacturing steps of a conventional LDD transistor.
【図４】従来のＬＤＤトランジスタの製造工程断面図で
ある。FIG. 4 is a cross-sectional view of manufacturing steps of a conventional LDD transistor.
【図５】本発明によるＬＤＤトランジスタの製造工程断
面図である。FIG. 5 is a cross-sectional view of the manufacturing process of the LDD transistor according to the present invention.
【図６】本発明によるＬＤＤトランジスタの製造工程断
面図である。FIG. 6 is a sectional view of a manufacturing process of an LDD transistor according to the present invention.
【図７】本発明によるＬＤＤトランジスタの製造工程断
面図である。FIG. 7 is a cross-sectional view of the manufacturing process of the LDD transistor according to the present invention.
【図８】本発明によるＬＤＤトランジスタの製造工程断
面図である。FIG. 8 is a sectional view of a manufacturing process of an LDD transistor according to the present invention.
【図９】本発明によるＬＤＤトランジスタの製造工程断
面図である。FIG. 9 is a cross-sectional view of the manufacturing process of the LDD transistor according to the present invention.
【図１０】従来ＬＤＤトランジスタにおいてインパクト
イオンのポテンシャル分布図である。FIG. 10 is a potential distribution diagram of impact ions in a conventional LDD transistor.
【図１１】本発明によるＬＤＤトランジスタにおいてイ
ンパクトイオンのポテンシャル分布図である。FIG. 11 is a potential distribution diagram of impact ions in the LDD transistor according to the present invention.
【図１２】従来のＬＤＤトランジスタと本発明によるＬ
ＤＤトランジスタとシミュレーション結果及び比較グラ
フ図である。FIG. 12: Conventional LDD transistor and L according to the present invention
It is a DD transistor, a simulation result, and a comparison graph figure.
【図１３】従来のＬＤＤトランジスタと本発明によるＬ
ＤＤトランジスタとシミュレーション結果及び比較グラ
フ図である。FIG. 13: Conventional LDD transistor and L according to the present invention
It is a DD transistor, a simulation result, and a comparison graph figure.
【図１４】従来のＬＤＤトランジスタと本発明によるＬ
ＤＤトランジスタとシミュレーション結果及び比較グラ
フ図である。FIG. 14 is a conventional LDD transistor and L according to the present invention.
It is a DD transistor, a simulation result, and a comparison graph figure.
【図１５】従来のＬＤＤトランジスタと本発明によるＬ
ＤＤトランジスタとシミュレーション結果及び比較グラ
フ図である。FIG. 15 shows a conventional LDD transistor and L according to the present invention.
It is a DD transistor and a simulation result and a comparison graph figure.
【図１６】従来のＬＤＤトランジスタと本発明によるＬ
ＤＤトランジスタとシミュレーション結果及び比較グラ
フ図である。FIG. 16 shows a conventional LDD transistor and L according to the present invention.
It is a DD transistor, a simulation result, and a comparison graph figure.
【図１７】従来のＬＤＤトランジスタと本発明によるＬ
ＤＤトランジスタとシミュレーション結果及び比較グラ
フ図である。FIG. 17: Conventional LDD transistor and L according to the present invention
It is a DD transistor and a simulation result and a comparison graph figure.
【図１８】従来のＬＤＤトランジスタと本発明によるＬ
ＤＤトランジスタとシミュレーション結果及び比較グラ
フ図である。FIG. 18: Conventional LDD transistor and L according to the present invention
It is a DD transistor and a simulation result and a comparison graph figure.
【図１９】従来のＬＤＤトランジスタと本発明によるＬ
ＤＤトランジスタとシミュレーション結果及び比較グラ
フ図である。FIG. 19 shows a conventional LDD transistor and L according to the present invention.
It is a DD transistor, a simulation result, and a comparison graph figure.
１０ Ｐ型基板 １３ 側壁スペーサ １４ ソース／ドレーン領域 １５ Ｐ型層 10 P-type substrate 13 Sidewall spacer 14 Source / drain region 15 P-type layer
Claims (10)
成する過程と、 前記ゲート電極の両側の基板表面内に、第２導電型の低
濃度のイオンを注入した後拡散させて低濃度の第２導電
型不純物拡散領域を形成する過程と、 全表面にわたって第１導電型不純物がドーピングされた
シリケートガラスを蒸着し、エッチングを施してゲート
電極の側面に側壁スペーサを形成する過程と、 前記側壁スペーサの下にある前記低濃度の第２導電型不
純物拡散領域に不純物を拡散させ、側壁スペーサの直下
に第１導電型不純物拡散領域を形成する過程と、 前記低濃度の第２導電型不純物拡散領域に隣接する箇所
に、第２導電型高濃度のイオンを注入した後拡散させて
高濃度の第２導電型不純物拡散領域を形成する過程と、 が順次含まれることを特徴とするＬＤＤトランジスタの
製造方法。1. A process of forming a gate electrode on a substrate of the first conductivity type, and a step of implanting low concentration ions of the second conductivity type into the surface of the substrate on both sides of the gate electrode and then diffusing the ions to lower the concentration. The process of forming the second conductivity type impurity diffusion region of high concentration and the doping of the first conductivity type impurity over the entire surface
A process of depositing silicate glass and performing etching to form a sidewall spacer on a side surface of the gate electrode, and diffusing impurities into the low-concentration second conductivity type impurity diffusion region under the sidewall spacer, A process of forming a first conductivity type impurity diffusion region immediately below, and a step of implanting a second conductivity type high concentration ion into a portion adjacent to the low concentration second conductivity type impurity diffusion region and then diffusing it to obtain a high concentration A method of manufacturing an LDD transistor, comprising: a step of forming a second conductivity type impurity diffusion region;
スペーサを形成することを特徴とする請求項１に記載の
ＬＤＤトランジスタの製造方法。2. The method of manufacturing an LDD transistor according to claim 1 , wherein the sidewall spacers are formed by performing RIE dry etching.
特徴とする請求項１に記載のＬＤＤトランジスタの製造
方法。3. The method of manufacturing an LDD transistor according to claim 1 , wherein the sidewall spacer is formed of BSG.
ーサをＰＳＧで形成することを特徴とする請求項１に記
載のＬＤＤトランジスタの製造方法。4. The method of manufacturing an LDD transistor according to claim 1 , wherein when the second conductivity type substrate is used, the side wall spacer is formed of PSG.
成することを特徴とする請求項１ないし４のいずれかに
記載のＬＤＤトランジスタの製造方法。A thickness of 5. 1500 Å, a manufacturing method of the LDD transistor according to any one of 4 to claims 1 and forming a sidewall spacer.
純物拡散領域の不純物は、同じ物質を用いることを特徴
とする請求項１に記載のＬＤＤトランジスタの製造方
法。6. The method of manufacturing an LDD transistor according to claim 1 , wherein the impurities of the first conductivity type substrate and the impurities of the first conductivity type impurity diffusion region use the same material.
１３（ｃｍ−２）のリンを注入して低濃度の第２導電型
不純物拡散領域を形成することを特徴とする請求項１に
記載のＬＤＤトランジスタの製造方法。7. 2 × 10 at an energy of 40 keV
13. The method of manufacturing an LDD transistor according to claim 1 , wherein 13 (cm −2 ) of phosphorus is implanted to form a low concentration second conductivity type impurity diffusion region.
１５（ｃｍ−２）のひ素を注入して高濃度の第２導電型
不純物拡散領域を形成することを特徴とする請求項１に
記載のＬＤＤトランジスタの製造方法。8. 5 × 10 at an energy of 60 keV
The method of manufacturing an LDD transistor according to claim 1 , wherein 15 (cm −2 ) of arsenic is implanted to form a high concentration second conductivity type impurity diffusion region.
ペーサの下方に第１導電型不純物拡散領域を形成するこ
とを特徴とする請求項１に記載のＬＤＤトランジスタの
製造方法。9. The method of LDD transistor according to claim 1 which is subjected to post-annealing step and forming a first conductivity type impurity diffusion region under the sidewall spacers.
電型不純物拡散領域が、前記低濃度の第２導電型不純物
拡散領域を外れないように形成することを特徴とする請
求項１に記載のＬＤＤトランジスタの製造方法。10. A first conductivity type impurity diffusion region formed under the sidewall spacers, according the to claim 1, characterized in that formed so as not to come off the second conductivity type impurity diffusion region of low concentration Manufacturing method of LDD transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR5714/1991 | 1991-04-10 | ||
| KR1019910005714A KR920020594A (en) | 1991-04-10 | 1991-04-10 | LDD transistor structure and manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0629308A JPH0629308A (en) | 1994-02-04 |
| JP2547690B2 true JP2547690B2 (en) | 1996-10-23 |
Family
ID=19313084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4116768A Expired - Fee Related JP2547690B2 (en) | 1991-04-10 | 1992-04-10 | Method for manufacturing LDD transistor |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2547690B2 (en) |
| KR (1) | KR920020594A (en) |
| DE (1) | DE4211999C2 (en) |
| TW (1) | TW268136B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5518945A (en) * | 1995-05-05 | 1996-05-21 | International Business Machines Corporation | Method of making a diffused lightly doped drain device with built in etch stop |
| US6339005B1 (en) * | 1999-10-22 | 2002-01-15 | International Business Machines Corporation | Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET |
| US7732285B2 (en) * | 2007-03-28 | 2010-06-08 | Intel Corporation | Semiconductor device having self-aligned epitaxial source and drain extensions |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6143477A (en) * | 1984-08-08 | 1986-03-03 | Hitachi Ltd | Manufacture of mos transistor |
| JPS61214575A (en) * | 1985-03-20 | 1986-09-24 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH01309376A (en) * | 1988-06-07 | 1989-12-13 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1991
- 1991-04-10 KR KR1019910005714A patent/KR920020594A/en not_active Application Discontinuation
-
1992
- 1992-03-26 TW TW081102330A patent/TW268136B/zh active
- 1992-04-09 DE DE4211999A patent/DE4211999C2/en not_active Expired - Fee Related
- 1992-04-10 JP JP4116768A patent/JP2547690B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6143477A (en) * | 1984-08-08 | 1986-03-03 | Hitachi Ltd | Manufacture of mos transistor |
| JPS61214575A (en) * | 1985-03-20 | 1986-09-24 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH01309376A (en) * | 1988-06-07 | 1989-12-13 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR920020594A (en) | 1992-11-21 |
| JPH0629308A (en) | 1994-02-04 |
| DE4211999A1 (en) | 1992-10-15 |
| DE4211999C2 (en) | 1999-06-10 |
| TW268136B (en) | 1996-01-11 |
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