JPH07147399A - Semiconductor device - Google Patents

Abstract

PURPOSE:To fully reduce capacity by setting the width in depth direction of a first region to be smaller than the total of the width of depletion layer according to gate voltage and the width of depletion layer formed inside the first region and then setting a second width in depth direction to be smaller than the total of the width of depletion layer inside the second region and the width of second and fourth depletion layers. CONSTITUTION:The width in depth direction of a region 1 is made smaller than the total of the width of depletion layer according to the gate voltage of a gate electrode 15 and the width of depletion layer formed in side the region I by pn junction of regions I and II. On the other hand, the width in depth direction of the region II is made smaller than the total of the width of depletion layer formed inside the region II by the pn junction of the regions I and II and the width of depletion layer according to the pn junction of regions II and IV, thus fully reducing capacity and achieving a low threshold voltage and a low leak current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MOSFET (Metal Oxide Semiconductor Field Ef).
fect Transistor).

[0002]

2. Description of the Related Art In a MOSFET, the power supply voltage tends to decrease as it is miniaturized, and it is necessary to lower the threshold voltage accordingly. However, if the impurity concentration of the substrate is increased to prevent the punch-through phenomenon, the threshold voltage also rises.Therefore, an impurity of the conductivity type opposite to that of the substrate is introduced to the surface of the substrate to make it apparent. I tried to lower the threshold voltage. However, in this case, although the apparent threshold voltage is lowered, there is a problem that the drain current (leakage current) value is increased when the gate voltage is 0V.

Therefore, the inventor of the present invention filed Japanese Patent Application No. 5-20886.
In application No. 7, by embedding a region having a conductivity type opposite to that of the well under the gate, the gate voltage required to reduce the drain current value by one digit in the region below the threshold voltage is obtained. A semiconductor device having a lower S coefficient and a method for manufacturing the same have been proposed. This semiconductor device is shown in FIG. 11 and briefly described.

This MOSFET has a region I having the same conductivity type as that of the substrate 1 under the gate electrode 5, and below the region I.
There is a region II which has the opposite conductivity type to the substrate 1. Further, between the region II and the source region 2 and between the region II and the drain region 3, there are regions III having the same conductivity type as that of the substrate 1. It should be noted that the substrate 1 is referred to as a region IV. Therefore, when the substrate 1 is p-type, the regions I, III and IV are p-type, and the region II, the source region 2 and the drain region 3 are n-type. When the substrate 1 is n-type, the conductivity types are opposite to each other.

The width W1 in the depth direction of the region I is smaller than the sum of the width Wg of the depletion layer due to the gate voltage and the width Wj1 of the depletion layer due to the junction of the region II (W1 <Wg + W).
j1), the width W2 in the depth direction of the region II is arbitrary. As a result, the region I becomes an inversion state during operation and becomes a channel region in charge of carrier conduction, and the threshold voltage of this MOSFET is controlled by the impurity concentration of the region I. Since the region II has a pn junction with the region I, the region I is depleted by this junction. Therefore, the region II helps depletion of the region I when a voltage is applied to the gate electrode 5, and reduces the apparent capacitance seen from the gate electrode 5. At the same time, the threshold voltage is reduced.

[0006]

[Patent Document 1] Japanese Patent Application No. 5-2
In the 08867 application, the concentration of the region II and the width in the depth direction may be set to arbitrary values, but if the concentration of the region II is sufficiently high and the width in the depth direction is sufficiently wide, the region II Is no longer depleted, the channel depletion layer in the region I stops in this region II, the electric field of the gate electrode does not spread further, and there is a problem that the capacitance does not sufficiently decrease. Therefore, the present invention aims to provide a semiconductor device in which the depletion layer extends to the substrate (region IV) and the capacitance can be sufficiently reduced by manufacturing the region II under the condition of being completely depleted. And

[0007]

As means for achieving the above object, a gate electrode formed on a semiconductor substrate having a first conductivity type with a thin gate insulating film sandwiched between the gate electrode and a gate electrode below the gate insulating film. And a source region and a drain region having a second conductivity type provided on both sides of the gate electrode, the gate insulating film, the source region, and the drain region below the gate insulating film. Between the gate insulating film and the second region having the first conductivity type and the second region having the second conductivity type formed in the substrate so as not to come into contact with the second region. A first region having a first conductivity type and formed between the second region and the source region and the drain region, respectively, and a depletion layer width due to the source region; Pn with the area A width of a depletion layer formed when a voltage is applied to the gate electrode, It is smaller than the sum of the width of the depletion layer formed in the first region by the pn junction with the second region, and the width of the second region is p with the first region.
Provided is a semiconductor device characterized by being smaller than the sum of the width of a depletion layer formed in the second region by an n-junction and the width of a depletion layer formed by a pn junction in the fourth region with the substrate. Is what you are trying to do.

[0008]

As a result of conducting various experiments, the present inventor may or may not completely deplete the region II by varying the implantation amount of impurities introduced when forming the region II. I knew that. Therefore, if the region II is completely depleted with the impurity implantation amount set to an appropriate value, the S coefficient is lowered and the capacitance of the semiconductor device can be sufficiently reduced. Hereinafter, this will be described in detail in Examples.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain one embodiment of a semiconductor device of the present invention, a MOS as shown in FIG. 1 under the following conditions.
An FET was manufactured and an experiment was conducted. MO whose configuration is shown in FIG.
SFET is a MOSFET having an LDD structure,
Its characteristics are the reference number 405001060 filed earlier.
No. “Semiconductor device” (filed on November 9, 1993).

To briefly describe the structure of this MOSFET, there are non-conductive side spacers 16 on both sides of the gate electrode 15, and the same conductivity type as that of the substrate 11 is provided under the gate electrode 15 via the gate oxide film 14. There is a region I that has.
Then, below that, there is a region II having a conductivity type opposite to that of the substrate 11. Further, between the region II and the source region 12 and between the region II and the drain region 13, there are regions III having the same conductivity type as the substrate 11, respectively. Further, the LDD region 17 is formed between the region I and the source region 12 and between the region I and the drain region 13. It should be noted that the substrate 11 is defined as a region IV. Therefore, if the substrate 11 is p-type, the regions I, III and IV are p-type,
The region II, the source region 12, the drain region 13, and the LDD region 17 are n-type. When the substrate 11 is n-type, the conductivity types are opposite to each other.

A method of manufacturing this MOSFET is shown in FIG.
(F) will be described together. First, as shown in FIG. 3A, a gate oxide film 14a having a thickness of 500 A (angstrom) is formed on the surface of the p-type substrate 11 having an impurity concentration of 1.5 × 10 ¹⁶ cm ^-3 which is the region IV. This gate oxide film 14a
Injecting B (boron) into the substrate 11 through the voltage of 25 KeV,
After injecting with an injection amount of 4 × 10 ¹² cm ^-2 , P (phosphorus) is added to 12
When an appropriate amount of implantation is performed with an implantation voltage of 0 KeV, a B-implanted layer 18 which will be a region I is formed below the gate oxide film 14a, and a P-region which is a region II is further implanted below the layer 18. Layer 19 is formed. The heat treatment of the impurities is performed at the same time as the heat treatment for activating the source region 12 and the drain region 13 described later to form regions I and II.

Then, as shown in FIG.
After the implantation, the gate oxide film 14a is removed, the gate oxide film 14 is attached again, a polysilicon thin film is formed, and then this is etched to form a gate electrode 1 having a thickness of 0.4 μm.
5 is formed. Further, as shown in FIG. 3C, B is implanted into the depth position where the region II is formed at a implantation voltage of 40 KeV and a dose of 5 × 10 ¹² cm ^{-2 using} the gate electrode 15 as a mask to form a region III. To form. Then, as shown in FIG. 3D, the implantation voltage 25 is used with the gate electrode 15 as a mask.
An n ⁻ layer 20 to be the LDD region 17 is formed on the surface side of the B-implanted layer 18 by implanting As with KeV and an implantation dose of 4 × 10 ¹³ cm ⁻² .

Then, as shown in FIG. 3E, the side spacer 16 is formed. This side spacer 16 is
It can be formed by forming a SiO ₂ film on the entire surface and performing anisotropic etching such as RIE. In this state, as shown in FIG. 6F, the injection voltage is 50 KeV with the gate electrode 15 and the side spacer 16 as a mask.
, N ⁻ layer 2 by implanting As with a dose of 1 × 10 ¹⁵ cm ⁻²
The source region 12 and the drain region 13 are formed outside the lower side spacer 16 of the layer 18 into which 0 and B are implanted. Finally, by performing heat treatment at 900 ° C. for 40 minutes, a MOSFET as shown in FIG. 1 can be manufactured.

FIG. 3 is a sectional view showing the impurity concentration of the MOSFET thus manufactured. The gate width in the direction perpendicular to the plane of the drawing is 30 μm, and the layer 19 to be the region II is
The impurity implantation amount of phosphorus (P) implantation for forming
It is when it is set to × 10 ¹² cm ^-2 . As shown in the figure, the region I, the source region 12 and the drain region 13 are
It is formed up to a depth of 0.1 μm from the surface,
Regions II and III are formed on the lower side up to a depth of 0.2 μm.

The impurity profile in the depth direction of the channel portion is shown in the graph of FIG.
The vertical axis of this graph is a logarithmic representation of the impurity concentration, and the horizontal axis is the depth. From FIG. 3 and FIG. 3, the peak formed up to the depth of 0.1 μm is the region I.
Shows the concentration of p-type impurities of
It can be seen that the peak between μm indicates the concentration of the n-type impurity in the region II, and the deeper portion indicates the concentration of the p-type impurity in the substrate 11 (region IV). It is possible to confirm that the area is formed.

FIG. 5 shows the potential profile when the gate electrode 15 is 0V. In the figure, the vertical axis represents voltage and the horizontal axis represents depth. From the figure, it can be seen that the voltage changes from the surface to a depth of about 0.35 μm (becomes a depletion layer), which indicates that the n-type region II
It can be seen that the depletion layer spreads even in the area of, reaching the substrate 11 (region IV).

FIG. 6 shows the drain current-gate voltage characteristic when the drain voltage is 0.05 V, and FIG. 7 shows the drain current in logarithmic display. It can be seen from FIG. 6 that the threshold voltage is a small value of about 0.4 V, and from the slope of the graph in FIG.
It can be seen that it is 0.3 mV / dec. This value is a normal MO
Despite being much smaller than the SFET and having a low threshold voltage, the leak current, which is the drain current when the gate electrode 15 is 0 V, is about 25.1 pA, which is extremely low at 1 pA or less per 1 μm gate width. Has a small value.

However, when the impurity implantation amount of phosphorus at the time of forming the region II is set to 5 × 10 ¹² cm ^-2 , as shown in the potential profile when the gate electrode 15 shown in FIG. It can be seen that the voltage is stable between 0.1 and 0.2 μm and the depletion layer does not reach the substrate 11. As a result, when examining the S coefficient, about 110 mV / d
It was a very large value of ec.

On the other hand, when the phosphorus impurity implantation amount when forming the region II is set to 3 × 10 ¹² cm ^-2 , as shown in the potential profile when the gate electrode 15 shown in FIG. Although the voltage changes between 0.1 and 0.3 μm, the voltage is stable near the depth of 0.05 μm, and the region II is depleted, but the region I is not completely depleted. I understand. As a result, the characteristics are normal M
It became the same as OSFET, and the S coefficient was a deteriorated value of about 90 mV / dec.

Here, when the abscissa represents the phosphorus injection amount and the S coefficient represents the vertical axis when forming the region II, the result is as shown in FIG. 10, and the S coefficient is obtained at a certain phosphorus injection amount. Therefore, it can be seen that there is an optimum implantation amount for obtaining a MOSFET having a low threshold voltage and a low leakage current. In the case of this MOSFET, (3.6-
4.4) It is in the range of 10 ¹² cm ^-2 . Further, the range of this implantation amount is the range of the amount in which the regions I and II are completely depleted. At this time, the S coefficient becomes a low value, and the MOS
The capacity of the FET is reduced. The total depth of the regions I and II is smaller than the depth (width) of the depletion layer.

Therefore, the conditions of each region in the MOSFET which is one embodiment of the semiconductor device of the present invention shown in FIGS. 1 and 3 are as follows. Depth direction width W of region I
1 is the depletion layer width Wg due to the gate voltage and p of the regions I and II.
The width is made smaller than the sum of the depletion layer width Wj1a formed in the region I by the n-junction (W1 <Wg + Wj1a). Area II
The width W2 in the depth direction is defined by the pn junction of the regions I and II.
It is made smaller than the sum of the depletion layer width Wj1b formed in II and the depletion layer width Wj2 due to the pn junction of the regions II and IV (W2
<Wj1b + Wj2). The width W3 in the depth direction of the region III is
It is made larger than the width W2 in the depth direction of II (W3> W2).
The lateral width W13 of the region III is the depletion layer width Wj3 due to the junction between the depletion layer width Wd of the source region 12 of the region II and the region II.
(W13> Wd + Wj3). Further, as a desirable condition, the substrate concentration N4 in the region IV is made thinner than the concentrations N1, N2, N3 in all the other regions I, II, III (N4 <N1, N2, N3).

Then, depending on these conditions, the following is obtained. The region I becomes an inversion state during operation and becomes a channel region responsible for carrier conduction. The threshold voltage of this MOSFET is controlled by the impurity concentration in the region I. The area II includes the area I and the substrate 11 (area I
V) and pn junction respectively, so region I and region II
This junction and the vicinity of the surface of the region IV are depleted. Therefore, the region II promotes depletion when a voltage is applied to the gate electrode 15 and reduces the apparent capacitance seen from the gate electrode 15. At the same time, the threshold voltage is reduced.

The region III prevents the depletion layer of the source region 12 from spreading and the region II and the source region 12 from becoming conductive. Further, the region III connects the regions I and IV to stabilize the potential of the region I. The impurity concentration of the region IV determines the capacitance of the source region 12 and the drain region 13. Since the punch-through is prevented by the region III, the impurity concentration of the region IV can be determined without taking this into consideration, and the impurity concentration of the source region 12 and the drain region 13 is made low to reduce the capacitance.

[0024]

According to the semiconductor device of the present invention, the width of the first region is within the first region due to the pn junction between the width of the depletion layer formed when a voltage is applied to the gate electrode and the second region. It is smaller than the sum of the width of the depletion layer formed, and the width of the second region is the width of the depletion layer formed in the second region by the pn junction with the first region and the fourth region. Pn with the substrate
Since it is smaller than the sum of the width of the depletion layer due to the junction, the depletion layer spreads to the substrate, and the capacitance of the semiconductor device can be sufficiently reduced. As a result, there is an effect that a low threshold voltage results in a low leak current.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a semiconductor device of the present invention.

2A to 2F are process diagrams showing an example of a method for manufacturing a semiconductor device.

FIG. 3 is a sectional view showing an embodiment of a semiconductor device of the present invention.

FIG. 4 is a graph showing an impurity profile in the depth direction of a channel portion.

FIG. 5 is a graph showing a potential profile when an impurity implantation amount of phosphorus is set to 3.8 × 10 ¹² cm ⁻² .

FIG. 6 is a graph showing drain current-gate voltage characteristics.

FIG. 7 is a graph showing drain current-gate voltage characteristics.

FIG. 8 is a graph showing a potential profile when the impurity implantation amount of phosphorus is set to 5 × 10 ¹² cm ⁻² .

FIG. 9 is a graph showing a potential profile when the impurity implantation amount of phosphorus is set to 3 × 10 ¹² cm ⁻² .

FIG. 10 is a graph showing the relationship between the impurity implantation amount of phosphorus and the S coefficient.

FIG. 11 is a configuration diagram showing a conventional example.

[Explanation of symbols]

1, 11 substrate 2, 12 source region 3, 13 drain region 4, 14, 14a gate insulating film 5, 15 gate electrode 16 side spacer 17 LDD region 18 B implanted layer (region I) 19 P implanted Layer (Region II) 20 n ^- layer

Claims (1)

[Claims] 1. A gate electrode formed by sandwiching a thin gate insulating film on a semiconductor substrate having a first conductivity type, and a second conductivity provided below the gate insulating film on both sides of the gate electrode. A source region and a drain region having a mold;
A second region having a second conductivity type formed in the substrate so as not to contact the gate insulating film and the source region and the drain region below the gate insulating film. A first region having a first conductivity type and formed between the gate insulating film and the second region; and a second region having a first conductivity type and the second region. Pn between the depletion layer formed by the source region and the drain region and formed between the source region and the drain region.
A third region having a width larger than the sum of the width of the depletion layer due to the junction, the width of the first region and the width of the depletion layer formed when a voltage is applied to the gate electrode; The width of the second region is smaller than the sum of the width of the depletion layer formed in the first region by the pn junction with the second region, and the width of the second region is the first region.
Is smaller than the sum of the width of the depletion layer formed in the second region by the pn junction with the region and the width of the depletion layer formed by the pn junction with the substrate that becomes the fourth region. Semiconductor device.