JP2546527B2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2546527B2
JP2546527B2 JP5326678A JP32667893A JP2546527B2 JP 2546527 B2 JP2546527 B2 JP 2546527B2 JP 5326678 A JP5326678 A JP 5326678A JP 32667893 A JP32667893 A JP 32667893A JP 2546527 B2 JP2546527 B2 JP 2546527B2
Authority
JP
Japan
Prior art keywords
stitch
package
stage
chip
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5326678A
Other languages
English (en)
Other versions
JPH07183423A (ja
Inventor
朗 白戸
俊弥 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5326678A priority Critical patent/JP2546527B2/ja
Publication of JPH07183423A publication Critical patent/JPH07183423A/ja
Application granted granted Critical
Publication of JP2546527B2 publication Critical patent/JP2546527B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体装置に関し、特に
ＰＳＧパッケージに関する。
【０００２】
【従来の技術】従来のＰＧＡパッケージは、パッドがス
タガータイプの多ピンＰＧＡの場合、図２に示すように
階段上にステッチ１０を設けてパッド１１の位置に合わ
せている。ボンディングは外側又は内側のパッドどちら
かにのみボンディングを行う。もう一つの方法に平行ボ
ンディングがあり、チップ上のパッドとステッチが相対
的に設けられており、ボンディングするさいは隣り合う
ボンディングワイヤーが接触をしないように、平行にボ
ンディングすることで内側と外側の両方のパッドを使用
できるようにしている。
【０００３】
【発明が解決しようとする課題】従来のＰＧＡパッケー
ジでは多ピンとなるとパット間隔が狭くなり外側パッド
内側パッドを両方とも使用してボンディングしようとす
ると隣り合うボンディングワイヤー同士が接触ショート
する危険性があった。また、平行ボンディングを行った
場合、外側パッドと内側パッドの両方にボンディングが
可能であるがパッドに合わせてステッチを設けるために
チップタイプ別のパッケージが必要となりパッケージの
汎用性がなくなってしまう。
【０００４】
【課題を解決するための手段】本発明の多ピンＰＧＡパ
ッケージは内側パッド用にステッチリードがチップ側に
せり出したステッチを２段目に備えている。
【０００５】
【実施例】本発明について図面を参照して説明する。図
１ (ａ）は本発明の半導体装置の断面図である。１段目
のパッケージ２には中央に多ピン用のチップ６が実装さ
れている。チップ上には図１ (ｃ）のように内側と外側
にパッド１１が設けられている。パッケージには対応し
たパッドとボンディングワイヤーによりボンディングさ
れるステッチの部分１０がありそのステッチは、パッケ
ージ下部の外部ピン５に接続されている。多ピン用のパ
ッケージではステッチ部の高さが複数の位置となるよう
階段状にしている。最上部には２段目のパッケージ１が
設けられ、外部ピン５に接続されるようにスルーホール
８が設けられている。ボンディングは階段状に高さの異
ったステッチ部１０とチップの外側パッドをボンディン
グする。２段目のパッケージ１は１段目のパッケージ２
がチップ６とボンディングされたあとに１段目のパッケ
ージに装着される。２段目のパッケージには１段目に装
着のさいに１段目のパッケージに設けられた外部ピンに
接続するための接続ピン７が設けられておりそれがステ
ッチ９につながっている。ステッチ９が設けられるステ
ッチリードは１段目でボンディングされているワイヤと
の接触保護の役目をもち、１段目の最も内側にあるステ
ッチにあわせてチップ側にせり出す形にする。チップの
内側とステッチ９をボンディングすることで１段目のボ
ンディングワイヤーとの接触を防止し、全パッドを使用
可能にする。
【０００６】
【発明の効果】以上説明したように本発明は、パッケー
ジを２段構成とし、２段目のパッケージのステッチのス
テッチリードをチップ側にせり出すようにしたので、チ
ップの外側と内側の両方のパッドをボンディングするこ
とが可能でボンディングワイヤー同士の接触もなくショ
ートしないという結果を有する。
【図面の簡単な説明】
【図１】本発明の一実施例を示す図
【図２】従来例を示す図
【符号の説明】
１ ２段目のパッケージ ２ １段目のパッケージ ３ キャップ ４ ボンディングワイヤー ５ ピン ６ チップ ７ １段目と２段目を接続するピン ８ スルーホール ９，１０ ステッチ １１ パッド

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項１】 スタガータイプのパッドが使用されてい
    るＰＧＡパッケージにおいて、高さの異なる複数段のス
    テッチリードを有し、最上段のステッチリードは下段の
    ステッチリード上までせり出したことを特徴とする半導
    体装置。
  2. 【請求項２】 前記最上段のステッチリード上に設けら
    れたステッチはチップ上に設けられた複数列パッドのう
    ち、内側パッドに接続されていることを特徴とする請求
    項１記載の半導体装置。
JP5326678A 1993-12-24 1993-12-24 半導体装置 Expired - Fee Related JP2546527B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5326678A JP2546527B2 (ja) 1993-12-24 1993-12-24 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5326678A JP2546527B2 (ja) 1993-12-24 1993-12-24 半導体装置

Publications (2)

Publication Number Publication Date
JPH07183423A JPH07183423A (ja) 1995-07-21
JP2546527B2 true JP2546527B2 (ja) 1996-10-23

Family

ID=18190439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5326678A Expired - Fee Related JP2546527B2 (ja) 1993-12-24 1993-12-24 半導体装置

Country Status (1)

Country Link
JP (1) JP2546527B2 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990056764A (ko) * 1997-12-29 1999-07-15 김영환 볼 그리드 어레이 패키지

Also Published As

Publication number Publication date
JPH07183423A (ja) 1995-07-21

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Effective date: 19960618

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