JP2025518666A5 - - Google Patents
Info
- Publication number
- JP2025518666A5 JP2025518666A5 JP2024565939A JP2024565939A JP2025518666A5 JP 2025518666 A5 JP2025518666 A5 JP 2025518666A5 JP 2024565939 A JP2024565939 A JP 2024565939A JP 2024565939 A JP2024565939 A JP 2024565939A JP 2025518666 A5 JP2025518666 A5 JP 2025518666A5
- Authority
- JP
- Japan
- Prior art keywords
- memory
- circuits
- coupled
- bit lines
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/836,634 | 2022-06-09 | ||
| US17/836,634 US11967394B2 (en) | 2022-06-09 | 2022-06-09 | Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods |
| PCT/US2023/019031 WO2023239471A1 (en) | 2022-06-09 | 2023-04-19 | Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025518666A JP2025518666A (ja) | 2025-06-19 |
| JP2025518666A5 true JP2025518666A5 (https=) | 2026-04-24 |
Family
ID=86332230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024565939A Pending JP2025518666A (ja) | 2022-06-09 | 2023-04-19 | フライングビット線を利用して有効なビット線長を大きくし、より高い性能と高められたメモリ密度をサポートするメモリアレイ、および関連方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US11967394B2 (https=) |
| EP (1) | EP4537335A1 (https=) |
| JP (1) | JP2025518666A (https=) |
| KR (1) | KR20250021458A (https=) |
| TW (1) | TW202349402A (https=) |
| WO (1) | WO2023239471A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20250335098A1 (en) * | 2024-04-30 | 2025-10-30 | Arm Limited | Access time in a memory array |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9305635B2 (en) | 2013-10-31 | 2016-04-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | High density memory structure |
| US9275686B2 (en) | 2014-05-28 | 2016-03-01 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Memory banks with shared input/output circuitry |
| US9928899B2 (en) * | 2015-12-29 | 2018-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) |
| CN117524279A (zh) | 2017-11-15 | 2024-02-06 | 三星电子株式会社 | 具有虚拟体化架构的sram及包括其的系统和方法 |
| KR102845639B1 (ko) * | 2019-08-07 | 2025-08-12 | 삼성전자주식회사 | 스토리지 장치 |
-
2022
- 2022-06-09 US US17/836,634 patent/US11967394B2/en active Active
-
2023
- 2023-04-19 JP JP2024565939A patent/JP2025518666A/ja active Pending
- 2023-04-19 KR KR1020247040935A patent/KR20250021458A/ko active Pending
- 2023-04-19 WO PCT/US2023/019031 patent/WO2023239471A1/en not_active Ceased
- 2023-04-19 EP EP23723321.8A patent/EP4537335A1/en active Pending
- 2023-05-08 TW TW112116928A patent/TW202349402A/zh unknown
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