KR20250021458A - 더 높은 성능, 증가된 메모리 밀도 및 관련 방법을 지원하기 위해 유효 비트 라인 길이를 늘리기 위해 플라잉 비트 라인을 사용하는 메모리 어레이 - Google Patents
더 높은 성능, 증가된 메모리 밀도 및 관련 방법을 지원하기 위해 유효 비트 라인 길이를 늘리기 위해 플라잉 비트 라인을 사용하는 메모리 어레이 Download PDFInfo
- Publication number
- KR20250021458A KR20250021458A KR1020247040935A KR20247040935A KR20250021458A KR 20250021458 A KR20250021458 A KR 20250021458A KR 1020247040935 A KR1020247040935 A KR 1020247040935A KR 20247040935 A KR20247040935 A KR 20247040935A KR 20250021458 A KR20250021458 A KR 20250021458A
- Authority
- KR
- South Korea
- Prior art keywords
- memory
- circuits
- circuit
- bit lines
- row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
- G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/836,634 | 2022-06-09 | ||
| US17/836,634 US11967394B2 (en) | 2022-06-09 | 2022-06-09 | Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods |
| PCT/US2023/019031 WO2023239471A1 (en) | 2022-06-09 | 2023-04-19 | Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20250021458A true KR20250021458A (ko) | 2025-02-13 |
Family
ID=86332230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020247040935A Pending KR20250021458A (ko) | 2022-06-09 | 2023-04-19 | 더 높은 성능, 증가된 메모리 밀도 및 관련 방법을 지원하기 위해 유효 비트 라인 길이를 늘리기 위해 플라잉 비트 라인을 사용하는 메모리 어레이 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US11967394B2 (https=) |
| EP (1) | EP4537335A1 (https=) |
| JP (1) | JP2025518666A (https=) |
| KR (1) | KR20250021458A (https=) |
| TW (1) | TW202349402A (https=) |
| WO (1) | WO2023239471A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20250335098A1 (en) * | 2024-04-30 | 2025-10-30 | Arm Limited | Access time in a memory array |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9305635B2 (en) | 2013-10-31 | 2016-04-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | High density memory structure |
| US9275686B2 (en) | 2014-05-28 | 2016-03-01 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Memory banks with shared input/output circuitry |
| US9928899B2 (en) * | 2015-12-29 | 2018-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) |
| CN117524279A (zh) | 2017-11-15 | 2024-02-06 | 三星电子株式会社 | 具有虚拟体化架构的sram及包括其的系统和方法 |
| KR102845639B1 (ko) * | 2019-08-07 | 2025-08-12 | 삼성전자주식회사 | 스토리지 장치 |
-
2022
- 2022-06-09 US US17/836,634 patent/US11967394B2/en active Active
-
2023
- 2023-04-19 JP JP2024565939A patent/JP2025518666A/ja active Pending
- 2023-04-19 KR KR1020247040935A patent/KR20250021458A/ko active Pending
- 2023-04-19 WO PCT/US2023/019031 patent/WO2023239471A1/en not_active Ceased
- 2023-04-19 EP EP23723321.8A patent/EP4537335A1/en active Pending
- 2023-05-08 TW TW112116928A patent/TW202349402A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| US20230402069A1 (en) | 2023-12-14 |
| JP2025518666A (ja) | 2025-06-19 |
| EP4537335A1 (en) | 2025-04-16 |
| WO2023239471A1 (en) | 2023-12-14 |
| TW202349402A (zh) | 2023-12-16 |
| US11967394B2 (en) | 2024-04-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| P11 | Amendment of application requested |
Free format text: ST27 STATUS EVENT CODE: A-2-2-P10-P11-NAP-X000 (AS PROVIDED BY THE NATIONAL OFFICE) |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |