TW202349402A - 用於支援更高效能、增加的記憶體密度的施用飛行位元線以增加有效位元線長度的記憶體陣列及相關方法 - Google Patents

用於支援更高效能、增加的記憶體密度的施用飛行位元線以增加有效位元線長度的記憶體陣列及相關方法 Download PDF

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Publication number
TW202349402A
TW202349402A TW112116928A TW112116928A TW202349402A TW 202349402 A TW202349402 A TW 202349402A TW 112116928 A TW112116928 A TW 112116928A TW 112116928 A TW112116928 A TW 112116928A TW 202349402 A TW202349402 A TW 202349402A
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TW
Taiwan
Prior art keywords
memory
circuits
circuit
row
coupled
Prior art date
Application number
TW112116928A
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English (en)
Chinese (zh)
Inventor
普拉莫德 柯勒
羅伯特Ａ 斯威澤
Original Assignee
美商微軟技術授權有限責任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 美商微軟技術授權有限責任公司 filed Critical 美商微軟技術授權有限責任公司
Publication of TW202349402A publication Critical patent/TW202349402A/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW112116928A 2022-06-09 2023-05-08 用於支援更高效能、增加的記憶體密度的施用飛行位元線以增加有效位元線長度的記憶體陣列及相關方法 TW202349402A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/836,634 2022-06-09
US17/836,634 US11967394B2 (en) 2022-06-09 2022-06-09 Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods

Publications (1)

Publication Number Publication Date
TW202349402A true TW202349402A (zh) 2023-12-16

Family

ID=86332230

Family Applications (1)

Application Number Title Priority Date Filing Date
TW112116928A TW202349402A (zh) 2022-06-09 2023-05-08 用於支援更高效能、增加的記憶體密度的施用飛行位元線以增加有效位元線長度的記憶體陣列及相關方法

Country Status (6)

Country Link
US (1) US11967394B2 (https=)
EP (1) EP4537335A1 (https=)
JP (1) JP2025518666A (https=)
KR (1) KR20250021458A (https=)
TW (1) TW202349402A (https=)
WO (1) WO2023239471A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250335098A1 (en) * 2024-04-30 2025-10-30 Arm Limited Access time in a memory array

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9305635B2 (en) 2013-10-31 2016-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. High density memory structure
US9275686B2 (en) 2014-05-28 2016-03-01 Avago Technologies General Ip (Singapore) Pte. Ltd. Memory banks with shared input/output circuitry
US9928899B2 (en) * 2015-12-29 2018-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)
CN117524279A (zh) 2017-11-15 2024-02-06 三星电子株式会社 具有虚拟体化架构的sram及包括其的系统和方法
KR102845639B1 (ko) * 2019-08-07 2025-08-12 삼성전자주식회사 스토리지 장치

Also Published As

Publication number Publication date
US20230402069A1 (en) 2023-12-14
KR20250021458A (ko) 2025-02-13
JP2025518666A (ja) 2025-06-19
EP4537335A1 (en) 2025-04-16
WO2023239471A1 (en) 2023-12-14
US11967394B2 (en) 2024-04-23

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