JP2024517141A5 - - Google Patents

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Publication number
JP2024517141A5
JP2024517141A5 JP2023565476A JP2023565476A JP2024517141A5 JP 2024517141 A5 JP2024517141 A5 JP 2024517141A5 JP 2023565476 A JP2023565476 A JP 2023565476A JP 2023565476 A JP2023565476 A JP 2023565476A JP 2024517141 A5 JP2024517141 A5 JP 2024517141A5
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JP
Japan
Prior art keywords
multiplexer
sram
performance level
bit cells
bit
Prior art date
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JP2023565476A
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English (en)
Japanese (ja)
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JP2024517141A (ja
JP7695392B2 (ja
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Priority claimed from US17/359,253 external-priority patent/US11527270B2/en
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Publication of JP2024517141A publication Critical patent/JP2024517141A/ja
Publication of JP2024517141A5 publication Critical patent/JP2024517141A5/ja
Application granted granted Critical
Publication of JP7695392B2 publication Critical patent/JP7695392B2/ja
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JP2023565476A 2021-05-06 2022-05-05 ハイブリッドライブラリラッチアレイ Active JP7695392B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202163185207P 2021-05-06 2021-05-06
US63/185,207 2021-05-06
US17/359,253 2021-06-25
US17/359,253 US11527270B2 (en) 2021-05-06 2021-06-25 Hybrid library latch array
PCT/US2022/027791 WO2022235879A1 (en) 2021-05-06 2022-05-05 Hybrid library latch array

Publications (3)

Publication Number Publication Date
JP2024517141A JP2024517141A (ja) 2024-04-19
JP2024517141A5 true JP2024517141A5 (https=) 2025-04-15
JP7695392B2 JP7695392B2 (ja) 2025-06-18

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ID=83932929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023565476A Active JP7695392B2 (ja) 2021-05-06 2022-05-05 ハイブリッドライブラリラッチアレイ

Country Status (5)

Country Link
US (1) US11527270B2 (https=)
EP (1) EP4334938B1 (https=)
JP (1) JP7695392B2 (https=)
KR (1) KR20240004963A (https=)
WO (1) WO2022235879A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118866031B (zh) * 2023-04-13 2025-09-26 长鑫存储技术有限公司 数据生成电路、存储器及数据生成电路的确定方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10340584A (ja) * 1997-06-09 1998-12-22 Nec Corp 半導体記憶装置
JP5057739B2 (ja) * 2006-10-03 2012-10-24 株式会社東芝 半導体記憶装置
WO2008131058A2 (en) 2007-04-17 2008-10-30 Rambus Inc. Hybrid volatile and non-volatile memory device
US8874831B2 (en) 2007-06-01 2014-10-28 Netlist, Inc. Flash-DRAM hybrid memory module
US7928761B2 (en) * 2007-09-06 2011-04-19 Tabula, Inc. Configuration context switcher with a latch
US7835175B2 (en) * 2008-10-13 2010-11-16 Mediatek Inc. Static random access memories and access methods thereof
JP2010170595A (ja) * 2009-01-20 2010-08-05 Panasonic Corp 半導体記憶装置
KR20130033230A (ko) 2011-09-26 2013-04-03 삼성전자주식회사 하이브리드 메모리 장치, 이를 포함하는 시스템, 및 하이브리드 메모리장치의 데이터 기입 및 독출 방법
US8693235B2 (en) 2011-12-06 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for finFET SRAM arrays in integrated circuits
JP2013206512A (ja) * 2012-03-29 2013-10-07 Kyushu Institute Of Technology 半導体記憶装置
WO2014070852A1 (en) * 2012-10-31 2014-05-08 Marvell World Trade Ltd. Sram cells suitable for fin field-effect transistor (finfet) process
US8913455B1 (en) * 2013-07-29 2014-12-16 Xilinx, Inc. Dual port memory cell
US9921980B2 (en) 2013-08-12 2018-03-20 Micron Technology, Inc. Apparatuses and methods for configuring I/Os of memory for hybrid memory modules
US9711194B2 (en) 2015-01-28 2017-07-18 Xilinx, Inc. Circuits for and methods of controlling the operation of a hybrid memory system
CN108511014A (zh) * 2018-02-07 2018-09-07 宁波大学 一种基于FinFET的存储单元
US10803928B2 (en) * 2018-06-18 2020-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Low voltage memory device
US10878893B1 (en) * 2019-06-04 2020-12-29 Arm Limited Control architecture for column decoder circuitry

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