KR20240004963A - 하이브리드 라이브러리 래치 어레이 - Google Patents

하이브리드 라이브러리 래치 어레이 Download PDF

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Publication number
KR20240004963A
KR20240004963A KR1020237041855A KR20237041855A KR20240004963A KR 20240004963 A KR20240004963 A KR 20240004963A KR 1020237041855 A KR1020237041855 A KR 1020237041855A KR 20237041855 A KR20237041855 A KR 20237041855A KR 20240004963 A KR20240004963 A KR 20240004963A
Authority
KR
South Korea
Prior art keywords
multiplexer
sram
bit cells
bit
performance level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020237041855A
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English (en)
Korean (ko)
Inventor
존 제이. 우
러셀 제이. 슈라이버
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20240004963A publication Critical patent/KR20240004963A/ko
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1009—Data masking during input/output
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
KR1020237041855A 2021-05-06 2022-05-05 하이브리드 라이브러리 래치 어레이 Pending KR20240004963A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202163185207P 2021-05-06 2021-05-06
US63/185,207 2021-05-06
US17/359,253 2021-06-25
US17/359,253 US11527270B2 (en) 2021-05-06 2021-06-25 Hybrid library latch array
PCT/US2022/027791 WO2022235879A1 (en) 2021-05-06 2022-05-05 Hybrid library latch array

Publications (1)

Publication Number Publication Date
KR20240004963A true KR20240004963A (ko) 2024-01-11

Family

ID=83932929

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020237041855A Pending KR20240004963A (ko) 2021-05-06 2022-05-05 하이브리드 라이브러리 래치 어레이

Country Status (5)

Country Link
US (1) US11527270B2 (https=)
EP (1) EP4334938B1 (https=)
JP (1) JP7695392B2 (https=)
KR (1) KR20240004963A (https=)
WO (1) WO2022235879A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118866031B (zh) * 2023-04-13 2025-09-26 长鑫存储技术有限公司 数据生成电路、存储器及数据生成电路的确定方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10340584A (ja) * 1997-06-09 1998-12-22 Nec Corp 半導体記憶装置
JP5057739B2 (ja) * 2006-10-03 2012-10-24 株式会社東芝 半導体記憶装置
WO2008131058A2 (en) 2007-04-17 2008-10-30 Rambus Inc. Hybrid volatile and non-volatile memory device
US8874831B2 (en) 2007-06-01 2014-10-28 Netlist, Inc. Flash-DRAM hybrid memory module
US7928761B2 (en) * 2007-09-06 2011-04-19 Tabula, Inc. Configuration context switcher with a latch
US7835175B2 (en) * 2008-10-13 2010-11-16 Mediatek Inc. Static random access memories and access methods thereof
JP2010170595A (ja) * 2009-01-20 2010-08-05 Panasonic Corp 半導体記憶装置
KR20130033230A (ko) 2011-09-26 2013-04-03 삼성전자주식회사 하이브리드 메모리 장치, 이를 포함하는 시스템, 및 하이브리드 메모리장치의 데이터 기입 및 독출 방법
US8693235B2 (en) 2011-12-06 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for finFET SRAM arrays in integrated circuits
JP2013206512A (ja) * 2012-03-29 2013-10-07 Kyushu Institute Of Technology 半導体記憶装置
WO2014070852A1 (en) * 2012-10-31 2014-05-08 Marvell World Trade Ltd. Sram cells suitable for fin field-effect transistor (finfet) process
US8913455B1 (en) * 2013-07-29 2014-12-16 Xilinx, Inc. Dual port memory cell
US9921980B2 (en) 2013-08-12 2018-03-20 Micron Technology, Inc. Apparatuses and methods for configuring I/Os of memory for hybrid memory modules
US9711194B2 (en) 2015-01-28 2017-07-18 Xilinx, Inc. Circuits for and methods of controlling the operation of a hybrid memory system
CN108511014A (zh) * 2018-02-07 2018-09-07 宁波大学 一种基于FinFET的存储单元
US10803928B2 (en) * 2018-06-18 2020-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Low voltage memory device
US10878893B1 (en) * 2019-06-04 2020-12-29 Arm Limited Control architecture for column decoder circuitry

Also Published As

Publication number Publication date
EP4334938A1 (en) 2024-03-13
US20220366945A1 (en) 2022-11-17
EP4334938B1 (en) 2026-02-18
JP2024517141A (ja) 2024-04-19
EP4334938A4 (en) 2025-01-08
US11527270B2 (en) 2022-12-13
JP7695392B2 (ja) 2025-06-18
WO2022235879A1 (en) 2022-11-10

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