JP2025511052A5 - - Google Patents
Info
- Publication number
- JP2025511052A5 JP2025511052A5 JP2024557703A JP2024557703A JP2025511052A5 JP 2025511052 A5 JP2025511052 A5 JP 2025511052A5 JP 2024557703 A JP2024557703 A JP 2024557703A JP 2024557703 A JP2024557703 A JP 2024557703A JP 2025511052 A5 JP2025511052 A5 JP 2025511052A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- piezoelectric
- substrate
- trap
- poi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2202900A FR3134238B1 (fr) | 2022-03-30 | 2022-03-30 | Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI) |
| FR2202900 | 2022-03-30 | ||
| PCT/EP2023/058282 WO2023187050A1 (fr) | 2022-03-30 | 2023-03-30 | Substrat piézoélectrique sur isolant (poi) et procédé de fabrication d'un substrat piézoélectrique sur isolant (poi) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025511052A JP2025511052A (ja) | 2025-04-15 |
| JP2025511052A5 true JP2025511052A5 (https=) | 2026-03-24 |
Family
ID=82385323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024557703A Pending JP2025511052A (ja) | 2022-03-30 | 2023-03-30 | ピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板およびピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板を製造するための方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US20250211199A1 (https=) |
| EP (1) | EP4500583A1 (https=) |
| JP (1) | JP2025511052A (https=) |
| KR (1) | KR20240169041A (https=) |
| CN (1) | CN119173996A (https=) |
| FR (1) | FR3134238B1 (https=) |
| TW (1) | TW202404134A (https=) |
| WO (1) | WO2023187050A1 (https=) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9768056B2 (en) * | 2013-10-31 | 2017-09-19 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition |
| FR3053532B1 (fr) * | 2016-06-30 | 2018-11-16 | Soitec | Structure hybride pour dispositif a ondes acoustiques de surface |
-
2022
- 2022-03-30 FR FR2202900A patent/FR3134238B1/fr active Active
-
2023
- 2023-03-30 CN CN202380039083.2A patent/CN119173996A/zh active Pending
- 2023-03-30 TW TW112112149A patent/TW202404134A/zh unknown
- 2023-03-30 EP EP23715527.0A patent/EP4500583A1/fr active Pending
- 2023-03-30 JP JP2024557703A patent/JP2025511052A/ja active Pending
- 2023-03-30 US US18/852,209 patent/US20250211199A1/en active Pending
- 2023-03-30 KR KR1020247035694A patent/KR20240169041A/ko active Pending
- 2023-03-30 WO PCT/EP2023/058282 patent/WO2023187050A1/fr not_active Ceased
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