Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/704—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings
  • H10N30/706—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings characterised by the underlying bases, e.g. substrates
  • H10N30/708—Intermediate layers, e.g. barrier, adhesion or growth control buffer layers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
  • H03H9/02—Details
  • H03H9/02535—Details of surface acoustic wave devices
  • H03H9/02818—Means for compensation or elimination of undesirable effects
  • H03H9/02952—Means for compensation or elimination of undesirable effects of parasitic capacitance
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
  • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
  • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
  • H03H9/02—Details
  • H03H9/02535—Details of surface acoustic wave devices
  • H03H9/02543—Characteristics of substrate, e.g. cutting angles
  • H03H9/02559—Characteristics of substrate, e.g. cutting angles of lithium niobate or lithium-tantalate substrates
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
  • H03H9/02—Details
  • H03H9/02535—Details of surface acoustic wave devices
  • H03H9/02543—Characteristics of substrate, e.g. cutting angles
  • H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N30/00—Piezoelectric or electrostrictive devices
  • H10N30/01—Manufacture or treatment
  • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
  • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
  • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Definitions

• Piezoelectric substrate on insulator (POI) and method of manufacturing a piezoelectric substrate on insulator (POI)
• the invention relates to a piezoelectric substrate on insulator (POI) comprising in this order a support substrate, a trapping structure, a dielectric layer and a piezoelectric layer, as well as a method of manufacturing such a POI substrate.
• POI piezoelectric substrate on insulator
• Such substrates are known in the state of the art.
• devices such as sensors or filters are made.
• the trapping structure makes it possible to reduce losses linked to parasitic effects at the interface between the support substrate and the dielectric layer.
• the trapping layer which is inserted between the support substrate and the dielectric layer, serves to reduce the density of free carriers and to prevent variations in the Fermi level. This results in a higher and constant resistivity in the supporting substrate, which allows a reduction of parasitic effects such as signal attenuation, generation of harmonic signals or conductive coupling.
• the object of the invention is therefore to reduce the harmful effect of the diffusion of metallic elements through the structure of the POI substrate.
• a piezoelectric substrate on insulator comprising: a support substrate, in particular a silicon-based substrate, a piezoelectric layer, in particular a layer of lithium tantalate (LTO ) or lithium niobate (LNO), a dielectric layer, in particular a silicon oxide layer, sandwiched between the piezoelectric layer and the support substrate, a trapping structure sandwiched between the dielectric layer and the support substrate, characterized in that the trapping structure comprises at least two trapping layers, the trapping layers being separated from each other by a dielectric intermediate layer.
• a support substrate in particular a silicon-based substrate
• a piezoelectric layer in particular a layer of lithium tantalate (LTO ) or lithium niobate (LNO)
• LTO lithium tantalate
• LNO lithium niobate
• a dielectric layer in particular a silicon oxide layer
• the separation of the trapping structure into at least two trapping layers with a dielectric layer between two trapping layers makes it possible to segregate part of the contamination by the metallic elements at the interfaces between the trapping layers, the intermediate layer thus reducing the level accumulation of metallic elements at the interface between the trapping structure and the support substrate.
• the support substrate may preferably have a resistivity greater than or equal to 500Q.cm
• the trapping layers of the POI substrate can be based on polycrystalline or amorphous or porous silicon or based on silicon carbide (SiC). Such layers effectively reduce parasitic effects.
• the dielectric intermediate layer of the POI substrate may be a layer of silicon oxide, in particular a layer of native silicon oxide or a layer deposited by chemical vapor deposition (CVD) or a layer obtained by thermal oxidation. Silicon oxides are easy to produce and at the same time we can observe an accumulation of metallic elements diffused at the interfaces of the intermediate layers of the trapping structure.
• CVD chemical vapor deposition
• the dielectric intermediate layer(s) of the POI substrate may have a thickness equal to or less than 5 nm, in particular equal to or less than 1 nm. Even layers of such low thickness show an effect on reducing parasitic effects.
• At least two of the at least two trapping layers may have one or more physical properties, in particular a different grain size. This makes it possible to further improve the suppression of parasitic effects.
• each trapping layer of the POI substrate can have the same thickness.
• at least one trapping layer of the POI substrate may have a thickness different from the other trapping layers. This makes it possible to optimize the properties of the POI substrate.
• the trapping structure of the POI substrate may have a thickness equal to or less than 5 pm, preferably equal to or less than 2 pm.
• the object of the invention is also achieved by the method of manufacturing a piezoelectric substrate on insulator (POI) as described above and comprising the steps of: providing a support substrate, in particular a substrate with silicon base, provide a substrate comprising a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO), form a trapping structure above the support substrate, form a dielectric layer, in particular a layer of silicon oxide, above the substrate comprising a piezoelectric layer and/or above the trapping structure, assembling the substrate comprising a piezoelectric layer with the support substrate such as the dielectric layer and the structure of trapping are sandwiched between the piezoelectric layer and the support substrate, characterized in that the step of forming the trapping structure comprises forming a first trapping layer, forming a dielectric intermediate layer on the first trapping layer and forming a second layer trapping on the dielectric intermediate layer.
• LTO lithium tantalate
• LNO lithium
• the method of manufacturing a piezoelectric substrate may further comprise a step of: forming a weakening zone inside the piezoelectric layer, and producing a fracture along the weakening zone to separate part of the piezoelectric layer from the remainder of the substrate comprising the piezoelectric layer after the assembly step to transfer the part of the piezoelectric layer to the support substrate.
• This process makes it possible to manufacture the POI substrates according to the invention in an industrial manner.
• Figure 1 schematically represents a piezoelectric substrate on insulator (POI) according to a first embodiment of the invention.
• Figure 2 schematically represents a piezoelectric substrate on insulator (POI) according to a second embodiment of the invention.
• Figure 3 schematically represents a piezoelectric substrate on insulator (POI) according to a third embodiment of the invention.
• Figure 4 schematically represents a method of manufacturing a piezoelectric substrate on insulator (POI) according to a fourth embodiment of the invention.
• Figure 1 schematically represents a piezoelectric substrate on insulator (POI) 100 according to the first embodiment of the invention.
• the piezoelectric substrate on insulator 100 comprises a support substrate 102.
• the support substrate 102 is a silicon-based substrate, in particular a monocrystalline silicon wafer.
• the support substrate preferably has a resistivity greater than or equal to 500 ⁇ .cm.
• a trapping structure 104 is arranged above the support substrate 102.
• the trapping structure 104 can be in direct contact with the support substrate 102.
• the trapping structure 104 has a thickness equal to or less than 5 ⁇ m, preferably equal to or less than 2pm.
• the trapping structure 104 comprises three layers: a first trapping layer 104a, an intermediate dielectric layer 104b and a second trapping layer 104c.
• the trapping layers 104a, 104c are based on polycrystalline or amorphous or porous silicon or based on silicon carbide (SiC). Preferably these are layers deposited by low pressure chemical vapor deposition (LPCVD). In this embodiment the two trapping layers 104a, 104c have the same thickness.
• the dielectric intermediate layer 104b may be a layer of silicon oxide, preferably a layer of native silicon oxide. According to variants, the dielectric intermediate layer can also be formed by chemical vapor deposition (CVD) or by thermal oxidation.
• the dielectric intermediate layer 104b preferably has a thinner thickness than the trapping layers 104a, 104b, in particular a thickness which is equal to or less than 5 nm, in particular equal to or less than 1 nm.
• a dielectric layer 106 is arranged above, in particular directly on the trapping structure 104.
• the dielectric layer 106 is preferably a layer based on silicon oxide.
• the dielectric layer 106 preferably has a thickness between 100nm and 1 pm, in particular between 200nm and 700nm.
• the dielectric layer 106 can be formed by CVD deposition or any other suitable deposition process.
• a piezoelectric layer 108 is arranged above, in particular directly on the dielectric layer 106. This is preferably a layer of lithium tantalate (LTO) or lithium niobate (LNO). The piezoelectric layer 108 typically has a thickness of between 200nm and 1 pm.
• LTO lithium tantalate
• LNO lithium niobate
• the two trapping layers 104a and 104c may have one or more different physical properties, such as grain size.
• the separation of the trapping structure 104 into at least two trapping layers 104a, 104c with an intermediate dielectric layer 104b between the two trapping layers 104a, 104c makes it possible to segregate part of the contamination by the metallic elements at the interfaces. between the trapping layers 104a, 104c and the intermediate layer 104b thus reducing the concentration of metallic elements at the interface between the trapping structure 104 and the support substrate 102. Thus, it is compensated for the reduction in the suppression of parasitic effects .
• Figure 2 schematically represents a piezoelectric substrate on insulator (POI) 200 according to a second embodiment of the invention.
• the piezoelectric substrate on insulator 200 comprises the support substrate 102, the dielectric layer 106 and the piezoelectric layer 108 of the first embodiment. A further description of these layers and their properties is omitted and reference is made to their description above in relation to the first embodiment.
• the trapping structure 204 comprises a total of five trapping layers 204a, 204c, 204e, 204g and 204i.
• An intermediate dielectric layer 204b, 204d, 204f and 204h is each time interposed between two trapping layers.
• the trapping layers 204a, 204c, 204e, 204g and 204i are made in the same way as the trapping layers 104a and 104c of the first embodiment and they have the same physical properties than the latter. In particular, they all have the same thicknesses, in particular all have a thickness of 0.2 ⁇ m or less.
• the dielectric intermediate layers 204b, 204d, 204f and 204h are made in the same way as the dielectric intermediate layer 104b of the first embodiment and they have the same physical properties as the latter. In particular, they all have the same thicknesses, in particular all a thickness of a few tenths of a nanometer (a few Angstroms), in particular one or less nanometer (10 or less Angstrom).
• the concentration of metallic elements, in particular lithium, at the interface between the first trapping layer 204a and the support substrate 102 can be further reduced, because metallic elements are trapped at each interface.
• the quantity of metallic elements which reach the interface with the support substrate 102 is lower than in a structure with fewer interfaces.
• more or fewer trapping layers and dielectric intermediate layers can be provided in the trapping structure, depending on the concentration level of metallic elements considered acceptable for a given application.
• Figure 3 schematically represents a piezoelectric substrate on insulator (POI) 300 according to a third embodiment of the invention.
• the piezoelectric substrate on insulator 300 comprises the support substrate 102, the dielectric layer 106 and the piezoelectric layer 108 of the first embodiment. These layers and their properties will not be described again but reference is made to their description in the first embodiment.
• the trapping structure 304 comprises several trapping layers 304a, 304c, 304e, 304g, 304i and 304k, which as in the second embodiment are separated by dielectric intermediate layers 304b, 304d, 304f, 304h, 304j.
• the dielectric intermediate layers 304b, 304d, 304f, 304h, 304j are produced as in the first or second embodiment and have the same thicknesses, for example a few tenths of a nanometer (a few Angstroms), in particular a or less nanometer (10 Angstrom or less).
• the trapping layer 304a is thicker, in particular of a thickness of 0.5pm or more
• the concentration of metallic elements, in particular lithium, at the interface between the first trapping layer 304a and the support substrate 102 can be reduced as in the second mode of realization.
• Layer 304a at the interface with the support substrate 102 is thicker and thus retains its trapping properties.
• more or fewer trapping layers and dielectric intermediate layers can be provided in the trapping structure depending on the level of accumulation of metallic elements considered acceptable for a given application.
• Figure 4 schematically represents a method of manufacturing a piezoelectric substrate on insulator (POI) according to the fourth embodiment of the invention to obtain a POI substrate 100 according to the first embodiment as described below above in relation to Figure 1.
• the reference numbers already used in the description of the POI substrate 100 in Figure 1 are reused for the description of the process.
• the method of manufacturing a piezoelectric substrate on insulator (POI) 100 begins with step I) of providing a support substrate 102, in particular a silicon-based substrate, in particular a monocrystalline silicon wafer.
• step II) provides for the formation of the trapping structure 104 on a free surface 120 of the support substrate 102.
• the formation of the trapping structure 104 begins with the formation of a first trapping layer 104a produced by low pressure chemical vapor deposition (LPCVD).
• LPCVD low pressure chemical vapor deposition
• the formation can be carried out by a thermal growth technique or by physical vapor deposition (PVD).
• the trapping layer 104a formed on the support substrate 102 is a layer based on polycrystalline, amorphous or porous silicon or based on silicon carbide.
• the thickness of the trapping layer 104a is equal to or less than 2.5 pm, in particular equal to or less than 1 pm.
• an intermediate dielectric layer 104b is formed on the first trapping layer 104a.
• the dielectric intermediate layer 104b may be a layer of silicon oxide, preferably a layer of native silicon oxide. According to one of the variants, the dielectric intermediate layer is formed by chemical vapor deposition (CVD) or by thermal oxidation.
• the dielectric intermediate layer 104b preferably has a thickness thinner than the first trapping layer 104a, in particular a thickness which is less than 5 nm, in particular less than 1 nm.
• a second trapping layer 104c is formed on the dielectric intermediate layer 104b in the same manner as the first trapping layer 104a and in particular with the same thickness.
• the two trapping layers 104a and 104c can be formed with one or more different physical properties, such as grain size.
• the two trapping layers 104a and 104c may be based on different materials, among those named above.
• layer 104a may be made of porous silicon and layer 104a of polycrystalline silicon.
• a dielectric layer 106a is formed on the free surface 122 of the second trapping layer 104c.
• the dielectric layer 106a is preferably a silicon oxide layer formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD).
• layer 106a is formed by oxidation of polycrystalline silicon.
• the dielectric layer 106a preferably has a thickness equal to or less than 1 pm, in particular equal to or less than 700 nm.
• a heat treatment can be carried out after deposition of the dielectric layer 106a to densify it.
• a substrate 124 comprising a piezoelectric layer 126, in particular a substrate 124 comprising lithium tantalate (LTO) or lithium niobate (LNO) is provided.
• the piezoelectric layer 124 is in this embodiment arranged above a base substrate 126.
• the piezoelectric layer 126 is a solid layer and forms the entire substrate 124.
• a second dielectric layer 106b in particular a layer of silicon oxide, is produced on the free surface 130 of the piezoelectric layer 126.
• This layer is produced in the same manner as the layer dielectric 106a formed during step III).
• the thickness is chosen such that the sum of the thicknesses of the two dielectric layers 106a and 106b is between 100nm and 1 pm, in particular between 200nm and 700nm.
• one or more surface treatment steps of the free surface 130 of the substrate 124 comprising a piezoelectric layer can be carried out before the formation of the dielectric layer 106b.
• a surface activation treatment can be carried out, such as a plasma treatment and/or an ozone-based treatment.
• step VI) the substrate 124 obtained after step V) is assembled with the support substrate 102 obtained in assembly step III) to form a support substrate - substrate assembly 132 comprising a layer piezoelectric.
• the assembly is implemented in such a way that the dielectric layers 106a and 106b are placed in direct contact. Assembly is preferably carried out by molecular adhesion.
• a thinning step VII) of the assembly 132 is carried out to obtain the POI substrate 100 with a thinner piezoelectric layer 108, as illustrated in Figure 1.
• the thinning step can be carried out by grinding or by a step of forming a weakening zone in the piezoelectric layer 126 before the assembly step VI so as to delimit the piezoelectric layer 108 to be transferred to the support substrate 102 and fracturing.
• This step of forming a weakening zone is carried out by implantation of atomic or ionic species in the piezoelectric layer 126.
• the atomic or ionic implantation can be carried out in such a way that the weakening zone is located inside the piezoelectric layer 126 and delimits a piezoelectric layer 108 to be transferred from the rest of the piezoelectric layer 126.
• a step of fracturing the assembly 132 by supplying thermal and/or mechanical energy to the level of the weakening zone of the piezoelectric layer 126 is then carried out to obtain the piezoelectric substrate on insulator (POI) 100.
• the bonding between the support substrate 102 and the substrate 124 can also be done between the trapping structure 104 and the dielectric layer 106b, that is to say without carrying out step III), or between the dielectric layer 106a and the piezoelectric layer 126.
• one or more steps of cleaning, brushing or polishing the surface directly below can be carried out to remove the presence of particles and dust.
• the method can also be applied to obtain the POI substrates 200 and 300 of the second and third embodiment of the invention described in connection with Figure 2 and Figure 3 respectively.

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• Physics & Mathematics (AREA)
• Acoustics & Sound (AREA)
• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Chemical & Material Sciences (AREA)
• Materials Engineering (AREA)
• Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
• Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

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Publications (1)

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Citations (2)

• 2022
  • 2022-03-30 FR FR2202900A patent/FR3134238B1/fr active Active
• 2023
  • 2023-03-30 CN CN202380039083.2A patent/CN119173996A/zh active Pending
  • 2023-03-30 TW TW112112149A patent/TW202404134A/zh unknown
  • 2023-03-30 EP EP23715527.0A patent/EP4500583A1/fr active Pending
  • 2023-03-30 JP JP2024557703A patent/JP2025511052A/ja active Pending
  • 2023-03-30 US US18/852,209 patent/US20250211199A1/en active Pending
  • 2023-03-30 KR KR1020247035694A patent/KR20240169041A/ko active Pending
  • 2023-03-30 WO PCT/EP2023/058282 patent/WO2023187050A1/fr not_active Ceased

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