JP2025511052A - ピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板およびピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板を製造するための方法 - Google Patents

ピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板およびピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板を製造するための方法 Download PDF

Info

Publication number
JP2025511052A
JP2025511052A JP2024557703A JP2024557703A JP2025511052A JP 2025511052 A JP2025511052 A JP 2025511052A JP 2024557703 A JP2024557703 A JP 2024557703A JP 2024557703 A JP2024557703 A JP 2024557703A JP 2025511052 A JP2025511052 A JP 2025511052A
Authority
JP
Japan
Prior art keywords
layer
substrate
piezoelectric
poi
trapping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024557703A
Other languages
English (en)
Japanese (ja)
Other versions
JP2025511052A5 (https=
Inventor
ラファエル カウルミローネ，
フレデリック アリベール，
イザベル ベルトラン，
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of JP2025511052A publication Critical patent/JP2025511052A/ja
Publication of JP2025511052A5 publication Critical patent/JP2025511052A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/704—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings
    • H10N30/706—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings characterised by the underlying bases, e.g. substrates
    • H10N30/708—Intermediate layers, e.g. barrier, adhesion or growth control buffer layers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02818—Means for compensation or elimination of undesirable effects
    • H03H9/02952—Means for compensation or elimination of undesirable effects of parasitic capacitance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02559—Characteristics of substrate, e.g. cutting angles of lithium niobate or lithium-tantalate substrates
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Landscapes

  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
JP2024557703A 2022-03-30 2023-03-30 ピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板およびピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板を製造するための方法 Pending JP2025511052A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR2202900A FR3134238B1 (fr) 2022-03-30 2022-03-30 Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)
FR2202900 2022-03-30
PCT/EP2023/058282 WO2023187050A1 (fr) 2022-03-30 2023-03-30 Substrat piézoélectrique sur isolant (poi) et procédé de fabrication d'un substrat piézoélectrique sur isolant (poi)

Publications (2)

Publication Number Publication Date
JP2025511052A true JP2025511052A (ja) 2025-04-15
JP2025511052A5 JP2025511052A5 (https=) 2026-03-24

Family

ID=82385323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024557703A Pending JP2025511052A (ja) 2022-03-30 2023-03-30 ピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板およびピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板を製造するための方法

Country Status (8)

Country Link
US (1) US20250211199A1 (https=)
EP (1) EP4500583A1 (https=)
JP (1) JP2025511052A (https=)
KR (1) KR20240169041A (https=)
CN (1) CN119173996A (https=)
FR (1) FR3134238B1 (https=)
TW (1) TW202404134A (https=)
WO (1) WO2023187050A1 (https=)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9768056B2 (en) * 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
FR3053532B1 (fr) * 2016-06-30 2018-11-16 Soitec Structure hybride pour dispositif a ondes acoustiques de surface

Also Published As

Publication number Publication date
US20250211199A1 (en) 2025-06-26
TW202404134A (zh) 2024-01-16
FR3134238B1 (fr) 2024-08-23
FR3134238A1 (fr) 2023-10-06
WO2023187050A1 (fr) 2023-10-05
KR20240169041A (ko) 2024-12-02
CN119173996A (zh) 2024-12-20
EP4500583A1 (fr) 2025-02-05

Similar Documents

Publication Publication Date Title
JP7262415B2 (ja) 複合基板およびその製造方法
CN115694391A (zh) 复合衬底的制造方法、复合衬底及声表面波滤波器
CN114499432B (zh) 一种异质薄膜衬底、其制备方法和滤波器
JP2025511029A (ja) ピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板およびピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板を製造するための方法
JP2025511052A (ja) ピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板およびピエゾエレクトリックオンインシュレータ（ｐｏｉ）基板を製造するための方法
JP2009141230A (ja) 半導体装置の製造方法および半導体装置製造用スパッタ装置
JP7612721B2 (ja) 複合基板、弾性表面波素子および複合基板の製造方法
JP7752128B2 (ja) 高周波デバイスのための、圧電層を転写するのに使用できる圧電構造体を製造するための方法、及びそのような圧電層を転写するための方法
CN116193965A (zh) 一种垂直整合晶圆的制备方法、制备装置和垂直整合晶圆
JP2025511029A5 (https=)
CN115101657A (zh) 一种单晶压电衬底结构、制备方法及声波器件
JP7791281B2 (ja) 複合基板
FR3141591A1 (fr) Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)
FR3141590A1 (fr) Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)
FR3141592A1 (fr) Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)
JP2025511052A5 (https=)
CN115051675A (zh) 一种用于声波器件的衬底结构及其制备方法
CN121793628A (zh) 复合衬底及其制备方法
JPH07297200A (ja) 半導体シリコンウェハおよびこの製造方法
JPS624378A (ja) 高耐圧ｍｏｓ容量ダイオ−ドの製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20260313

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20260313