KR20240169041A - 절연체상 압전(poi) 기판 및 절연체상 압전(poi) 기판 생성 방법 - Google Patents

절연체상 압전(poi) 기판 및 절연체상 압전(poi) 기판 생성 방법 Download PDF

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Publication number
KR20240169041A
KR20240169041A KR1020247035694A KR20247035694A KR20240169041A KR 20240169041 A KR20240169041 A KR 20240169041A KR 1020247035694 A KR1020247035694 A KR 1020247035694A KR 20247035694 A KR20247035694 A KR 20247035694A KR 20240169041 A KR20240169041 A KR 20240169041A
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KR
South Korea
Prior art keywords
layer
substrate
piezoelectric
trapping
poi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020247035694A
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English (en)
Korean (ko)
Inventor
라파엘 칼미로네
프레데릭 알리베르
이사벨 베르트랑
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소이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 소이텍 filed Critical 소이텍
Publication of KR20240169041A publication Critical patent/KR20240169041A/ko
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/704—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings
    • H10N30/706—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings characterised by the underlying bases, e.g. substrates
    • H10N30/708—Intermediate layers, e.g. barrier, adhesion or growth control buffer layers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02818—Means for compensation or elimination of undesirable effects
    • H03H9/02952—Means for compensation or elimination of undesirable effects of parasitic capacitance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02559—Characteristics of substrate, e.g. cutting angles of lithium niobate or lithium-tantalate substrates
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

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  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
KR1020247035694A 2022-03-30 2023-03-30 절연체상 압전(poi) 기판 및 절연체상 압전(poi) 기판 생성 방법 Pending KR20240169041A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR2202900A FR3134238B1 (fr) 2022-03-30 2022-03-30 Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)
FRFR2202900 2022-03-30
PCT/EP2023/058282 WO2023187050A1 (fr) 2022-03-30 2023-03-30 Substrat piézoélectrique sur isolant (poi) et procédé de fabrication d'un substrat piézoélectrique sur isolant (poi)

Publications (1)

Publication Number Publication Date
KR20240169041A true KR20240169041A (ko) 2024-12-02

Family

ID=82385323

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247035694A Pending KR20240169041A (ko) 2022-03-30 2023-03-30 절연체상 압전(poi) 기판 및 절연체상 압전(poi) 기판 생성 방법

Country Status (8)

Country Link
US (1) US20250211199A1 (https=)
EP (1) EP4500583A1 (https=)
JP (1) JP2025511052A (https=)
KR (1) KR20240169041A (https=)
CN (1) CN119173996A (https=)
FR (1) FR3134238B1 (https=)
TW (1) TW202404134A (https=)
WO (1) WO2023187050A1 (https=)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9768056B2 (en) * 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
FR3053532B1 (fr) * 2016-06-30 2018-11-16 Soitec Structure hybride pour dispositif a ondes acoustiques de surface

Also Published As

Publication number Publication date
US20250211199A1 (en) 2025-06-26
JP2025511052A (ja) 2025-04-15
TW202404134A (zh) 2024-01-16
FR3134238B1 (fr) 2024-08-23
FR3134238A1 (fr) 2023-10-06
WO2023187050A1 (fr) 2023-10-05
CN119173996A (zh) 2024-12-20
EP4500583A1 (fr) 2025-02-05

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Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20241025

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application