JP2025507250A - 複合構造および関連する製造プロセス - Google Patents

複合構造および関連する製造プロセス Download PDF

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Publication number
JP2025507250A
JP2025507250A JP2024541671A JP2024541671A JP2025507250A JP 2025507250 A JP2025507250 A JP 2025507250A JP 2024541671 A JP2024541671 A JP 2024541671A JP 2024541671 A JP2024541671 A JP 2024541671A JP 2025507250 A JP2025507250 A JP 2025507250A
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JP
Japan
Prior art keywords
carbon film
glassy carbon
thin layer
substrate
composite structure
Prior art date
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Pending
Application number
JP2024541671A
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English (en)
Japanese (ja)
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JP2025507250A5 (https=
Inventor
グウェルタズ ゴーダン，
ヒューゴ ビアード，
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of JP2025507250A publication Critical patent/JP2025507250A/ja
Publication of JP2025507250A5 publication Critical patent/JP2025507250A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Inorganic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Carbon And Carbon Compounds (AREA)
  • Recrystallisation Techniques (AREA)
  • Ceramic Products (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Laminated Bodies (AREA)
JP2024541671A 2022-02-18 2023-01-31 複合構造および関連する製造プロセス Pending JP2025507250A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR2201443 2022-02-18
FR2201443A FR3132976B1 (fr) 2022-02-18 2022-02-18 Structure composite et procede de fabrication associe
PCT/EP2023/052346 WO2023156193A1 (fr) 2022-02-18 2023-01-31 Structure composite et procede de fabrication associe

Publications (2)

Publication Number Publication Date
JP2025507250A true JP2025507250A (ja) 2025-03-18
JP2025507250A5 JP2025507250A5 (https=) 2025-12-10

Family

ID=81580657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024541671A Pending JP2025507250A (ja) 2022-02-18 2023-01-31 複合構造および関連する製造プロセス

Country Status (8)

Country Link
US (1) US20250140602A1 (https=)
EP (1) EP4479994A1 (https=)
JP (1) JP2025507250A (https=)
KR (1) KR20240154013A (https=)
CN (1) CN118696397A (https=)
FR (1) FR3132976B1 (https=)
TW (1) TW202349454A (https=)
WO (1) WO2023156193A1 (https=)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6371143B2 (ja) * 2014-07-08 2018-08-08 イビデン株式会社 ＳｉＣウェハの製造方法、ＳｉＣ半導体の製造方法及び黒鉛炭化珪素複合基板
JP6371142B2 (ja) * 2014-07-08 2018-08-08 イビデン株式会社 ＳｉＣウェハの製造方法、ＳｉＣ半導体の製造方法及び炭化珪素複合基板
US20180158672A1 (en) * 2015-06-25 2018-06-07 Tivra Corporation Crystalline Semiconductor Growth on Amorphous and Poly-Crystalline Substrates

Also Published As

Publication number Publication date
CN118696397A (zh) 2024-09-24
FR3132976A1 (fr) 2023-08-25
KR20240154013A (ko) 2024-10-24
TW202349454A (zh) 2023-12-16
FR3132976B1 (fr) 2024-11-29
US20250140602A1 (en) 2025-05-01
WO2023156193A1 (fr) 2023-08-24
EP4479994A1 (fr) 2024-12-25

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