KR20240154013A - 복합 구조체 및 관련 제조 공정 - Google Patents
복합 구조체 및 관련 제조 공정 Download PDFInfo
- Publication number
- KR20240154013A KR20240154013A KR1020247031068A KR20247031068A KR20240154013A KR 20240154013 A KR20240154013 A KR 20240154013A KR 1020247031068 A KR1020247031068 A KR 1020247031068A KR 20247031068 A KR20247031068 A KR 20247031068A KR 20240154013 A KR20240154013 A KR 20240154013A
- Authority
- KR
- South Korea
- Prior art keywords
- composite structure
- carbon film
- glassy carbon
- substrate
- thin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H01L21/02002—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/36—Carbides
-
- H01L21/185—
-
- H01L21/76254—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P10/00—Bonding of wafers, substrates or parts of devices
- H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Chemical & Material Sciences (AREA)
- Organic Chemistry (AREA)
- Engineering & Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Inorganic Chemistry (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Carbon And Carbon Compounds (AREA)
- Recrystallisation Techniques (AREA)
- Ceramic Products (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Laminated Bodies (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FRFR2201443 | 2022-02-18 | ||
| FR2201443A FR3132976B1 (fr) | 2022-02-18 | 2022-02-18 | Structure composite et procede de fabrication associe |
| PCT/EP2023/052346 WO2023156193A1 (fr) | 2022-02-18 | 2023-01-31 | Structure composite et procede de fabrication associe |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20240154013A true KR20240154013A (ko) | 2024-10-24 |
Family
ID=81580657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020247031068A Pending KR20240154013A (ko) | 2022-02-18 | 2023-01-31 | 복합 구조체 및 관련 제조 공정 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US20250140602A1 (https=) |
| EP (1) | EP4479994A1 (https=) |
| JP (1) | JP2025507250A (https=) |
| KR (1) | KR20240154013A (https=) |
| CN (1) | CN118696397A (https=) |
| FR (1) | FR3132976B1 (https=) |
| TW (1) | TW202349454A (https=) |
| WO (1) | WO2023156193A1 (https=) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6371143B2 (ja) * | 2014-07-08 | 2018-08-08 | イビデン株式会社 | SiCウェハの製造方法、SiC半導体の製造方法及び黒鉛炭化珪素複合基板 |
| JP6371142B2 (ja) * | 2014-07-08 | 2018-08-08 | イビデン株式会社 | SiCウェハの製造方法、SiC半導体の製造方法及び炭化珪素複合基板 |
| US20180158672A1 (en) * | 2015-06-25 | 2018-06-07 | Tivra Corporation | Crystalline Semiconductor Growth on Amorphous and Poly-Crystalline Substrates |
-
2022
- 2022-02-18 FR FR2201443A patent/FR3132976B1/fr active Active
-
2023
- 2023-01-31 US US18/837,681 patent/US20250140602A1/en active Pending
- 2023-01-31 WO PCT/EP2023/052346 patent/WO2023156193A1/fr not_active Ceased
- 2023-01-31 JP JP2024541671A patent/JP2025507250A/ja active Pending
- 2023-01-31 EP EP23702162.1A patent/EP4479994A1/fr active Pending
- 2023-01-31 CN CN202380021538.8A patent/CN118696397A/zh active Pending
- 2023-01-31 KR KR1020247031068A patent/KR20240154013A/ko active Pending
- 2023-02-07 TW TW112104269A patent/TW202349454A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| CN118696397A (zh) | 2024-09-24 |
| FR3132976A1 (fr) | 2023-08-25 |
| TW202349454A (zh) | 2023-12-16 |
| FR3132976B1 (fr) | 2024-11-29 |
| JP2025507250A (ja) | 2025-03-18 |
| US20250140602A1 (en) | 2025-05-01 |
| WO2023156193A1 (fr) | 2023-08-24 |
| EP4479994A1 (fr) | 2024-12-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI861252B (zh) | 用於製作複合結構之方法,該複合結構包含一單晶SiC薄層在一結晶SiC載體底材上 | |
| JP7542053B2 (ja) | 多結晶炭化ケイ素で作られたキャリア基板上に単結晶炭化ケイ素の薄層を含む複合構造を製造するためのプロセス | |
| US20070141803A1 (en) | Methods for making substrates and substrates formed therefrom | |
| CN115088063B (zh) | 用于制造包括位于由SiC制成的载体衬底上的由单晶SiC制成的薄层的复合结构的方法 | |
| JP7620646B2 (ja) | 非常に高い温度に対応する剥離可能な仮基板、及び前記基板から加工層を移動させるプロセス | |
| CN115023802A (zh) | 包含在SiC制载体衬底上的单晶SiC制薄层的复合结构的制造方法 | |
| US20240379351A1 (en) | Method for fabricating a polycrystalline silicon carbide carrier substrate | |
| CN114730699A (zh) | 制造包括位于由SiC制成的载体基板上的单晶SiC薄层的复合结构的方法 | |
| TWI907572B (zh) | 製作含凝聚物之交界區之半導體結構之方法 | |
| EP4085478B1 (fr) | Procede de fabrication d'une structure composite comprenant une couche mince monocristalline sur un substrat support | |
| KR20240154013A (ko) | 복합 구조체 및 관련 제조 공정 | |
| US20240395603A1 (en) | Composite structure comprising a useful monocrystalline sic layer on a polycrystalline sic carrier substrate and method for manufacturing said structure | |
| WO2025186046A1 (fr) | Procédé de préparation d'un substrat support en matériau polycristallin et procédé de fabrication d'une structure composite incluant ledit substrat support | |
| WO2025186045A1 (fr) | Procédé de préparation d'un substrat support en matériau polycristallin et procédé de fabrication d'une structure composite incluant ledit substrat support | |
| CN118302839A (zh) | 制造包括具有改进的电性能的由碳化硅制成的工作层的半导体结构体的方法 | |
| JP2024537777A (ja) | 多結晶SiCでできた担体基板上に単結晶SiCでできた薄層を含む複合構造を製作するための方法 | |
| TW202301554A (zh) | 用於製作碳化矽基半導體結構及中間複合結構之方法 | |
| FR3151939A1 (fr) | Procédé de fabrication d’une couche contrainte | |
| CN118077032A (zh) | 用于在多晶SiC的载体衬底上制造包含单晶SiC的薄膜的复合结构体的方法 | |
| FR3165753A1 (fr) | Procédé de fabrication d’une structure composite incluant une couche mince monocristalline transférée sur un substrat support |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |
|
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |