JP2025507015A - 多結晶半導体のエッチング - Google Patents

多結晶半導体のエッチング Download PDF

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Publication number
JP2025507015A
JP2025507015A JP2024552402A JP2024552402A JP2025507015A JP 2025507015 A JP2025507015 A JP 2025507015A JP 2024552402 A JP2024552402 A JP 2024552402A JP 2024552402 A JP2024552402 A JP 2024552402A JP 2025507015 A JP2025507015 A JP 2025507015A
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JP
Japan
Prior art keywords
plasma
substrate
layer
recess
exposing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024552402A
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English (en)
Japanese (ja)
Other versions
JP2025507015A5 (enExample
Inventor
ハン，ユン
ランジャン，アロック
智之 大石
秀平 小川
憲 小林
ビオルシ，ピーター
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron US Holdings Inc
Original Assignee
Tokyo Electron US Holdings Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron US Holdings Inc filed Critical Tokyo Electron US Holdings Inc
Publication of JP2025507015A publication Critical patent/JP2025507015A/ja
Publication of JP2025507015A5 publication Critical patent/JP2025507015A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
    • H01J37/32899—Multiple chambers, e.g. cluster tools
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
JP2024552402A 2022-03-09 2023-03-07 多結晶半導体のエッチング Pending JP2025507015A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/690,715 2022-03-09
US17/690,715 US12300500B2 (en) 2022-03-09 2022-03-09 Etching of polycrystalline semiconductors
PCT/US2023/014748 WO2023172584A1 (en) 2022-03-09 2023-03-07 Etching of polycrystalline semiconductors

Publications (2)

Publication Number Publication Date
JP2025507015A true JP2025507015A (ja) 2025-03-13
JP2025507015A5 JP2025507015A5 (enExample) 2026-03-11

Family

ID=87935870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024552402A Pending JP2025507015A (ja) 2022-03-09 2023-03-07 多結晶半導体のエッチング

Country Status (5)

Country Link
US (1) US12300500B2 (enExample)
JP (1) JP2025507015A (enExample)
KR (1) KR20240159879A (enExample)
TW (1) TW202349493A (enExample)
WO (1) WO2023172584A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12288812B2 (en) * 2022-06-02 2025-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of fabrication thereof
US12424442B2 (en) * 2022-12-28 2025-09-23 Tokyo Electron Limited Methods for forming semiconductor devices using modified photomask layer

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100618850B1 (ko) 2004-07-22 2006-09-01 삼성전자주식회사 반도체 소자 제조용 마스크 패턴 및 그 형성 방법과 미세패턴을 가지는 반도체 소자의 제조 방법
US20080286978A1 (en) * 2007-05-17 2008-11-20 Rong Chen Etching and passivating for high aspect ratio features
US8916477B2 (en) 2012-07-02 2014-12-23 Novellus Systems, Inc. Polysilicon etch with high selectivity
US9318343B2 (en) 2014-06-11 2016-04-19 Tokyo Electron Limited Method to improve etch selectivity during silicon nitride spacer etch
US9679780B1 (en) 2016-09-28 2017-06-13 International Business Machines Corporation Polysilicon residue removal in nanosheet MOSFETs
US10896816B2 (en) 2017-09-26 2021-01-19 International Business Machines Corporation Silicon residue removal in nanosheet transistors
US10658491B2 (en) 2018-06-15 2020-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling profiles of replacement gates
JP7071884B2 (ja) * 2018-06-15 2022-05-19 東京エレクトロン株式会社 エッチング方法及びプラズマ処理装置
US11120997B2 (en) * 2018-08-31 2021-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Surface treatment for etch tuning
US11935758B2 (en) 2019-04-29 2024-03-19 Lam Research Corporation Atomic layer etching for subtractive metal etch
US11355350B2 (en) 2019-12-20 2022-06-07 Tokyo Electron Limited Etching method, substrate processing apparatus, and substrate processing system
US11302581B2 (en) 2020-05-05 2022-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Gate profile control through sidewall protection during etching

Also Published As

Publication number Publication date
TW202349493A (zh) 2023-12-16
US20230317462A1 (en) 2023-10-05
US12300500B2 (en) 2025-05-13
KR20240159879A (ko) 2024-11-07
WO2023172584A1 (en) 2023-09-14

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