Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
  • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
  • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
  • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
  • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
  • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32431—Constructional details of the reactor
  • H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
  • H01J37/32899—Multiple chambers, e.g. cluster tools
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials

Definitions

• the present invention relates generally to a method of processing a substrate, and, in particular embodiments, to etching of polycrystalline semiconductors.
• a semiconductor device such as an integrated circuit (IC) is fabricated by sequentially depositing and patterning layers of dielectric, conductive, and semiconductor materials over a substrate to form a network of electronic components and interconnect elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias) integrated in a monolithic structure.
• IC integrated circuit
• interconnect elements e.g., transistors, resistors, capacitors, metal lines, contacts, and vias
• the semiconductor industry increasingly demands plasma-processing technology to provide processes for patterning features with accuracy, precision, and profile control, often at atomic scale dimensions.
• These requirements are particularly stringent for three-dimensional (3D) structures, for example, a fin field-effect transistor (FinFET) wherein the gate electrode wraps around three sides of closely-spaced, narrow and long fin- shaped semiconductor features formed by etching trenches into the semiconductor substrate.
• FinFET fin field-effect transistor
• a method of processing a substrate that includes: performing a cyclic plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching a patterning layer including a polycrystalline semiconductor material to form or extend a recess by exposing the substrate to a first plasma, the substrate including an oxide layer, the patterning layer formed over the oxide layer, exposing the substrate to a second plasma, the second plasma
• a method of processing a substrate that includes: performing a cyclic plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching a polysilicon layer to form a recess by exposing the substrate to a first plasma for a first duration, the substrate including an oxide layer, the polysilicon layer formed over the oxide layer, the first plasma including hydrogen bromide and dichlorine, and exposing the substrate to a second plasma for a second duration, the second plasma including dihydrogen.
• a method of fabricating a fin field-effect transistor that includes: forming a fin feature over an oxide layer, the oxide layer formed over the substrate, the fin feature including a fin hard mask and a fin under the fin hard mask, the fin including silicon; depositing a dummy gate material including polysilicon; depositing a gate hard mask layer over the dummy gate material; depositing a photoresist over the hard mask layer; performing a photolithographic process to pattern the photoresist; etching the gate hard mask layer to transfer a pattern from the photoresist to the hard mask layer; and performing a cyclic plasma etch process using the gate hard mask layer as an etch mask, the cyclic plasma etch process exposing the fin hard mask, the cyclic plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching the dummy gate material to form a recess by exposing the substrate to a first plasma, the first plasma including a
• Figures 1A-1G illustrate cross sectional views of an example substrate during an example cyclic plasma process at various stages in accordance with various embodiments, wherein Figure 1A illustrates an incoming substrate comprising polysilicon, a hard mask layer, and a patterned photoresist layer, Figure 1B illustrates the substrate after a hard mask open step, Figure 1C illustrates the substrate after a first main etch with a first plasma of the cyclic plasma process, Figure 1D illustrates the substrate after a first hydrogen treatment of the cyclic plasma process with a second plasma, Figure 1E illustrates the substrate after cycles of steps of the cyclic plasma process, Figure 1F illustrates the substrate after a surface treatment to form a protective surface layer, and Figure 1G illustrates the substrate after a soft-landing etch with a third plasma;
• Figures 2A-2E illustrate perspective views of an example substrate during an example cyclic plasma process for fabricating a three-dimensional (3D) semiconductor device at various stages in accordance with various embodiments, wherein Figure 2A illustrates an incoming substrate comprising an oxide layer, a fin feature, a polysilicon layer, a hard mask layer, and a patterned photoresist layer, Figure 2B illustrates the substrate after a hard mask open step, Figure 2C illustrates the substrate after cycles of steps of the cyclic plasma process, Figure 2D illustrates the substrate after a surface treatment to form a protective surface layer, and Figure 2E illustrates the substrate after a soft-landing etch forming a dummy gate feature wrapping the fin feature; and
• Figures 3A-3C illustrate process flow charts of methods of cyclic plasma process in accordance with various embodiments, wherein Figure 3A illustrates some embodiment process flows, Figure 3B illustrates alternate embodiment process flows, and Figure 3C illustrates yet other embodiment process flows.
• This application relates to a method of processing a substrate, more particularly to a method of cyclic plasma process that enables etch profile control in features with high aspect ratio (HAR).
• poor etch profile control in HAR features may result in variations in critical dimension (CD) across the HAR features and poor line edge roughness (LER).
• CD critical dimension
• LER line edge roughness
• This issue may be particularly challenging during a plasma etch of polysilicon used in front-end-of-line (FEOL) fabrication of advanced logic nodes.
• FEOL front-end-of-line
• Different silicon crystalline orientation and grain boundaries of polysilicon tend to lead to variation in lateral etch rate, which can cause poor sidewall profile with surface roughness. Therefore, a plasma etch technique for polysilicon in HAR features with better etch profile control may be desired.
• Embodiments of the present application disclose methods of cyclic plasma process comprising a main plasma etch step and a hydrogen plasma treatment step for sidewall smoothening.
• the cyclic plasma process may further comprise a soft-landing etch to be performed after the last main plasma etch step.
• the methods described in this disclosure may advantageously reduce the LER of HAR features formed in a layer comprising polysilicon. This maybe particularly useful to fabricate a polysilicon gate or dummy gate in a 3D semiconductor device such as a fin fieldeffect transistor (FinFET). Further, the methods herein may improve the critical dimension (CD) control in the HAR features by providing a uniform, controlled lateral etch rate on the sidewalls.
• CD critical dimension
• features with aspect ratio (ratio of height of the feature to the width of the feature) equal to or higher than 10:1 may be enabled by the cyclic plasma process.
• a cyclic plasma process comprising a main plasma etch step and a hydrogen plasma treatment step for sidewall smoothening are first described referring to Figures 1A-1G in accordance with various embodiments.
• Some embodiments of the cyclic plasma process applied for a gate etch during fabricating a fin field-effect transistor (FinFET) are next described referring to Figures 2A-2E.
• Example process flow diagrams are illustrated in Figure 3A-3C. All figures in this disclosure are drawn for illustration purpose only and not to scale, including the aspect ratios of features.
• Figure 1A illustrates a cross sectional view of an incoming substrate too comprising a polysilicon layer 120.
• the substrate too comprises a semiconductor substrate in various embodiments.
• the substrate too maybe a silicon wafer, or a silicon-on-insulator (SOI) wafer.
• the substrate too may comprise a silicon germanium wafer, silicon carbide wafer, gallium arsenide wafer, gallium nitride wafer and other compound semiconductors.
• the substrate too comprises heterogeneous layers such as silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, as well layers of silicon on a silicon or SOI substrate.
• the substrate too may have undergone a number of steps of processing following, for example, a conventional process to fabricate a semiconductor structure. Accordingly, various device regions may have been formed in the substrate too. At this stage, for example, the substrate too may include isolation regions such as shallow trench isolation (STI) regions as well as other regions formed therein.
• STI shallow trench isolation
• the substrate too may further comprise an insulating layer 110.
• the insulating layer 110 may comprise an oxide such as silicon oxide.
• the insulating layer 110 may be formed by thermal oxidation.
• the insulating layer 110 is a layer to be fabricated as an insulating region, such as a buried oxide (BOX) layer in a semiconductor device.
• the insulating layer 110 may have a thickness between about 10 nm to about 1 pm.
• a polysilicon layer 120 is formed over the insulating layer 110.
• the polysilicon layer 120 illustrated in Figure 1A is the layer to be patterned by the embodiment methods for forming high aspect ratio (HAR) features.
• HAR high aspect ratio
• the aspect ratio (width to height) of the HAR features maybe more than 1:5 or more, for example, 1:10 or more in some embodiments.
• the polysilicon layer 120 is to be patterned to form a gate or a dummy gate for a semiconductor device.
• the polysilicon used in the polysilicon layer 120 may comprise a doped polysilicon to have desired material properties including electrical properties.
• the polysilicon layer 120 may be deposited over the insulating layer 110 using appropriate deposition techniques such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), as well as other plasma processes such as plasma enhanced CVD (PECVD), sputtering, and other processes.
• the polysilicon layer 120 may have a thickness of about 50 nm to about 500 nm. Since polysilicon is polycrystalline form of silicon, it comprises many crystallites 125 and grain boundaries between individual crystallites as illustrated in Figure 1A.
• a hard mask layer 130 may be formed over the polysilicon layer 120.
• the hard mask layer 130 may comprise silicon oxide in one embodiment.
• the hard mask layer 130 may comprise silicon nitride, silicon carbonitride (SiCN), or silicon oxycarbide (SiOC).
• the hard mask layer 130 may comprise titanium nitride.
• the hard mask layer 130 may comprise other suitable organic materials such as spin-on carbon hard mask (SOH) materials.
• the hard mask layer 130 may be a stacked hard mask comprising, for example, two or more layers using two different materials.
• the first hard mask of the hard mask layer 130 may comprise a metal-based layer such as titanium nitride, titanium, tantalum nitride, tantalum, tungsten based compounds, ruthenium based compounds, or aluminum based compounds
• the second hard mask material of the hard mask layer 130 may comprise a dielectric layer such as silicon oxide, silicon nitride, SiCN, SiOC, silicon oxynitride, or silicon carbide.
• the hard mask layer 130 maybe deposited using suitable deposition techniques such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), as well as other plasma processes such as plasma enhanced CVD (PECVD), sputtering, and other processes including wet processes.
• CVD chemical vapor deposition
• PVD physical vapor deposition
• PECVD plasma enhanced CVD
• sputtering and other processes including wet processes.
• the hard mask layer 130 may have a thickness of about 5 nm to about 50 nm in various embodiments.
• an additional layer such as silicon-containing anti-reflective coating films (SiARC) or other ARC films may be formed over the hard mask layer 130.
• a patterned photoresist layer 140 may be formed over the hard mask layer 130.
• the patterned photoresist layer 140 provides a pattern to form respective features in the polysilicon layer 120.
• the patterned photoresist layer 140 serves as a first etch mask when forming respective features in the hard mask layer 130 ( Figure 1B), and subsequently the formed features in the hard mask layer 130 may serve as a second etch mask during a cyclic plasma process to etch the polysilicon such that the features of the patterned photoresist layer 140 will be transferred to the polysilicon layer 120, as described below.
• the patterned photoresist layer 140 may comprise 248 nm resists, 193 nm resists, 157 nm resists, EUV (extreme ultraviolet) resists, or electron beam (EB) sensitive resists.
• a photoresist may be deposited over the hard mask layer 130 using a dry process or wet process, for example, a spin-coating technique. The deposited photoresist maybe then patterned with an appropriate lithographic process to form the patterned photoresist layer 140. In one embodiment, the patterned photoresist layer 140 has a thickness between 20 nm and too nm.
• CD critical dimension
• the CD may be between 10 nm and too nm. In one or more embodiments, the CD may be between 10 nm and 40 nm.
• Figure 1B illustrates a cross sectional view of semiconductor structure during fabrication after a hard mask open step in accordance with an embodiment.
• the hard mask open step may be performed using a plasma etch process, for example a reactive ion etching (RIE) process, to form recesses 150 in the hard mask layer 130.
• RIE reactive ion etching
• the section of the hard mask layer 130 that is not masked by the patterned photoresist layer 140 may be removed, thereby transferring the pattern defined by the patterned photoresist layer 140 to the hard mask layer 130.
• at least a portion of the polysilicon layer 120 may be exposed at the bottom of the recesses 150 after the hard mask open step.
• the substrate too may comprise additional layers above and/or below the hard mask layer 130, and the additional layers may also be removed during the hard mask open step.
• the remaining portion of the patterned photoresist layer 140 may be removed prior to performing subsequent steps. In one or more embodiments, some of the patterned photoresist layer 140 may remain during subsequent steps as illustrated in Figures 1B-1G, but maybe removed at any stage in other embodiments.
• Figure 1C illustrates a cross sectional view of semiconductor structure during fabrication after a first main etch with a first plasma of the cyclic plasma process.
• the cyclic plasma process may be applied to etch polysilicon with controlled etch profile and sidewalls.
• a cycle of the cyclic plasma process in accordance with various embodiments may start with the main etch by exposing the substrate too to a first plasma.
• the main etch may be anisotropic to extend the recesses 150 into the polysilicon layer 120.
• the cyclic etch process maybe performed in a suitable plasma processing chamber equipped with one or more plasma sources such as inductively coupled plasma (ICP), capacitively couple plasma (CCP), microwave plasma (MW), or others.
• the main etch maybe a reactive ion etching (RIE) process, and may use a first etch gas, for example, comprising a halogen gas.
• RIE reactive ion etching
• the first etch gas may hydrogen bromide (HBr) and dichlorine (Cl 2 ).
• the first etch gas may also comprise additive gases such as dioxygen (0 2 ) and/or noble gas (e.g., He, Ne, Ar, Kr, etc.).
• the first etch gas maybe selected so that the first plasma to etch polysilicon has high selectivity and high polysilicon etch rate.
• the selectivity may be with respect to the mask material of the hard mask layer 130, for example silicon oxide, silicon nitride, or SiON.
• plasma conditions for the main etch may be determined to obtain desired selectivity and etch rate.
• the main etch may be performed at a total gas flow between 50 seem and 1000 seem, a pressure between 5 mTorr and 300 mTorr, a temperature between -io°C and 15O°C, and an operating frequency between 100 kHz and 10 GHz.
• the flow rate of HBr is maintained in the range from about o seem to 500 seem and the Cl 2 flow rate is between about o seem and 100 seem.
• the total flow rate of the additive gases may be in the range from about 50 seem to 500 seem.
• the main etch may be performed with a process time between 5 s and 120 s, for example, 10 s to 30 s in one embodiment.
• the main etch may primarily be an anisotropic etch with vertical directionality to extend the recesses 150 vertically, some lateral etch on the sidewalls of the recesses 150 may occur.
• the effect of lateral etch may especially be critical in CD control of narrow recesses and HAR features, where most of the surfaces of a patterning layer are its sidewalls.
• the lateral etch may lead to CD loss and line edge roughness (LER), which may severely hamper device performance and yield. These issues of undesired lateral etch may be worse in etching of polysilicon.
• the sidewalls of the recesses 150 comprise different grains, and different crystal planes are exposed on surface. Because the etch rate of silicon depends on the type of crystal plane, the rate of the lateral etch during the main etch may vary across the sidewalls from the top to the bottom. As a result, the surfaces of the sidewalls may not be smooth and with poor LER.
• the inventors of this disclosure identified that implementing a subsequent exposure to a second plasma comprising hydrogen (e.g., H 2 ) in the cyclic plasma process, referred to as a hydrogen treatment below, can alleviate this issue by smoothening the sidewall surfaces as further described below.
• the depth of the recesses 150 may be less than the total thickness of the three layers (i.e. , the polysilicon layer 120, the hard mask layer 130, and the patterned photoresist layer 140). In other words, the recesses 150 do not reach to the bottom of the polysilicon layer 120.
• the recesses 150 are extended stepwise by repeating the main etch of the cyclic plasma process to form a high aspect ratio (HAR) feature of the polysilicon layer 120.
• HAR high aspect ratio
• stepwise removal of the polysilicon by the cyclic plasma process advantageously enables performing sidewall smoothing multiple times between steps of the cyclic plasma process.
• Figure 1D illustrates a cross sectional view of semiconductor structure during fabrication after a first hydrogen treatment of the cyclic plasma process with a second plasma.
• a hydrogen treatment may be performed by exposing the substrate to the second plasma comprising hydrogen.
• the second plasma comprises molecular hydrogen i.e., dihydrogen (H 2 ).
• the hydrogen treatment smoothens the surfaces of the sidewalls as illustrated in Figure 1D.
• H-containing radical species in the second plasma may induce amorphization of a portion of polysilicon on the surface and etching of silicon atoms, which may lead to smoothening. This is illustrated in Figure 1D as a surface modified silicon layer 160 formed on the surfaces of the recesses 150.
• the CD variation for example, 3 sigma (standard deviation from a mean of CDs measured at different gate heights or depths of the recesses 150 being formed), may be reduced by 20% or more from before the hydrogen treatment.
• the CD standard deviation- may be below 1.0 nm after the hydrogen treatment.
• the surface roughness maybe represented by other indices such as root mean square of height variation (RMS), roughness average (R a ) and peak-to-valley height (h).
• RMS root mean square of height variation
• R a roughness average
• h peak-to-valley height
• the hydrogen treatment may advantageously improve the etch uniformity of a next cycle in the cyclic plasma process because the sidewalls may be covered with amorphous silicon and no longer has different crystal planes exposed on surface.
• the hydrogen treatment may further comprise flowing an optional admixture of inert gas (e.g., He, Ne, Ar, Kr etc.) into the plasma processing chamber.
• inert gas e.g., He, Ne, Ar, Kr etc.
• the exposure to the second plasma may be performed at a total gas flow between 50 seem and 500 seem, a pressure between 5 mTorr and 300 Torr, a temperature between -io°C and 200°C, and an operating frequency between too kHz and 10 GHz.
• the exposure to the second plasma may be performed with a process time between 2 s and 50 s, for example, 5 s to 10 s in one embodiment.
• process parameters such as flow rate, pressure may be selected to provide sufficient modification of the sidewall surfaces, while keeping process time as short as possible for better process efficiency.
• process parameters for the hydrogen plasma step may be optimized with respect to the previous steps of the cyclic plasma process (e.g., Figure 1C).
• ICP inductively coupled plasma
• MW microwave plasma
• CCP capacitively coupled plasma
• a process condition with chamber pressure of 30-80 mTorr, source power of 250-1000 W, and H 2 flow of 100-200 seem may be used.
• steps of the main etch and the hydrogen treatment may be repeated in the cyclic plasma process to reach the desired depth for the recesses 150.
• a second main etch may be performed after the first hydrogen treatment (e.g., Figure 1D) to extend the recesses 150 vertically.
• the sidewall surfaces may be smoothened and amorphized by the first hydrogen treatment, the second main etch may proceed with better etch profile control compared with the first main etch.
• the process conditions of the second main etch may be the same as the first main etch in some embodiments, but may be different in other embodiments.
• a second hydrogen treatment maybe performed to treat and smoothen the newly exposed sidewall and bottom surfaces of the recesses 150, replenishing the surface modified silicon layer 160.
• the process conditions of the second hydrogen treatment may be the same as the first hydrogen treatment in some embodiments, but maybe different in other embodiments.
• one or more step of the main etch or the hydrogen treatment may be skipped or replaced with a different intervening process step according to a process recipe.
• Figure 1E illustrates the substrate 100 after cycles of steps of the cyclic plasma process.
• the recess 150 vertically extends in the polysilicon layer 120 after the cycles of steps.
• the surface modified silicon layer 160 may also be extended after the final hydrogen treatment.
• the recess 150 may extend stepwise and conformally without much variation in critical dimension (CD) from the recess top to bottom.
• CD critical dimension
• any number of cycles may be performed until a desired level of etching may be achieved.
• the cycles may end with the main etch and the final hydrogen treatment may be skipped. Whether the final hydrogen treatment is needed or not may depend on the final etch profile which is largely determined by the polycrystalline condition of the surface modified silicon layer 160 at the film depth.
• the bottom of the recess 150 may still be above the insulating layer 110 as illustrated in Figure 1E, and subsequent steps comprising a soft -landing etch may further extend the recess 150 as below.
• Figure 1F illustrates a cross sectional view of semiconductor structure during fabrication after a surface treatment to form a protective surface layer 170.
• the surface treatment maybe performed to form the protective surface layer 170.
• the protective surface layer 170 is to provide sidewall protection during the subsequent soft -landing etch.
• the surface treatment comprises exposing the substrate to a reactive gas that induces a surface reaction with the silicon atoms on the sidewall.
• the reactive gas comprising oxygen (e.g., 0 2 , CO or C0 2 ) and a thin layer comprising an oxide (e.g., silicon oxide) maybe formed as the protective surface layer 170.
• the reactive gas may comprise nitrogen (e.g., N 2 , NH 3 , etc.) and the protective surface layer 170 may comprise a nitride (e.g., silicon nitride).
• the surface treatment is a plasma process. It is also possible, in the surface treatment, to deposit a new material for the protective surface layer 170 over silicon.
• various deposition techniques maybe used, such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), as well as other plasma processes such as plasma enhanced CVD (PECVD) and other processes.
• a process condition with chamber pressure of 80-120 mTorr, source power of 100-300 W and 0-50 W bias power, and 0 2 flow of 100- 200 seem with Ar flow of 200-500 seem is used.
• Figure 1G illustrates a cross sectional view of semiconductor structure during fabrication after a soft-landing etch with a third plasma.
• the cyclic plasma process may further comprise another etch process, referred to as the soft -landing etch in this disclosure, with different process conditions from the main etch.
• the purpose of the soft-landing etch is to further remove polysilicon to fabricate the target high aspect ratio (HAR) features in the polysilicon layer 120 while preventing any damage to other components or feature on the substrate 100.
• the soft-landing etch may have higher etch selectivity (e.g., polysilicon-to-oxide selectivity) than the main etch so that the insulating layer 110 and other possible features (e.g., a fin feature as illustrated below in Figures 2A-2E) are not impacted.
• the soft -landing etch further extends the recesses 150 and may expose the insulating layer no in various embodiments.
• the soft -landing etch maybe a reactive ion etching (RIE) process, and may use a second etch gas, for example, comprising a halogen gas.
• the second etch gas may hydrogen bromide (HBr) and dichlorine (Cl 2 ).
• the second etch gas may also comprise additive gases such as dioxygen (0 2 ) and/or noble gas (e.g., He, Ne, Ar, Kr, etc.).
• the composition of the second etch gas for the soft-landing etch may be the same as the first etch gas for the main etch, but in other embodiments may be different.
• the second etch gas may be selected so that the third plasma to etch polysilicon during the soft -landing etch has selectivity higher than that of the first plasma during the main etch.
• the selectivity may be with respect to the mask material of the hard mask layer 130, the insulating layer 110, the fin structure or other features.
• plasma conditions for the soft-landing etch may be determined to obtain desired selectivity. For this reason, in one embodiment, the etch rate of the soft -landing etch maybe less than the etch rate of the main etch.
• the process time of the soft- landing etch may be longer than that of the main etch.
• the amount of polysilicon to be etched by the sof -landing etch is less than the amount of polysilicon to be etched by the cycles of the main etch.
• the soft-landing etch may be performed at a total gas flow between too seem and 1000 seem, a pressure between 10m Torr and 800 mTorr, a temperature between -io°C and 200°C, and an operating frequency between too kHz and 10 GHz.
• the flow rate of HBr is maintained in the range from about too seem to 500 seem and the Cl 2 flow rate is between about o seem and 300 seem.
• the total flow rate of the additive gases may be in the range from about o seem to 200 seem.
• the main etch may be performed with a process time between 2 s and 120 s, for example, 10 s to 50 s in one embodiment.
• the process may be performed at a condition with higher chamber pressure, lower bias power, higher additive flow rates (e.g., 0 2 , C0 2 , or N 2 ) for more surface deposition, compared to the main etch process conditions.
• higher additive flow rates e.g., 0 2 , C0 2 , or N 2
• Figures 2A-2E illustrate perspective views of an example substrate during an example cyclic plasma process for fabricating a three-dimensional (3D) semiconductor device at various stages in accordance with various embodiments.
• the cyclic plasma process in accordance with various embodiments in this disclosure may be applied and particularly useful in fabricating a 3D semiconductor device.
• Figures 2A-2E illustrate an example for a fin field-effect transistor (FinFET), although other 3D semiconductor device may be fabricated utilizing the method of etching polysilicon described in this disclosure. Process details may be the same as already described above and may not be repeated.
• FinFET fin field-effect transistor
• the substrate too comprises the same features as illustrated above in Figure 1A, including an insulating layer 110, a polysilicon layer 120, a hard mask layer 130, and a patterned photoresist layer 140. Further, the substrate too in Figure 2A comprises a fin feature having fins 200 comprising a semiconductor material and fin hard mask 210 formed over the fins 200. It should be noted that while two fins 200 are depicted in Figure 2A for illustration purpose, the number of fins is not limited. In various embodiments, the fins 200, at the end of fabrication, may form the transistor channels in a FinFET device.
• the fins 200 may have a height between about 20 nm to about too nm and a width between about 5 nm to about 30 nm. While the fabrication of a SOI FinFET is illustrates in Figures 2A-2E, the cyclic plasma process is applicable to the fabrication of a bulk FinFET, where the fins 200 will be tied with and connected to the substrate too directly.
• the fins 200 comprise silicon, silicon germanium, or other semiconductor materials.
• An n-type field effect transistor or a p-type field effect transistor may be formed with different types of materials being used for the fins 200 in some embodiments.
• n-FETs may be fabricated with using materials for the fins 200 having high electron mobility while p-FETs maybe fabricated with using materials for the fins 200 having high hole mobility.
• the fins 200 maybe selected to be a material selected from Groups III-V of the periodic table.
• the fin feature may be formed by a conventional method, for example, by depositing a layer of material for the fins 200, depositing the fin hard mask 210, patterning the fin hard mask to define the pattern for the fins 200, and etching the material for the fins 200 using the patterned fin hard mask as an etch mask.
• the deposition of the layer of material for the fins 200 may be formed by deposition processes, for example, epitaxially by a chemical vapor deposition (CVD) method.
• CVD chemical vapor deposition
• the fin hard mask 210 may comprise silicon oxide in one embodiment.
• the fin hard mask 210 may comprise silicon nitride, silicon carbonitride (SiCN), or silicon oxycarbide (SiOC).
• the fin hard mask 210 maybe deposited using suitable deposition techniques such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), as well as other plasma processes such as plasma enhanced CVD (PECVD), sputtering, and other processes.
• the fin hard mask 210 maybe then patterned, for example, by a lithographic process and an etch process. In certain embodiments, the fin hard mask 210 may be removed prior to forming the polysilicon layer 120.
• the fin feature may then be buried in the polysilicon layer 120 after depositing the polysilicon layer 120.
• the polysilicon layer 120 may be used to form a dummy gate in one embodiment.
• the deposition of the polysilicon layer 120 and subsequent steps of depositing the hard mask layer 130 and forming the patterned photoresist maybe performed as previously described referring to Figure 1A.
• Figure 2B illustrates a perspective view of semiconductor structure during fabrication after a hard mask open step.
• the hard mask open step may be performed using a plasma etch process, for example a reactive ion etching (RIE) process as previously described referring to Figure 1B.
• RIE reactive ion etching
• the pattern of the patterned photoresist layer 140 maybe transferred to the hard mask layer 130.
• the remaining portion of the patterned photoresist layer 140 maybe removed after the hard mask open step, for example by ashing.
• Figure 2C illustrates a perspective view of semiconductor structure during fabrication after cycles of steps of the cyclic plasma process.
• cycles of the main etch and the hydrogen treatment may be performed to etch the polysilicon layer 120 with the patterned hard mask layer 130 as an etch mask.
• the high aspect ratio (HAR) features comprising a plurality of lines and recesses are assumed in various embodiments.
• the cycles of the cyclic plasma process may end with the final hydrogen treatment, and therefore a surface modified silicon layer 160 may cover the surface of the polysilicon layer that was exposed by the main etch.
• the final hydrogen treatment may be skipped and the sidewalls of the polysilicon layer 120 maybe exposed.
• the cycles maybe stopped when the top surfaces of the fin feature (e.g., top surfaces of the fin hard mask 210 in
• Figure 2C are first exposed so that further removal of polysilicon in the polysilicon layer 120 may separately be performed by a more selective etch, for example a soft-landing etch as described below.
• Figure 2D illustrates a perspective view of semiconductor structure during fabrication after a surface treatment to form a protective surface layer 170.
• the surface treatment to form the protective surface layer 170 maybe performed as previously described referring to Figure 1F.
• the protective surface layer 170 may cover or replace the surface of the surface modified silicon layer 160 and any exposed portion of the polysilicon layer 120.
• Figure 2E illustrates a perspective view of semiconductor structure during fabrication after a soft-landing etch forming a dummy gate feature wrapping the fin feature.
• the soft-landing etch may be next performed to further etch polysilicon with selectivity higher than that of the main etch.
• Process conditions of the soft -landing etch for polysilicon may be selected so as to minimize or eliminate damages to other components such as the insulating layer 110 and the fins 200, and the fin hard mask 210.
• subsequent process steps for fabricating a semiconductor device such as FinFET may follow.
• steps may be including but not limited to gate spacer formation, gate implantation, fin recess and source/drain formation, channel release, and middle-of-line (MOL)/back-end-of-line (BEOL) processes.
• FIGS 3A-3C illustrate process flow charts of methods of cyclic plasma process in accordance with various embodiments. The process flow can be followed with the figures discussed above and hence will not be described again.
• a process flow 30 starts with a cyclic plasma process 310 comprising, as a main etch, etching a patterning layer comprising polysilicon to form a recess by exposing the substrate to a first plasma (block 320, Figure 1C).
• a hydrogen treatment the substrate maybe exposed to a second plasma comprising dihydrogen (H 2 ) (block 330, Figure 1D).
• the main etch and the hydrogen treatment may be repeated for any number of times to extend the recess (e.g., Figure 1E).
• the substrate maybe then exposed to a third plasma, for a soft-landing etch, to further extend the recess (block 340, Figure 1G).
• an optional surface treatment to form a protective surface layer may be performed (block 335, Figure 1F) prior to the soft-landing etch (block 340).
• subsequent fabrication process steps e.g., gate spacer formation
• fabricating a semiconductor device maybe performed (block 350).
• FIG 3B another process flow 32 starts with a cyclic plasma process 312 comprising, as a main etch, etching a polysilicon layer to form a recess by exposing the substrate to a first plasma comprising hydrogen bromide (HBr) and dichlorine (Cl 2 ) for a first duration (block 322, Figure 1C).
• a first plasma comprising hydrogen bromide (HBr) and dichlorine (Cl 2 ) for a first duration
• the substrate maybe exposed to a second plasma comprising dihydrogen (H 2 ) for a second duration (block 332, Figure 1D).
• the main etch and the hydrogen treatment maybe repeated for any number of times to extend the recess (e.g., Figure 1E).
• a surface treatment to form a protective surface layer may be performed (block 335, Figure 1F), followed by a soft- landing etch, where the substrate may be exposed to a third plasma comprising hydrogen bromide (HBr) and dichlorine (Cl 2 ) for a third duration (block 342, Figure 1G).
• HBr hydrogen bromide
• Cl 2 dichlorine
• yet another process flow 34 starts with forming a fin feature comprising a find hard mask and a silicon fin over an oxide layer (block 301).
• a dummy gate material comprising polysilicon may be deposited (block 302), followed by depositing a gate hard mask layer over the dummy gate material (block 303).
• a photoresist is then deposited (block 304) and patterned by performing a photolithographic process (block 305, Figure 2A).
• the gate hard mask layer maybe etched next to transfer the pattern from the photoresist to the hard mask layer (block 306, Figure 2B).
• a cyclic plasma process may follow to etch the dummy gate material using the patterned gate hard mask layer as an etch mask.
• the cyclic plasma process may start with a main etch by exposing the substrate to a first plasma comprising a halogen to form or extend a recess in the dummy gate material (block 324).
• a hydrogen treatment the substrate may be exposed to a second plasma comprising hydrogen (block 334).
• the main etch and the hydrogen treatment may be repeated for any number of times to extend the recess.
• the cyclic plasma process maybe continued until the top surfaces of the fin hard mask are exposed at the bottom of the recess (e.g., Figure 2C).
• the process flow 34 continues for a surface treatment to form a protective surface layer (block 335, Figure 2D), followed by a soft- landing etch, where the substrate may be exposed to a third plasma comprising a halogen (block 344, Figure 1G).
• the soft-landing etch may extend the recess to expose the oxide layer.
• Example 1 A method of processing a substrate that includes: performing a cyclic plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching a patterning layer including a polycrystalline semiconductor material to form or extend a recess by exposing the substrate to a first plasma, the substrate including an oxide layer, the patterning layer formed over the oxide layer, exposing the substrate to a second plasma, the second plasma including dihydrogen, and extending the recess by exposing the substrate to a third plasma, the second plasma being different from the first plasma and the third plasma.
• Example 2 The method of example 1, further including, before performing the cyclic plasma etch process, forming a patterned hard mask layer over the patterning layer by a lithographic process and an etch, and where the cyclic plasma etch process is performed using the hard mask layer as an etch mask.
• Example 3 The method of one of examples 1 or 2, further including, after performing the cyclic plasma etch process and before extending the recess by exposing the substrate to the third plasma, performing a surface treatment to form a protective surface layer on surfaces of the recess, the protective surface layer protecting sidewalls of the recess during extending the recess by exposing the substrate to the third plasma.
• Example 4 The method of one of examples 1 to 3, where the surface treatment includes exposing the substrate to a reactive gas, the reactive gas including oxygen, and where the protective surface layer include an oxide.
• Example 5 The method of one of examples 1 to 4, where the surface treatment includes exposing the substrate to a reactive gas, the reactive gas including nitrogen, and where the protective surface layer include a nitride.
• Example 6 The method of one of examples 1 to 5, where the first plasma includes a halogen.
• Example 7 The method of one of examples 1 to 6, where the first plasma includes hydrogen bromide and dichlorine.
• Example 8 The method of one of examples 1 to 7, where exposing the substrate to the second plasma amorphizes the polycrystalline semiconductor material at surfaces of the recess.
• Example 9 The method of one of examples 1 to 8, where exposing the substrate to the second plasma smoothens surfaces of the sidewalls of the recess.
• Example 10 The method of one of examples 1 to 9, where the third plasma includes a halogen.
• Example 11 The method of one of examples 1 to 10, where the third plasma includes hydrogen bromide and dichlorine.
• Example 12 The method of one of examples 1 to 11, where an etch rate of the polycrystalline semiconductor material during exposing the substrate to the third plasma is slower than an etch rate of the polycrystalline semiconductor material during exposing the substrate to the first plasma.
• Example 13 The method of one of examples 1 to 12, where the recess extended by exposing the substrate to the third plasma has a height -to-width ratio between about 5 to 10.
• Example 14 A method of processing a substrate that includes: performing a cyclic plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching a polysilicon layer to form a recess by exposing the substrate to a first plasma for a first duration, the substrate including an oxide layer, the polysilicon layer formed over the oxide layer, the first plasma including hydrogen bromide and dichlorine, and exposing the substrate to a second plasma for a second duration, the second plasma including dihydrogen.
• Example 15 The method of example 14, where the first duration is between 5 s to 120 s, and where the second duration is between 2 s to 50 s.
• Example 16 The method of one of examples 14 or 15, where exposing the substrate to the second plasma amorphizes the polysilicon layer at surfaces of the recess and reduce a standard deviation of critical dimensions of the recess at different depths by 20% or more.
• Example 17 The method of one of examples 14 to 16, further including, after performing the cyclic plasma etch process: performing a surface treatment to form a protective surface layer on surfaces of the recess; and further extending the recess in the layer by an etch process including exposing the substrate including a third plasma for a third duration, the third plasma including hydrogen bromide and dichlorine, the protective surface layer protecting sidewalls of the recess from the third plasma.
• Example 18 The method of one of examples 14 to 17, where the third duration is longer than the first duration.
• Example 19 A method of fabricating a fin field-effect transistor that includes: forming a fin feature over an oxide layer, the oxide layer formed over the substrate, the fin feature including a fin hard mask and a fin under the fin hard mask, the fin including silicon; depositing a dummy gate material including polysilicon; depositing a gate hard mask layer over the dummy gate material; depositing a photoresist over the hard mask layer; performing a photolithographic process to pattern the photoresist; etching the gate hard mask layer to transfer a pattern from the photoresist to the hard mask layer; and performing a cyclic plasma etch process using the gate hard mask layer as an etch mask, the cyclic plasma etch process exposing the fin hard mask, the cyclic plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching the dummy gate material to form a recess by exposing the substrate to a first plasma, the first plasma including a halogen; and exposing the substrate to
• Example 20 The method of example 19, further including, after performing the cyclic plasma etch process, extending the recess by exposing the substrate to a third plasma, the third plasma including a halogen, where performing the cyclic plasma etch process exposes top surfaces of the fin hard mask, and where extending the recess by exposing the substrate to the third plasma exposes the oxide layer.

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