JP2024531904A5 - - Google Patents

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Publication number
JP2024531904A5
JP2024531904A5 JP2024505580A JP2024505580A JP2024531904A5 JP 2024531904 A5 JP2024531904 A5 JP 2024531904A5 JP 2024505580 A JP2024505580 A JP 2024505580A JP 2024505580 A JP2024505580 A JP 2024505580A JP 2024531904 A5 JP2024531904 A5 JP 2024531904A5
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JP
Japan
Prior art keywords
input
signal
output
multiplexer
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024505580A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024531904A (ja
Filing date
Publication date
Priority claimed from US17/396,046 external-priority patent/US11971741B2/en
Application filed filed Critical
Publication of JP2024531904A publication Critical patent/JP2024531904A/ja
Publication of JP2024531904A5 publication Critical patent/JP2024531904A5/ja
Pending legal-status Critical Current

Links

JP2024505580A 2021-08-06 2022-07-06 経時変化の緩和 Pending JP2024531904A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/396,046 2021-08-06
US17/396,046 US11971741B2 (en) 2021-08-06 2021-08-06 Aging mitigation
PCT/US2022/036199 WO2023014460A1 (en) 2021-08-06 2022-07-06 Aging mitigation

Publications (2)

Publication Number Publication Date
JP2024531904A JP2024531904A (ja) 2024-09-03
JP2024531904A5 true JP2024531904A5 (https=) 2025-06-17

Family

ID=82748577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024505580A Pending JP2024531904A (ja) 2021-08-06 2022-07-06 経時変化の緩和

Country Status (8)

Country Link
US (1) US11971741B2 (https=)
EP (1) EP4381603A1 (https=)
JP (1) JP2024531904A (https=)
KR (1) KR20240039133A (https=)
CN (1) CN117769805A (https=)
PH (1) PH12023553288A1 (https=)
TW (1) TW202308319A (https=)
WO (1) WO2023014460A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11881862B2 (en) * 2021-08-17 2024-01-23 Qualcomm Incorporated Mitigation of duty-cycle distortion
US11967358B2 (en) * 2022-05-26 2024-04-23 Micron Technology, Inc. Apparatuses and methods for bias temperature instability mitigation
US20240235545A9 (en) * 2022-10-23 2024-07-11 Intel Corporation Adaptive clock gating for improving wear out-induced duty cycle shift in computer clock network

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU762154A1 (ru) * 1978-11-28 1980-09-07 Aleksandr M Botov Устройство определения временного положения основного максимума периодического сигнала 1
US5583461A (en) * 1994-09-19 1996-12-10 Advanced Micro Devices, Inc. Internal clock signal generation circuit having external clock detection and a selectable internal clock pulse
JPH09252252A (ja) * 1996-03-14 1997-09-22 Sanyo Electric Co Ltd D/a変換器
US5694056A (en) * 1996-04-01 1997-12-02 Xilinx, Inc. Fast pipeline frame full detector
US6275478B1 (en) * 1998-07-10 2001-08-14 Qualcomm Incorporated Methods and apparatuses for fast power control of signals transmitted on a multiple access channel
US6657979B1 (en) * 1999-08-23 2003-12-02 Motorola, Inc. Reduced power consumption multiplexer using self-decoding power down logic
JP3923715B2 (ja) * 2000-09-29 2007-06-06 株式会社東芝 メモリカード
US6864726B2 (en) * 2003-06-17 2005-03-08 Intel Corporation Output signal control from a DAC-driven amplifier-based driver
KR101136036B1 (ko) * 2003-12-24 2012-04-18 삼성전자주식회사 유휴 모드에서의 전력 소모가 감소된 프로세서 시스템 및그 방법
JP2005208259A (ja) * 2004-01-21 2005-08-04 Optrex Corp 有機elディスプレイ装置の駆動装置および駆動方法
US7760749B2 (en) * 2007-01-11 2010-07-20 Via Technologies, Inc. Apparatus and method for deskewing 1000 BASE-T Ethernet physical layer signals
DE102007006385B4 (de) * 2007-02-08 2019-02-14 Infineon Technologies Ag Eine Schaltkreis-Anordnung, ein Prozessor mit einer Schaltkreis-Anordnung, ein elektrisches Gerät und ein Verfahren zum Betreiben einer Schaltkreis-Anordnung
US7839194B2 (en) * 2007-11-21 2010-11-23 Rambus Inc. Clock circuitry for generating multiple clocks with time-multiplexed duty cycle adjustment
JP2012222497A (ja) * 2011-04-06 2012-11-12 Renesas Electronics Corp 受信回路及びエラー検出方法
KR101851614B1 (ko) * 2011-12-12 2018-06-12 삼성전자주식회사 기능블럭을 포함하는 SoC의 클락 제어 방법, 이를 구현한 SoC 및 이를 포함하는 반도체 시스템
JP2014093682A (ja) * 2012-11-05 2014-05-19 Denso Corp 通信システム
JP6032082B2 (ja) * 2013-03-25 2016-11-24 富士通株式会社 受信回路及び半導体集積回路
US9071235B2 (en) * 2013-10-18 2015-06-30 Micron Technology, Inc. Apparatuses and methods for changing signal path delay of a signal path responsive to changes in power
US9500700B1 (en) * 2013-11-15 2016-11-22 Xilinx, Inc. Circuits for and methods of testing the operation of an input/output port
US9401223B2 (en) * 2014-05-09 2016-07-26 Oracle International Corporation At-speed test of memory arrays using scan
US9966960B2 (en) * 2014-12-17 2018-05-08 Silicon Laboratories Inc. Configurable logic circuit including dynamic lookup table
CN104639042B (zh) * 2014-12-24 2017-11-17 聚辰半导体(上海)有限公司 低功耗可调倍频器
US9606604B1 (en) * 2015-11-25 2017-03-28 Globalfoundries Inc. Energy efficient high-speed link and method to maximize energy savings on the energy efficient high-speed link
JP6639348B2 (ja) * 2016-07-20 2020-02-05 シナプティクス・ジャパン合同会社 表示制御デバイス及び表示パネルモジュール
US10110229B1 (en) * 2017-06-06 2018-10-23 Intel Corporation Aging-resistant signal path circuitry
US10878879B2 (en) * 2017-06-21 2020-12-29 Mediatek Inc. Refresh control method for memory system to perform refresh action on all memory banks of the memory system within refresh window
TWI739269B (zh) * 2020-01-08 2021-09-11 瑞昱半導體股份有限公司 適應信號輸入模態的信號接收裝置及其信號處理方法

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